SHARP LHF80V13

PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F800BVHE-BTL90
Flash Memory
8M (1M ×8/512K x 16)
(Model No.: LHF80V13)
Spec No.: EL109049A
Issue Date: December 1, 1998
SHARP
LHFSOV13
l Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.
l When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).
*Office electronics
*Instrumentation and measuring equipment
*Machine tools
*Audiovisual equipment
*Home appliance
l Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands high reliabilitv, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
*Control and safety devices for airplanes, trains, automobiles,
transportation equipment
*Mainframe computers
@Traffic control systems
@Gasleak detectors and automatic cutoff devices
*Rescue and security equipment
*Other safety devices and safety equipment, etc.
and other
(3) Do not use the products covered herein for the following equipment which demands
extremelv high performance in terms of functionality, reliability, or accuracy.
*Aerospace equipment
l Communications equipment for trunk lines
*Control equipment for the nuclear power industry
l Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
aPlease direct all queries regarding the products covered herein to a sales representative of the
company.
Rev. 1.01
SHARP
1
LHF8OVl3
CONTENTS
PAGE
PAGE
............................................................ 3
1 INTRODUCTION..
1.1 Features ........................................................................
3
1.2 Product Overview. ........................................................ 3
5 DESIGN CONSIDERATIONS
...................................... 20
5.1 Three-Line Output Control ....................................... 20
5.2 RY/BY# and Block Erase and Word/Byte Write
Polling.. ....................................................................
20
OF OPERATION.. ..................................... .7
5.3 Power Supply Decoupling ........................................ 20
2.1 Data Protection.. ........................................................... 8
5.4 V,, Trace on Printed Circuit Boards ........................ 20
2 PRINCIPLES
5.5 V,,,
........................................................... .8
3,BUS OPERATION
3.1 Read ..............................................................................
8
V,,
RP##Transitions.. ..................................... 21
5.6 Power-Up/Down
Protection.. .................................... 21
5.7 Power Dissipation ..................................................... 21
3.2 Output Disable.. ............................................................ 8
3.3 Standby.. .......................................................................
8
6 ELECTRICAL
SPECIFICATIONS
............................... 22
...................................................... .8
6.1 Absolute Maximum Ratings ..................................... 22
3.5 Read Identifier Codes Operation.. ............................... .9
6.2 Operating Conditions ................................................ 22
9
6.2.1 Capacitance ......................................................... 22
3.4 Deep Power-Down
3.6 Write .............................................................................
6.2.2 AC Input/Output Test Conditions ....................... 23
.......................................... .9
6.2.3 DC Characteristics .............................................. 24
4.1 Read Array Command ................................................ 12
6.2.4 AC Characteristics - Read-Only Operations.. ..... 26
4.2 Read Identifier Codes Command ............................... 12
6.2.5 AC Characteristics - Write Operations ............... 29
4.3 Read Status Register Command.. ............................... 12
6.2.6 Alternative CE#-Controlled Writes.. ................... 3 1
4.4 Clear Status Register Command.. ............................... 12
6.2.7 Reset Operations ................................................. 33
4.5 Block Erase Command. .............................................. 12
6.2.8 Block Erase and Word/Byte Write Performance 34
4 COMMAXD
DEFINITIONS..
4.6 Word/Byte Write Command.. ..................................... 13
4.7 Block Erase Suspend Command ................................ 13
7 PACKAGE AND PACKING
SPECIFICATIONS..
...... .35
4.8 Word/Byte Write Suspend Command.. ...................... 14
4.9 Considerations of Suspend ......................................... 14
4.10 Block Locking .......................................................... 14
4.10.1 V,,=V,,
for Complete Protection.. .................... 14
4.10.2 WP#=V,, for Block Locking.. ............................ 14
4.10.3 WP#=V,,
for Block Unlocking.. ........................ 14
Rev. 1.0
SHARP
LHF8OV13
2
LH28F8OOBVHE-BTL90
8M-BIT (1Mbit x 8 / 512Kbit x 16)
Smart3 Flash MEMORY
n Smart3 Technology
- 2.7V-3.6V Vcc
- 2.7V-3.6V or 11.4V-12.6V Vpp
n User-Configurable
x8 or x 16 Operation
n High-Performance Access Time
- 90ns(2.7V-3.6V)
n Operating Temperature
- -40°C to +85”C
n Optimized Array Blocking Architecture
- Two 4k-word Boot Blocks
- Six 4k-word Parameter Blocks
- Fifteen 32k-word Main Blocks
- Bottom Boot Location
n Extended Cycling Capability
- 100,000 Block Erase Cycles
n Enhanced Automated Suspend Options
- Word/Byte Write Suspend to Read
- Block Erase Suspend to Word/Byte Write
- Block Erase Suspend to Read
n Enhanced Data Protection Features
- Absolute Protection with Vpp=GND
- Block Erase and Word/Byte Write Lockout
during Power Transitions
- Boot Blocks Protection with WP#=VIL
n Automated Word/Byte Write and Block Erase
- Command User Interface
- Status Register
n Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode Decreases
ICC in Static Mode
n SRAM-Compatible Write Interface
n Industry-Standard Packaging
- 48-Lead TSOP
n ETOXTM” Nonvolatile Flash Technology
n CMOS Process (P-type silicon substrate)
w Not designed or rated as radiation hardened
SHARP’s LH28F800BVHE-BTL90
Flash memory with Smart3 technology is a high-density, low-cost, nonvolatile, read/write
storage solution for a wide range of applications. LH28F800BVHE-BTL90
can operate at V,,=2.7V-3.6V
and
V,=2.7V-3.6V.
Its low voltage operation capability realize battery life and suits for cellular phone application.
[ts Boot, Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible
component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal
solution for code + data storage applications. For secure code storage applications, such as networking, where code is either
directly executed out of flash or downloaded to DRAM, the LH28F800BVHE-BTL90
offers two levels of protection: absolute
protection with V,, at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their
code security needs.
Ihe LH28F800BVHE-BTL90
is manufactured on SHARP’s 0.35pm ETOXTM* process technology. It come in industrystandard package: the 48-lead TSOP ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 1.01
SHARP
LHF8OV13
1 INTRODUCTION
This datasheet contains LH28F8OOBVHE-BTL90
specifications. Section 1 provides a flash memory
overview. Sections 2,3,4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F800BVHE-BTL90
Flash memory are:
Smart3
*Smart3 Technology
3
eliminates the need for a separate 12V converter, while
V,=l2V
maximizes block erase and word/byte wriu
performance. In addition to flexible erase and prograrr
voltages, the dedicated V,, pin gives complete datr
protection when V,, 5 VPPLK.
Table 1. V,, and V,, Voltage Combinations Offered by
Smart3 Technology
V,, Voltage
V,, Voltage
2.7V-3.6V, 11.4V- 12.6V
~
2.7V-3.6V
Internal V,, and V, detection Circuitry automatically
configures the device for optimized read and write
operations.
*Enhanced Suspend Capabilities
*Boot Block Architecture
Please note following important differences:
l VPPLK has been lowered
to 1.5V to support 2.7V-3.6V
block erase and word/byte write operations. The V,
voltage transitions to GND is recommended for
designs that switch V,, off during read operation.
*To take advantage of Smart3 technology, allow V,,
and V,,, connection to 2.7V-3.6V.
1.2 Product
Overview
The LH28F800BVHE-BTL90
is a high-performance 8Mbit Smart3 Flash memory organized as lM-byte of 8
bits or 512K-word of 16 bits. The lM-byte/512K-word
of
data is arranged in two 8K-byte/4K-word boot blocks, six
8K-byte/4K-word
parameter blocks and fifteen 64Kbyte/32K-word
main blocks which are individually
erasable in-system. The memory map is shown in Figure
3.
Smart3 technology provides a choice of V,, and V,,
combinations, as shown in Table 1, to meet system
performance and power expectations. V, at 2.7V-3.6V
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word/byte write
operations.
A block erase operation erases one of the device’s 32Kword blocks typically within 0.51s (2.7V-3.6V V,,,
11.4V-12.6V V,,), 4K-word blocks typically within 0.3 1s
(2.7V-3.6V V,,, 11.4V- 12.6V V,,) independent of other
blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software
to suspend block erase to read or write data from any other
block.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 12.6~s (2.7V-3.6V V,,, 11.4V-12.6V V,,), 4Kword blocks typically within 24.5us (2.7V-3.6V V,,,
11.4V-12.6V V,,).
Word/byte write suspend mode
enables the system to read data or execute code from any
other flash memory array location.
Rev. 1.1
LHF8OV13
The boot blocks can be locked for the WP# pin. Block
erase or word/byte write for boot block must not be carried
out by WP# to Low and RP# to V,
The status register indicates when the WSM’s block erase
or word/byte write operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase or word/byte
write. RY/BY#-high Z indicates that the WSM is ready for
a new command, block erase is suspended (and word/byte
write is inactive), word/byte write is suspended, or the
device is in deep power-down mode.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static modt
(addresses not switching). In APS mode, the typical I,,
current is 3 mA at 2.7V V,,.
When CE# and RP# pins are at V,,, the I,, CM05
standby mode is enabled. When the RP# pin is at GND
deep power-down
mode is enabled which minimize:
power consumption and provides write protection during
reset. A reset time (tpHQv) is required from RP# switching
high until outputs are valid. Likewise, the device has :
from RP#-high until writes to the CUI
wake time (tp&
are recognized. With RP# at GND, the WSM is reset ant
the status register is cleared.
The device is available in 48-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in Figure
2.
The access time is 90 ns (tAv v> over the extended
temperature range (-40°C to +880 C) and V,, supply
voltage range of 2.lV-3.6V.
Rev. 1.0
SHARP
LHF8OV13
5
a3
WE#
OE#
RP#
WP#
I
1
Y
Decoder
Y-Gating
I
Write
)
I
RYiBY#
Figure 1. Block Diagram
AIS c== 1
A14
A13
A12
I
2
I
:
15
:
3
4
6
=
7
I
I
8
9
10
11
12
13
14
1.5
41
ho
A9
As
NC
NC
wE#
RP#
VPP
WP#
RYIBY#
48
16
17
18
19
A17
A7
%
2
A3
A2
A,
I
I
I
0
48-LEAD TSOP
STANDARD
PINOUT
12mm x 20mm
TOP VIEW
20
21
22
23
24
48
47
46
45
44
43 a
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
21 I
26 I
25 I
A16
BYTE#
GND
DQdAI
DQ7
DQM
DQ6
DQI~
DQs
DQIZ
DQ4
VCC
DQI
DQ3
DQIO
DQ2
DQg
DQ1
DQs
OE#
DQo
GND
CE#
A0
Figure 2. TSOP 48-Lead Pinout
Rev. 1.0
SHARP
LHF8OV13
Symbol
A-1
Ao-Al
8
DQu-DQls
CE#
RP#
OE#
WE#
WP#
BYTE#
RY/BY#
VPP
Vcc
GND
NC
Table 2. Pin Descriptions
Name and Function
‘Me
ADDRESS INPUTS: Addresses are internally latched during a write cycle.
: Byte Select Address. Not used in x16 mode.
A-1
INPUT
Au-A ,u : Row Address. Selects 1 of 2048 word lines.
A,,-A,,
: Column Address. Selects 1 of 16 bit lines.
A,5-A,8 : Main Block Address. (Boot and Parameter block Addresses are A,2-A,8.)
DATA INPUT/OUTPUTS :
DQo-DQ7:Inputs data and commands during CUI write cycles; outputs data during memory array,
status register and identifier code read cycles. Data pins float to high-impedance when the chip is
INPUT/
deselected or outputs are disabled. Data is internally latched during a write cycle.
OUTPUT DQs-DQrs:Inputs data during CUI write cycles in x16 mode; outputs data during memory array
read cycles in x 16 mode; not used for status register and identifier code read mode. Data pins float
to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode (Byte#=V,,).
Data is internally latched during a write cycle.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal
automation. RP#/-high enables normal operation. When driven low, RP# inhibits write operations
which provides data protection during power transitions. Exit from deep power-down sets the
INPUT
device to read array mode. With RP#=V HH, block erase or word/byte write can operate to all
blocks without WP##state. Block erase or word/byte write with V,,<RP#<VHH produce spurious
results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
INPUT
the rising edge of the WE# pulse.
WRITE PROTECT: Master control for boot blocks locking. When VI,. locked boot blocks cannot
INPUT
be erased and programmed.
BYTE ENABLE: BYTE# V,, places device in x8 mode. All data is then input or output on DQ,-,,
INPUT
and DQ8-15 float. BYTE# VIH places the device in x16 mode , and turns off the A-, input buffer.
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an
OPEN
internal operation (block erase or word/byte write). RY/BY#-high Z indicates that the WSM is
DRAIN
ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte
OUTPUT
write is suspended, or the device is in deep power-down mode.
BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or
writing words/bytes.With V,,<V,,,,,
memory contentscannotbe altered.Block eraseand
SUPPLY
word/byte write with aninvalid V,, (seeDC Characteristics)producespuriousresultsand should
not be attempted.
DEVICE POWER SUPPLY: Do not float any power pins. With VcclV,KO,
all write attempts to
SUPPLY the flash memoryare inhibited. Device operationsat invalid V,, voltage (seeDC Characteristics)
producespuriousresultsandshouldnot be attempted.
SUPPLY
GROUND:
Do not float any ground pins.
NO CONNECT: Lead is not internal connected;it may be driven or floated.
Rev. 1.1
SHARP
LHF8OV13
7
2 PRINCIPLES OF OPERATION
Bottom
The LH28F8OOBVHE-BTL90
Smart3 Flash memory
includes an on-chip WSM to manage block erase and
word/byte write functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block erasure
and word/byte write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep powerdown mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the VP, voltage. High
voltage on VP, enables successful block erasure and
word/byte writing. All functions associated with altering
memory contents-block erase, word/byte write, status and
identifier codes-are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and word/byte write.
The internal algorithms are regulated by the WSM,
including pulse repetition, internal verification and
margining of data. Addresses and data are internally latch
during write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or outputs
status register data.
Interface software that initiates and polls progress of block
erase and word/byte write can be stored in any block. This
code is copied to and executed from system RAM during
flash memory updates. After successful completion, reads
are again possible via the Read Array command. Block
erase suspend allows system software to suspend a block
erase to read/write data from/to blocks other than that
which is suspend. Word/byte write suspend allows system
software to suspend a word/byte write to read data from
any other flash memory array location.
Boot
7FFFF
78000
77FFF
7maO
6FFFF
68000
67FFF
58OCO
57FFF
48OCQ
47FFF
28000
27FFF
2OOa
1FFFF
18000
17FFF
08000
07FFF
07OQO
06FFF
0%
05000
04FFF
04000
03FFF
03000
02FFF
02Om
OIFFF
OloOa
OOFFF
omoo
4K-word Parameter Block
2
4K-word Parameter Block
1
4K-word Parameter Block
0
4K-word Boot Block
1
4K-word Boot Block
0
Figure 3. Memory Map
Rev. 1.0
SHARI=
LHF8OV13
8
2.1 Data Protection
3.2 Output Disable
Depending on the application, the system designer may
choose to make the V,
power supply switchable
(available only when memory block erases or word/byte
writes are required) or hardwired to V,,,,,.
The device
accommodates either design practice and encourages
optimization of the processor-memory interface.
With OE# at a logic-high level (V,,), the device output
are disabled. Output pins (DQu-DQ15) are placed in a
high-impedance state.
When VppIVppLK, memory contents cannot be altered.
The CUI, with two-step block erase or word/byte write
command sequences, provides protection from unwanted
operations even when high voltage is applied to V,,. All
write functions are disabled when V,, is below the write
lockout voltage VLKO or when RP# is at V,,. The device’s
boot blocks locking capability for WP# provides
additional protection from inadvertent code or data
alteration by block erase and word/byte write operations.
Refer to Table 6 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the V,, voltage. RP# can
be at either VI, or V,.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from deep power-down mode, the device
automatically resets to read array mode. Six control pins
dictate the data flow in and out of the component: CE#,
OE#, WE#, RP#, WP# and BYTE#. CE# and OE# must be
driven active to obtain data at the outputs. CE# is the
device selection control, and when active enables the
selected memory device. OE# is the data output
(DQo-DQls) control and when active drives the selected
memory data onto the I/O bus. WE# must be at Vt, and
RP# must be at V,, or V,,. Figure 11, 12 illustrates read
cycle.
3.3 Standby
CE# at a logic-high level (V,,) places the device in
standby mode which substantially reduces device power
consumption. DQo-DQ,, outputs are placed in a highimpedance state independent of OE#. If deselected during
block erase or word/byte write, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at V, initiates the deep power-down
mode.
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum 01
100 ns. Time tpHQv is required after return from powerdown until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase or word/byte write modes, RP#-low
will abort the operation. RY/BY# remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tpHWL is required after RP# goes
to logic-high (V,,) before another command can be
written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase or word/byte write modes. If a CPU
reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array data.
SHARP’s flash memories allow proper CPU initialization
following a system reset through the use of the RP# input.
In this application, RP# is controlled by the same RESET#
signal that resets the system CPU.
Rev. 1.0
SHARI=
LHF8OV13
9
3.5 Read Identifier Codes Operation
3.6 Write
The read identifier codes operation outputs the
manufacturer code and device code (see Figure 4). Using
the manufacturer and device codes, the system CPU can
automatically match the device with its proper algorithms.
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V,,=2.7V-3.6V
and
V,=V,,,,,
the CUI additionally controls block erasure
and word/byte write.
LGA01
.
7*
:;:,::.,,,..
,:’,..,:,
:: .f:‘::,’,;’.:;j, ;:; : ,;.,,,:,:;y):::j,:.:.: ::,::,,:I,..,:;‘.$
.I..,.,
:.‘;:. : ..:.,:,...,.. .,,,:
j
,,,::,,:
,..,
‘.
,:,.
: ....‘. ..
:>:: ,.,. :: .:,.j..y::‘..
.. .:..
.. ...:’
:,,‘,y:.
.‘.,,.:,‘,.,‘j’.
:,,,:::,::
,.‘,‘.
....:., ‘:. :; :. :
.:...
:,. :.:..I..‘/./..,..I.,.,
,.
:
.;y.:.
,:i,..
.,,:.,,.
: .d:.:‘....:..,:,.:,‘j..
.. . .-:,; : ,,,,,..,:.I.‘.’.:.. . .,,,,:.:. . . .ji
.
.... ..A..
The Block Erase command requires appropriate command
data and an address within the block to be erased. The
WordByte Write command requires the command and
address of the location to be written.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
‘on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 13 and 14 illustrate WE# and CE# controlled write
operations.
4 COMMAND
DEFINITIONS
Figure 4. Device Identifier Code Memory Map
When the V, voltage I V,,,,
Read operations from the
status register, identifier codes, or blocks are enabled.
Placing VPPHIR on V,, enables successful block erase
and word/byte write operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these commands.
Rev. 1.0
SHARP
LHFSOV13
Deep Power-Down
Read Identifier Codes
4,lO
v,
X
8
!$Hor
10
X
X
v,
v,
VI,
X
See
Figure 4
V,
VI,
VIL
X
I-m
6,7,8
Write
“:”
Or
HH
Mode
Read
Notes
8
Deep Power-Down
Read Identifier Codes
vIH
Or
VHH
‘1,
Output Disable
Standby
Table 3.2. Bus Operations(BYTE#=Vn.)(*,2)
CE#
OE#
WE#
Address
RP##
V,
10
4,lO
8,9
“:”
Or
Or
HI-l
VI,
“:”
Or
76-m
IuII2s:
677 78
‘IHor
VI-II-I
High Z
High Z
X
Note 5
High Z
X
DIN
DQ,-7
DQ,-1,
RY/BY#c3)
X
VIL
VIL
VIH
X
X
D,,,
High Z
X
VIL
vIH
vIH
X
X
High Z
High Z
X
X
X
X
X
HighZ
High Z
X
X
X
X
X
High Z
High Z
High Z
V,
V,
vIH
X
See
Figure 4
X
Note 5
High Z
High Z
VIL
vIH
vIL
X
X
X
X
‘1,
HI-l
Write
VP,
X
,
DIN
. Refer to DC Characteristics. When V,r,5V,PLK, memory contents can be read, but not altered.
and
!. X can be Vu or VrB for control pins and addresses, and V,,
or V,,,z
for V,. See DC Characteristics for V,,,
vPPHI/2 voltages.
1, RY/BY# is V,, when the WSM is executing internal block erase or word/byte write algorithms. It is High Z during when
the WSM is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or
deep power-down mode.
‘. RP# at GNDk0.2V ensures the lowest deep power-down current.
‘. See Section 4.2 for read identifier code data.
I. Command writes involving block erase or word/byte write are reliably executed when VPP=VPPHrjz and V,--=2.7V-3.6V.
Block erase or word/byte write with VnrcRP#<V,
produce spurious results and should not be attempted.
. Refer to Table 4 for valid DIN during a write operation.
Never hold OE# low and WE# low at the same timing.
~1 A-1 set to VI, or VlB in byte mode (BYTE#=Vu).
0. w# set to vL or VI,.
Rev. 1.0
SHARP
LHF8OV13
Table 4. Command Detinitions(7)
NOTES:
1. BUS operations are defined in Table 3.1 and Table 3.2.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4. A-, set to V, or V,, in Byte Mode (BYTE#=V,).
BA=Address within the block being erased. The each block can select by the address pin A,, through A,, combination.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for
read identifier code data.
5. If the block is boot block, WP# must be at V, or RP# must be at V,, to enable block erase or word/byte write
operations. Attempts to issue a block erase or word/byte write to a boot block while WP# is V,, or RP# is V,,.
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 1.0
SHARP
LHF8OV13
12
4.1 Read Array Command
4.4 Clear Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase or word/byte write, the device will
not recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via
an Erase Suspend or Word/Byte Write Suspend command.
The Read Array command functions independently of the
V, voltage and RP# can be V,, or V,.
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
“1”s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 7). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
sequence) may be performed. The status register may bc
polled to determine if an error occurred during the
sequence.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer and device codes (see Table 5
for identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command functions
independently of the V, voltage and RP# can be V, or
V,. Following the Read Identifier Codes command, the
following information can be read:
Table 5. Identifier Codes
4.3 Read Status Register Command
The status register may be read to determine when a block
erase or word/byte write is complete and whether the
speration completed successfully. It may be read at any
ime by writing the Read Status Register command. After
writing this command, all subsequent read operations
output data from the status register until another valid
:ommand is written. The status register contents are
atched on the falling edge of OE# or CE#, whichever
occurs. OE# or CE# must toggle to V, before further
.eads to update the status register latch. The Read Status
tegister command functions independently of the V,,
{ohage. RP# can be V,, or V,,.
To clear the status register, the Clear Status Regista
command (50H) is written. It functions independently o
the applied V,, Voltage. RP# can be V,, or V,,. Thi:
command is not functional during block erase OI
.word/byte write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by i
two-cycle command. A block erase setup is first written
followed by an block erase confirm. This commanc
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the
device automatically outputs status register data when read
(see Figure 5). The CPU can detect block erase completion
by analyzing the output data of the RY/BY# pin or status
register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to “1”. Also, reliable block erasure can only occur when
V,,=2.7V-3.6V
and VPP=VPPH1,2. In the absence of this
high voltage, block contents are protected against erasure.
If block erase is attempted while V,,IV,,,,,
SR.3 and
SR.5 will be set to “1”. Successful block erase for boot
blocks requires that the corresponding if set, that
WP#=V,
or RP#=V,,.
If block erase is attempted to
boot block when the corresponding WP#=V,,
or
RP#=V,,, SR.l and SR.5 will be set to “1”. Block erase
operations with V,,<RP#<V,,
produce spurious results
and should not be attempted.
Rev. 1.0
SHARI=
LHF8OV13
13
4.6 Word/Byte Write Command
4.7 Block Erase Suspend Command
Word/byte write is executed by a two-cycle command
sequence. Word/byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
The Block Erase Suspendcommandallows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block-eraseprocessstarts,
writing the Block Erase Suspendcommandrequeststhat
the WSM suspend the block erase sequence at a
predeterminedpoint in the algorithm. The device outputs
status register data when read after the Block Erase
Suspendcommandis written. Polling statusregister bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended(both will be set to “1”).
RY/BY# will also transition to High Z. Specification
twHRz2definesthe block erasesuspendlatency.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for “1”s that do not successfully write
to “0”s. The CUI remains in read status register mode until
it receives another command.
Reliable word/byte
writes can only occur when
V,,=2.7V-3.6V
and VPP=VPPH,,2. In the absence of this
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V,,IV,,,
status register bits SR.3 and SR.4 will be set
to “1”. Successful word/byte write for boot blocks requires
that the corresponding if set, that WP#=V,, or RP#=V,.
If word/byte write is attempted to boot block when the
corresponding WP#=V, or RP#=V,,, SR.1 and SR.4 will
be set to “1”. Word/byte write operations with
V,&P#<V,
producespuriousresultsandshouldnot be
attempted.
At this point, a Read Array commandcan be written to
,readdata from blocks other than that which is suspended.
A Word/Byte Write commandsequencecan alsobe issued
during erase suspendto program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.8), a word/byte write operation can also be
suspended.
During a word/byte write operationwith block
erasesuspended,statusregisterbit SR.7 will return to “0”
and the RY/BY# output will transition to VOL. However,
SR.6 will remain “1” to indicate block erase suspend
status.
The only other valid commandswhile block erase is
suspendedare Read Status Register and Block Erase
Resume.After a Block EraseResumecommandis written
to the flash memory, the WSM will continue the block
erase process.Status register bits SR.6 and SR.7 will
automatically clear and RY/BY# will return to VOL. After
the Erase Resume command is written, the device
automatically outputs statusregister data when read (see
Figure 7). V, must remain at V,,,,,,
(the sameV,,
level usedfor block erase)while block eraseis suspended.
RP# mustalsoremainat V,, or V,, (the sameRP# level
usedfor block erase).WP# mustalsoremainat VIL or V,,
(the sameWP# level usedfor block erase).Block erase
cannot resumeuntil word/byte write operationsinitiated
during block erasesuspendhave completed.
Rev. 1.0
SHARP
14
LHF8OV13
4.8 Word/Byte Write Suspend Command
4.10 Block Locking
The Word/Byte
Write Suspend command allows
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts, writing the Word/Byte Write Suspend command
requests that the WSM suspend the word/byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to “1”). RY/BY# will also transition to
High Z. Specification twHRZl defines the word/byte write
suspend latency.
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte
Write
Resume command is written to the flash memory, the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear and
RYlBY# will return to V,,. After the Word/Byte Write
Resume command is written, the device automatically
outputs status register data when read (see Figure 8). V,,
must remain at V,,,,,
(the same V,, level used for
word/byte write) while in word/byte write suspend mode.
RP# must also remain at V, or V,, (the same RP# level
used for word/byte write). WP# must also remain at V, or
V, (the same WP# level used for word/byte write).
4.10.1 Vpp=v~
for Complete Protection
The V, programming voltage can be held low for
complete write protection of all blocks in the flash device.
4.10.2 WP#=V,, for Block Locking
The lockable blocks are locked when WP#=V,;
any
.program or erase operation to a locked block will result in
an error, which will be reflected in the status register. For
top configuration, the top two boot blocks are lockable.
For the bottom configuration, the bottom tow boot blocks
are lockable. Unlocked blocks can be programmed or
erased normally (Unless V, is below V,,,).
4.10.3 WP#=VIH for Block Unlocking
WP#=V,,
unlocks all lockable blocks.
These blocks can now be programmed or erased.
WP# controls 2 boot blocks locking and V,, provides
protection against spurious writes. Table 6 defines the
write protection methods.
4.9 Considerations of Suspend
After the suspend command write to the CUI, read status
register command has to write to CUI, then status register
bit SR.6 or SR.2 should be checked for places the device
in suspend mode.
Operation
Block Erase
or
Word/Byte Write
VP,
V,
RP#
X
VI,
“PPLK
‘HH
vlH
Table 6. Write Protection Alternatives
WP#
X
All Blocks Locked.
X
All Blocks Locked.
X
All Blocks Unlocked.
2 Boot Blocks Locked.
‘IL
All
Blocks Unlocked.
‘1,
Effect
Rev. 1.0
SHARP
LHF8OV13
WSMS
7
1
ESS
ES
6
5
15
Table 7. Status Register Definition
1 WBWS
1
1 WBWSS
VPPS
4
3
1
2
DPS
R
1
0
NOTES:
SR.7 = WRITE STATE MACHINE
1 = Ready
0 = Busy
Check RY/BY#
word/byte write
SR.7=“0”.
STATUS (WSMS)
or SR.7 to determine block erase OK
completion. SR.6-0 are invalid while
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are “1”s after a block erase attempt,
an improper command sequence was entered.
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = WORD/BYTE WRITE STATUS (WBWS)
1 = Error in Word/Byte Write
0 = Successful Word/Byte Write
SR.3 does not provide a continuous indication of V,, level.
The WSM interrogates and indicates the V,, level only after
Block Erase or Word/Byte Write command sequences. SR.3
is not guaranteed to reports accurate feedback only when
SR.3 = V, STATUS (VPPS)
1 = V, Low Detect, Operation Abort
O=V,OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
vPP~vPPHll2~
The WSM interrogates the WP# and RP# only after Block
Erase or Word/Byte Write command sequences. It informs
the system, depending on the attempted operation, if the
WI% is not V,, RP# is not V,.
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = WP# or RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
SR.0 is reserved for future use and should be masked out
when polling the status register.
.
Rev. 1.0
SHARP
LHF8OV13
Stan
BUS
operation
Write ?OH.
Block Address
Command
Data=?OH
Addr=Witbin
Block to be Erased
Write
Daca=WH
Ad&=Within
Block to be Erased
Read
Swtus Regater Data
Write
Erase Setup
Write DOH.
Block Address
Erase Loop
Comment.9
Check SR.7
l=WSM Ready
OzWSM Busy
standby
Repeat for subsequent block eraw,es.
Full sta& check can be done after each block erase or after a sequence of
block erawres.
Write FFH after the last operation 10 place devxe in read array mode.
Full Status
Check If Desired
FULL STATUS
CHECK PROCEDURE
BUS
operation
Read Status Register
Data(See Above)
Comments
Command
Standby
Check SR.3
l=Vpp Enor Detect
Standby
Check SR.1
I=Device Prolect Detect
Standby
Check SR.4.5
Both I=Command
staodhy
Check SR.5
l=Block Erase Error
Sequence Error
SR.jSR.4SR.3
and SR.1 are only cleared by the Clear Status
Register Command in cakes where multiple blocks are erased
&fore full status is checked.
If error is detected. clear the Sratw Register befae attempting
retry or mher error reccwery.
Block Erase Error
Block Erase Successful
Figure 5. Automated Block Erase Flowchart
Rev. 1.0
SHARI=
BUS
operation
Command
write
Setup Wordmyte
Write
Wri1e
Word/Byte Write
Dau=4OH OT 10H
Addr=Location m Be Wnlten
Datz=Daa to Be Written
Ad&Location
to Be Written
Status Register Data
Read
Check SR.7
l=WSM Ready
O=WSM Busy
Standby
Repeat for subsequent byte writes.
SR full s&s check can be done aiier each WordiByte mile. or after a sequence of
WcdByTe writes.
Write FFH after the last WadApe
mte operaooo to place- device m
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
BUS
operation
Comments
Command
Standby
Check SR.3
l=Vpp Error Detect
Standby
Check SR.l
l=Device Protect Detect
Standby
Check SR.4
l=Data Write Error
Device Protea Error
SR.4.SR.3 and SR. I are ooly cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
If error 1s detected. clear the Status Register before attempting
retry or other e*n recovery.
Figure 6. Automated Word/Byte Write Flowchart
Rev. 1.0
SHARP
LHF8OV13
BUS
operation
Command
write
EraJe
Suspend
Comments
Data=BOH
Addr-X
Siatuv Register Data
Ad&X
Read
Standby
Check SR.7
I=WSM Ready
O=WSM Busy
Standby
Check SR.6
I=Blwk Erase Suspended
OzBlock Erase Completed
Write
Erase
R&VJllle
Data=DOH
Addr=X
Figure 7. Block Erase Suspend/Resume Flowchart
Rev. 1.0
SHARP
19
LHF8OV13
BUS
operation
Comments
Command
Dau=BOH
Adh=X
Word/Byte Write
Suspend
Write
Status Register
I Addr-X
Read
I
Read Array
Data=FFH
Ad&=X
Word/Byte
Complet
Figure 8. Word/Byte Write Suspend/Resume Flowchart
Rev. 1.0
SHARP
LHF8OV13
20
5 DESIGN CONSIDERATIONS
5.3 Power Supply Decoupling
5.1 Three-Line Output Control
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1 $ ceramic capacitor
connected between its V,, and GND and between its V,,
and GND. These high-frequency,
low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7 pF
electrolytic capacitor should be placed at the array’s power
supply connection between V,, and GND. The bulk
capacitor will overcome voltage slumps caused by PC
board trace inductance’.
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD
should also
toggle during system reset.
5.2 RY/BY#, Block Erase and Word/Byte
Write Polling
RY/BY# is an open drain output that should be connected
to V,, by a pulllup resistor to provide a hardware method
of detecting block erase and word/byte write completion.
It transitions low after block erase or word/byte write
commands and returns to High Z when the WSM has
finished executing the internal algorithm.
5.4 Vpp Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V,, Power supply trace. The V,, pin
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V,, power bus. Adequate V,,
supply traces and decoupling will decrease V,, voltage
spikes and overshoots.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or deep power-down modes.
Rev. 1.1
SHARP
LHF8OV13
5.5 VCC, Vpp, RP# Transitions
Block erase and word/byte write are not guaranteed if V,,
falls outside of a valid V,,,,,, range, V,, falls outside of
a valid 2.7V-3.6V range, or RP##V,, or V,,. If V,, error
is detected, status register bit SR.3 is set to “1” along with
SR.4 or SR.5, depending on the attempted operation. If
RP# transitions to V, during block erase or word/byte
write, RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the device
will enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V, clear
the status register.
The CUI latches commands issued by system software and
is not altered by V, or CE# transitions or WSM actions.
Its state is read array mode upon power-up, after exit from
deep power-down or after V,, transitions below VLKo.
After block erase or word/byte write, even after V,,
transitions down to V,,,,: the CUI must be placed in read
array mode via the Read Array command if subsequent
access to the memory array is desired.
5.6 Power-Up/Down Protection
Ihe device is designed to offer protection against
accidental block erasure or word/byte writing during
power transitions. Upon power-up,
the device is
indifferent as to which power supply (V,, or V,,)
?owers-up first. Internal circuitry resets the CUI to read
uray mode at power-up.
21
A system designer must guard against spurious writes fol
V,- voltages above VLKO when V,, is active. Since botl
WE# and CE# must be low for a command write, driving
either to V,, will inhibit writes. The GUI’s two-steI
command sequence architecture provides added level 01
protection against data alteration.
WP# provide additional protection from inadvertent code
or data alteration. The device is disabled while RP#=V,
regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must considei
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering RP# to V, standby or sleep modes. If
access is again needed, the devices can be read following
wake-up cycles required after RP# is
*e ‘PHQV
and tPHWL
first raised to VI,. See AC Characteristics- Read Only
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
J
Rev. 1.0
SHARP
LHF8OV13
6 ELECTRICAL
SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase and
Word/Byte Write .. ..... ..... ...... ...... ..... .-40°C to +85”C(‘)
Temperature under Bias ......_.._._._........
-40°C to +85”C
Storage Temperature ... ..... ...... ...... ...... .... .. -65°C to +12X
Voltage On Any Pin
(except V,,, V,,, and RP#) . ...... ..... - 0.5v to +7.ov(*)
V,- Supply Voltage ... ..... .._................... -0.2v to +7.ovQ)
V, Update Voltage during Block
Erase and Word/Byte Write .... .... . -0.2V to +14.0V(2*3)
RF% Voltage .... ..... .... ..... ...... ..... ...... ..... -0.5V to +14.0V(2,3)
22
*WARNING:
Stressing the device beyond the “Absolutt
Maximum Ratings” may cause permanent damage. Thest
are stress ratings only. Operation beyond the “Operating
Conditions”
is not recommended and extended exposurt
beyond the “Operating
Conditions”
may affect devict
reliability.
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND
Minimum DC voltage is -0.5V on input/output pinr
and -0.2V on V,, and V,, pins. During transitions
this level may undershootto -2.OV for periods<20ns
Maximum DC voltage on input/output pinsand V,, is
V,,+O.5V which, during transitions,may overshoottc
Vcc+2.0V for periods<20ns.
3. Maximum DC voltage on V,, andRP##may overshool
to +14.OV for periodsc20ns.
4. Output shortedfor no morethan onesecond.No more
than one output shortedat a time.
Output Short Circuit Current ..... ...... .... ....... ....... ... lOOn~4(~)
6.2 Operating Conditions
TemperatureandV,, OperatingConditions
Symbol
Parameter
Min.
Max.
Unit
T,
OperatingTemperature
-40
+85
“C
V,,
V,, Supply Voltage (2.7V-3.6V)
2.7
3.6
V
Test Condition
Ambient Temperature
5.2.1 CAPACITANCE(l)
Symbol
Parameter
C,,
Input Capacitance
CO”,
Output Capacitance
VOTE:
1. Sampled,not 100%tested.
T,=+25”C, f=lMHz
Max.
TYP.
7
10
9
12
Unit
PF
pF
Condition
v,=o.ov
V,,,=o.OV
Rev. 1.0
SHARP
23
LHF8OV13
I
6.2.2 AC INPUT/OUTPUT
TEST CONDITIONS
AC test inputs are driven at 2.7V for a Logic “1” and O.OV for a Logic “0.” Input timing begins, and output timing ends, at 1.35V.
Input rise and fail times (10% to 90%) ~10 ns.
Figure 9. Transient Input/Output Reference Waveform for V,,=2.7V-3.6V
Test Configuration Capacitance Loading Value
Test Configuration
C,(pF)
30
V,,=2.7V-3.6V
lN914
CL Includes Jig
Capacitance
Figure 10. Transient Equivalent Testing Load
Circuit
Rev. 1.01
SHARP
LHF8OV13
24
5.2.3 DC CHARACTERISTICS
Sym.
IL1
Parameter
Input Load Current
IL0
Output Leakage Current
ICC,
V,, Standby Current
DC Characteristics
V,,=2.lV-3.6V
Notes
MaX.
TYP.
1
*OS
1
1,3,6,
10
Unit
PA
kO.5
ClA
25
50
ClA
0.2
2
mA
5
20
fl
15
25
mA
30
mA
17
mA
1,3,6
‘CC,
V,, Deep Power-Down
ICCR
V,, Read Current
kcw
Current
V,, Word/Byte Write Current
1,lO
1,576
1,7
5
Test
Conditions
VCC=VCCMax.
V,,=Vcc or GND
CMOS Inputs
V,,=V,,Max.
CE#=RP#=V,@.2V
TTL Inputs
VCC=VCCMax.
CE#=RP#=V,,
RP##=GND+0.2V
I,, (RY/BY#)=OmA
CMOS Inputs
VCC=VCCMax~C.,C=GND
f=SMHz, I,,
TTL Inputs
yc5=$IMax..
CE#=GND
=
OUT=OmA
V,=2.7;-3.6V
Rev. 1.0
SHARP
LHF8OV13
DC Characteristics (Continued)
V,,=2.7V-3.6V
Notes
Min.
Max.
VIH
Parameter
Input Low Voltage
Input High Voltage
VOL
Output Low Voltage
3,7
Output High Voltage
u-w
Output High Voltage
(CMOS)
3,7
SYm.
VI,
‘OH1
‘OH2
25
7
7
397
-0.5
0.8
Unit
V
2.0
+os
Vcc
V
0.4
V
V
2.4
0.85
V
V,,
V
!&
‘PPLK
‘PPHl
‘PPH2
V, Lockout Voltage during Normal
Operations
VP, Voltage during Word/Byte Write
or Block EraseOperations
V, Voltage during Word/Byte Write
or Block EraseOperations
V,, Lockout Voltage
RP# Unlock Voltage
4,7
1.5
V
2.7
3.6
V
11.4
12.6
V
Test Conditions
V,,=V,,
Min.
IoL=2.0mA
V,,=V,,
Min.
I,,=- 1.5d
V,,=V,,
Min.
I,,=-2.om.A
V,,=V,,
Min.
I,,=- lOOpA
2.0
V
V,
UnavailableWP#
11.4
12.6
V
83
JOTES:
. All currentsarein RMS unlessotherwisenoted.Typical valuesat nominalV,, voltage andT,=+25”C.
. ‘CCWS and ‘CCES are specifiedwith the device de-selected.If read or word/byte written while in erasesuspendmode.the
device’scurrentdraw is the sumof I,,,,
or ICC-sand ICCRor Iccw, respectively.
. IncludesRY/BY#.
. Block erasesandword/byte writes are inhibited when Vpp<VppLK, and not guaranteedin the rangebetweenVppr&max.)
and VppH,(min.), between Vpprn(max.) and VPPH2(min.), between VppH2(max.) and Vpp&nin.),
and above
VppH3@=).
. Automatic Power Savings(APS) reducestypical ICCRto 3mA at 2.7V V,, in static operation.
. CMOS inputsareeither V,,- +0.2V or GND+0.2V. TTL inputs areeither V, or VI,.
Sampled,not 100%tested.
Boot block erasesand word/byte writes are inhibited when the correspondingRP#=V,, and WP#=V,,. Block eraseand
word/byte write operationsare not guaranteed with V,,<RP#<V,
andshouldnot be attempted.
RF%connectionto a V, supplyis allowedfor a maximumcumulativeperiod of 80 hours.
0. BYTE# input level is V,,+o.2V in word modeor GND-cO.2Vin byte mode.WP# input level is Vc,+0.2V or GND+0.2V.
‘LKO
Rev. 1.01
SHARP
LHF8OV13
6.2.4
Sym.
t-EHoZ
bLoX
tGHO7
tOH
I I
tFVOV
AC CHARACTERISTICS
)
- READ-ONLY
V,,=2.i’V-3.6V,
Parameter
OPERATIONS(l)
T,=-40°C
CE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
Output Hold from Address, CE# or OE# Change, Whichever
Occurs First
BYTE# and A-, to Output Delay
BYTE# Low to Output in High Z
CE# to BYTE# High or Low
to +85X
Notes
3
3
3
3
Min.
Max.
55
0
20
1
Unit
ns
ns
ns
ns
0
I
3
3
3,4
$Jop.
tELzv
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQv-tCLQv after the falling edge of CE# without impact on tELQv.
3. Sampled, not 100% tested.
4. If BYTE# transfer during reading cycle, exist the regulations separately.
90
30
5
ns
ns
ns
Rev. 1.01
I
SHARF’
27
LHFSOV13
r
Standby
Device
Address Selection
VIH
@DRESSES(A)
Data Valid
--_--------
Address Stable
VIL
tOH+--4
VOH
DATA(D/Q)
(DQo-DQA
VOL
--__----_-_
HIGH
\
Z
_____-_-_-_
7
\
[
/
I-
HIGHZ
VIH
RP#(P)
VU
Figure 11. AC Waveform for Read Operations
Rev. 1.0
SHARP
LHF8OV13
Device
Address Selection
f
L
Data Valid
Address Stable
4
CE#(E)
117
OE#(G)
::r
. In
BYTEWI
VU
VOH
DATA(D/Q)
HIGH
Z
@Qo-DQ-r)
VOL
4
DATA(D/Q)
HIGH
HIGH
Z
Z
:DQs-DQts)
VOL
Figure 12. BYTJ3# timing Waveform
Rev. 1.0
SHARP
LHF8OV13
6.2.5
AC CHARACTERISTICS
- WRITE
29
OPERATIONS(I)
NOTES:
1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations.
Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A,, and D,, for block erase or word/byte write.
4. V, should be held at V,,,,,
( and if necessary RP# should be held at V,)
until determination of block erase or
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.01
SHARP
LHF8OV13
30
ADDRESSES(A)
CE#(Ej
OE#(G)
WE#(W)
DATACDIQ)
BYTE#(D
RY/BY#(R)
vppw
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 13. AC Waveform for WE#-Controlled
Write Operations
Rev. 1.0
SHARP
LHF8OV13
6.2.6 ALTERNATIVE
CE#-CONTROLLED
31
WRITES(l)
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A,, and D,, for block erase or word/byte write.
4. V, should be held at VPPHIR ( and if necessary RP# should be held at VHH) until determination of block erase or
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.Ol
SHARI=
32
VIH
ADDRESSES(A)
VIL
VIH
CE#(E)
VIL
VIH
OE#(G)
WE#(WI
VIH
\
VIH
DATAi.D/Q)
I
%HwH
High Z
tPHEL
VIH
I
I
VIL
,
BYTENF)
’
hEH
11
l-l-
fEHFV
w
w
I
RY/BY#fR)
hHEH
VIH
VHHI
RF’N’)
VIH
l
t
f
f+Ej . .
I
. . fy
I
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confii
or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 14. AC Waveform for CE#-Controlled Write Operations
Rev. 1.0
SHARF’
LHF8OV13
33
6.2.7 RESET OPERATIONS
RY/BY#(R)
VOL
VIH
=wP)
VIL
(A)Reset
During Read Array
Mode
High Z
RYiBY#(R)
VOL
VIH
RWP)
VIL
(B)Reset During
2.w
Block Erase or Word/Byte
Write
L
vcc
VIL
-
t2VPH
-
VIH
I
RP#(P)
a
VIL
(C)RP#
rising Timing
Figure 15. AC Waveform for Reset Operation
Reset AC Specifications
Sym.
‘PLPH
tpL&J
t2VPH
Parameter
‘RP# Pulse Low Time
(If RP# is tied to V,,, this specification is not applicable)
RP# Low to Reset during Block Erase or Word/Byte Write
V,, 2.7V to RP# High
Notes
V,,=2.7V-3.6V
Min.
Max.
100
12
3
ns
22
100
Unit
PS
ns
qoTEs:
. If RP#/ is asserted while a block erase or word/byte write operation is not executing, the reset will complete within loons.
!. A reset time, tpHQv, is required from the later of RY/BY# going High Z or RP# going high until outputs are valid.
1. When the device power-up, holding RP# low minimum lOOtis is required after V,, has been in predefined range and also
has been in stable there.
Rev. 1.0
SHARP
LHFSOV13
6.2.8
BLOCK
ERASE
AND WORD/BYTE
WRITE
PERFORMANCE(3)
Block Write Time
NOTES:
1. Typical values measured at T,=+25”C and nominal voltages. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. All values are in word mode (BYTE#=V,,). At byte mode (BYTE#=V,,), those values are double.
Rev. 1.0
SHARP
LHF80V13
7 Package and packing
specification
1. Package Out line Specification
Refer to drawing No.AAl
35
1
14 2
2. Markings
2 - 1. Marking contents
( 1) Product name : LH28F800BVHE-BTL90
( 2 > Company name : SHARP
( 3) Date code
xxx
Indicates
(Example) Y Y
WW
The marking
of “JAPAN” indicates
2 - 2. Marking layout
Refer drawing No.AAl
(This layout does not define
3.
was manufactured
Denotes the production
Denotes the production
~~~~_~~~~~~~c::.:‘:.r.
E
(4)
the product
14 2
the dimensions
ref.code
week.
(l-3)
(Lower two digits
of the year.)
the country of origin.
of marking
character
and marking
position.)
Packing Specification
(Dry packing for surface mount packages)
Dry packing is used for the purpose of maintaining
IC quality
after mounting
packages on the PCB (Printed
Circuit
Board).
When the epoxy resin which is used for plastic
packages is stored at high
humidity,
it may absorb 0.15% or more of its weight in moisture,
If the surface
mount type package for a relatively
large chip absorbs a large amount of moisture
between the epoxy resin and insert material (e.g. chip,lead
frame) this moisture
may suddenly vaporize into steam when the entire package is heated during the
soldering
process (e.g. VPS). This causes expansion and results
in separation
between the resin and insert material,
and sometimes cracking
of the package.
This dry packing is designed to prevent the above problem from occurring
in
surface mount packages.
3 - 1. Packing Materials
Material Name
Material Specificaiton
Purpose
Tray
Conductive plastic
(50devices/tray)
Fixing of device
________________-_______________________------------------------------------------------------------------------.-------------------------------____________
Conductive
plast
ic
Upper
cover
tray
(ltray/case)
Fixing
of
device
________________________________________---------------------------------------------------------------_-______-_______________________________------------Laminated aluminum bag Aluminum polyethylene
(lbag/case)
Drying of device
________________________________________---------------------------------------------------.----------------------------------------------------------------Silica
gel
Des
i
ccant
Drying
of device
__._---_____.--_________________________~~-~~~~-~~~~~---~~.------~---~.~~~~~~~~~~~~~~~-~~~~~-~~~~~~-~~~~~-~~~~-~~~~~-~~~~~~~~~~~----~~
P P band
Polypropylene
Fixing ,of tray
(3pcs/case)
________________________________________-----------------------------------------------------.-------------------------------------------------------.------Inner
case
Card
board
(500device/case)
Packaging of device
________________________________________--------------------------------------------------------------------------------------------------------------------Label
Paper
Indicates
part number, quant ity
and date of manufacture
________________________________________----------------------------------------------------------------________
__________-_____---_____________________---Outer case
Card board
Outer packing of tray
(Devices shall be placed into a tray in the same direction.).
SHARP
3-2.
36
Outline dimension
Refer to attached
Storage
4.
LHF80V13
4-l.
of tray
drawing
and Opening of Dry Packing
Store under conditions
shown below before opening
(1)
Temperature range : 5-40°C
: 80% RH or less
(2)
Humidity
the dry packing
4 - 2. Notes on opening the dry packing
(1)
Before opening the dry packing, prepare a working tabIe which is
grounded against ESD and use a grounding strap.
(2)
The tray has been treated to be conductive
or anti-static.
If the
device is transferred
to another tray, use a equivalent
tray.
4 - 3.
Storage after opening the dry packing
Perform the following
to prevent absorption
of moisture after opening.
(1)
After opening the dry packing, store the ICs in an environment with
temperature
of 5~25°C and a relative
humidity of 60% or less and
after
opening
dry packing.
mount ICs within 72 hours
4 - 4.
5.
Baking (drying)
before mounting
( 1)
Baking is necessary
(A)
If the humidity ind i cator in the desiccant
becomes pink
(B)
If the procedure in section 4-3 could not be performed
( 2)
Recommended baking condit i ons
bake it before
If the above conditions
( A) and (B) are applicable,
mounting. The recommended conditions
are 16-24 hours at 120°C.
Heat resistance
tray is used for shipping tray.
Surface
5-
c
a
Mount Conditions
Please perform the following
quality.
conditions
when mounting
ICs not to deteriorate
IC
ne time sqlder ing.)
1 .Solderinn
conditions(The
following
conditions
are valid only for
Temperature
and
Duration
71
Mounting Method
Ref low solder ing Peak temperature of 230°C or less,
surface
duration of less than 15 seconds.
(air)
200°C or over,duration
of less than 40 seconds.
Temperature increase rate of l-4YYsecond
________-_______________________________~~~~~~~-~.~--~~-~---~~~.~--~~--~.-~------.-.
_.____________.-___________________
260°C or less, duration
of less
Manual soldering
than 10 seconds.
(soldering
iron)
a - 2.
Conditions
for removal of residual
( 1)
Ultrasonic
washing power
(2)
Washing time
(3)
Solvent temperature
flux
: 25 Watts/liter
: Total I minute
: 15%40°C
or less
maximum
SHARI=
LHF80V13
37
!
1
f
JAPAN
YYWW
xxx
--
24
I
0
/SEE DETAIL A
DETAIL
A
PKG.BASE PLANE
#T;
9 - F{kk.
LEAD FINISH
*4I2
j AA1142
UNIT
ME j TSOP48-P-1220
RAWING NO.
1 TIN-LEE R%
77~f~ b~~+h’##&,
/~rlQ$&Mh!% o
( PLATING NOTE Plastic
body dimensions do not include
j
of resin.
j mm
burr
SHARP
LHF80V13
38
W
cn
io
M
it% 1
4iw
\ME;TSOP48-1220TCM-RH
s4cz j
JRAWING
NO. j CV756
UNIT j mm
NOTE
SHARI=
@upplementary
LHF80V13
39
data)
LHF80V13
Recommended mounting
Product name(Package)
Packing specification
Mounting method
Reflow soldering
conditions
Measurement
Storage
point
conditions
for two time reflow soldering
.
LH28F800BVHE-BTL90 (TSOP48-P-1220)
Tray (Dry packing)
Reflow soldering
(Air)
Peak temperature of 230°C or less.
200°C or over, duration of less than 40 seconds.
Preheat temperature of 125-15O”C, durat ion of less
than 180 seconds. Temperature increase rate of
l-4Ws
econd ,
IC package surface
After opening the dry packing, store the ICs in
an environment with a temperature of 5-25°C and
a relative
humidity of 60% or less.
If doing reflow soldering
twice,do
the first
reflow soldering
within
72 hours after opening
dry packing and do the second reflow soldering
within 72 hours after the first
reflow soldering.
conditions
If the above storage conditions
are not
applicable,
bake it before reflow soldering.
The recommended conditions
are 16-24 hours
at 120°C.
(Heat resistance
tray is used for shipping tray:)
Note
Recommended Reflow
Soldering(Air)
Temperature
Peak
230°C
Preheating
Profile
temper *ature
MAX.
,,~~~~~~~
rate
I-IC/second
Time
(NO. 980807-X14)
SHARI=
40
LHF8OV13
Data Protection
Flash memory LHF8OVXX family
Noises
having
generated
a level
exceeding
under specific
Such noises,
operating
undesired
the data stored
operating
specified
conditions
when induced onto WE# signal
commands, causing
To protect
the limit
(TSOPpackage. CSPpackage)
in the specification
may be
on some systems.
or power supply,
may be interpreted
as false
unwanted overwriting,
systems
memory updating.
in the flash memory against
with the flash memory should have the following
write
protect
designs,
as
appropriate:
1) Protecting
By setting
data in specific
a WP# to low, only
Parameter
and main blocks
System program,
etc.,
When a high voltage
For further
can be protected
against
overwriting.
cannot be locked.
is applied
to RP#, overwrite
on control1
them in the boot block.
operation
is enabled for al 1 blocks.
ing of WP# and RP#, refer
to the specification.
4.10)
2) Data protection
When the level
flashmemory
the boot block
can be locked by storing
information
(See chapter
write
block
through
Vpp
of Vpp is lower than VPPLK (lockout
is disabled.
voltage),
All blocks are lockedandthedata
write
operation
on the
intheblocksarecompletely
protected.
For the lockout
voltage,
3) Data protect
ion through
When the RP# is kept
transition,
refer
write
to the specification.
(See chapter
4.10 and 6.23.
>
RP#
low during
operation
power up and power down sequence such as vo 1 tage
on the flash
memory is disabled,
write
protecting
all
blocks.
For the detai 1s of RP# control,
4) Noise rejection
Consider
noise
refer to the specification.
(See chapter 5.6 and 6.2.7. >
of WE#
rejection
of WE# in order
to prevent
false
write
command input.
Rev 1.01