SHARP LHF08CH3

PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F008SCT-L12
Flash Memory
8M (1M ×8)
(Model No.: LHF08CH3)
Spec No.: EL104164B
Issue Date: May 7, 1999
SHARP
LHF08CH3
l Handle
this document carefully for it contains material protected by international
copyright law. Any reproduction, full or in part, of this material is prohibited without the
express written permission of the company.
l When using the products covered
herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein
application areas. When using
in Paragraph (2), even for the
precautions given in Paragraph
in Paragraph (3).
are designed and manufactured
for the following
the products covered herein for the equipment listed
following application areas, be sure to observe the
(2). Never use the products for the equipment listed
*Office electronics
*Instrumentation
and measuring equipment
*Machine tools
@Audiovisual equipment
*Home appliance
*Communication
equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands hiqh reliabilitv, should first contact a sales representative
of the
company and then accept responsibility for incorporating
into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
&ontrol
and safety devices for airplanes, trains, automobiles,
transportation equipment
l Mainframe computers
l Traffic control systems
*Gas leak detectors and automatic cutoff devices
*Rescue and security equipment
mother safety devices and safety equipment,etc.
and other
(3) Do not use the products covered herein for the following equipment which demands
extremelv hiqh performance in terms of functionality, reliability, or accuracy.
l Aerospace
equipment
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equipment for trunk lines
*Control equipment for the nuclear power industry
@Medical equipment related to life support, etc.
(4) Please direct all queries and comments
three Paragraphs to a sales representative
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regarding the interpretation
of the company.
the products covered
of the above
herein to a sales representative
of the company.
Paw
i
1
SHARI=
1
LHF08CH3
CONTENTS
PAGE
PAGE
...................................................
3
....................................................
3
3
5.1 Three-Line Output Control ................................
.23
5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit
23
Configuration Polling.. .........................................
7
7
5.3 Power Supply Decoupling.. ................................
23
5.4 V,, Trace on Printed Circuit Boards.. ............... .23
3.0 BUS OPERATION .................................................
3.1 Read ...................................................................
a
a
5.5 v,,, v,,, RP# Transitions.. ..............................
5.6 Power-Up/Down Protection.. .............................
5.7 Power Dissipation ..............................................
.24
.24
3.2 Output Disable ....................................................
6
3.3 Standby ...............................................................
3.4 Deep Power-Down ..............................................
3.5 Read Identifier Codes Operation.. .......................
3.6 Write ....................................................................
a
8
9
6.0 ELECTRICAL SPECIFICATIONS.. .....................
6.1 Absolute Maximum Ratings ...............................
6.2 Operating Conditions .........................................
.25
25
25
9
6.2.1 Capacitance .................................................
25
4.0 COMMAND DEFINITIONS ....................................
9
6.2.2 AC Input/Output Test Conditions.. ............... .26
27
6.2.3 DC Characteristics ........................................
4.1 Read Array Command.. .....................................
12
6.2.4 AC Characteristics - Read-Only Operations .29
4.2 Read Identifier Codes Command ......................
12
4.3 Read Status Register Command.. .....................
4.4 Clear Status Register Command.. .....................
12
6.2.5 AC Characteristics - Write Operations.. ....... .32
6.2.6 Alternative CE#-Controlled Writes.. ............. .35
6.2.7 Reset Operations .........................................
36
1.0 INTRODUCTION
1.1 New Features..
1.2 Product Overview
2.0 PRINCIPLES
................................................
OF OPERATION..
...........................
2.1 Data Protection ...................................................
4.5 Block Erase Command.. ....................................
4.6 Byte Write Command ........................................
4.7 Block Erase Suspend Command.. .....................
4.6 Byte Write Suspend Command.. .......................
12
12
13
5.0 DESIGN CONSIDERATIONS
.............................
6.2.6 Block Erase, Byte Write and Lock-Bit
Configuration Performance ...........................
.23
24
39
13
14
4.9 Set Block and Master Lock-Bit Commands.. ..... 14
4.10 Clear Block Lock-Bits Command.. ................... 15
7.0 ADDITIONAL
INFORMATION
............................
.40
7.1 Ordering Information .........................................
.40
8.0 PACKAGE AND PACKING SPECIFICATIONS
..4 1
Rev. 1.0
SHAi?P
2
LHF08CH3
LH28FOOSSCT-L12
8M-BIT (1 MB x 8)
SmartVoltage
Flash MEMORY
n SmartVoltage
Technology
- 2.7V(Read-Only),
3.3V or 5V Vcc
- 3.3V, 5V or 12V Vpp
n
Automated
Byte Write and Block Erase
- Command User Interface
- Status Register
n High-Performance
- 120ns(5V*0.5V),
170ns(2.7V-3.6V)
n
Enhanced Automated Suspend Options
- Byte Write Suspend to Read
- Block Erase Suspend to Byte Write
- Block Erase Suspend to Read
n
Extended Cycling Capability
- 100,000 Block Erase Cycles
- 1.6 Million Block Erase Cycles/Chip
Read Access Time
150ns(3.3V*O.3V),
n Operating Temperature
- 0°C to +7O”C
I
I
I
High-Density
Symmetrically-Blocked
Architecture
- Sixteen 64K-byte Erasable Blocks
Low Power Management
- Deep Power-Down
Mode
- Automatic Power Savings Mode
Decreases Ice in Static Mode
Enhanced Data Protection Features
- Absolute Protection with Vpp=GND
- Flexible Block Locking
- Block Erase/Byte Write Lockout
during Power Transitions
n SRAM-Compatible
Write Interface
n
Industry-Standard
- 40-Lead TSOP
Packaging
n
ETOXTM* Nonvolatile
Flash Techno WY
W CMOS Process
(P-type silicon substrate)
n
Not designed
hardened
or rated as radiation
SHARP’s LH28F008SCT-L12
Flash memory with SmartVoltage
technology is a high-density, low-cost, nonvolatile,
?ead/write storage solution for a wide range of applications. Its symmetrically-blocked
architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking,
where code is either directly executed out of flash or
downloaded to DRAM, the LH28F008SCT-L12
offers three levels of protection: absolute protection with V,, at
ZND, selective hardware block locking, or flexible software
block locking. These alternatives
give designers
Jltimate control of their code security needs.
The LH28F008SCT-L12
is manufactured
on SHARP’s
0.38um ETOXTM process
technology.
It come in
ndustry-standard
package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA
architecture, the LH28F008SCT-L12
enables quick and easy upgrades for designs demanding the state-of-the-art.
‘ETOX is a trademark
of Intel Corporation.
Rev. 1.3
3
LHF08CH3
SmartVoltage
technology provides a choice of Voc
and V,, combinations,
as shown in Table 1, to mee
system performance
and power expectations.
2.7\
V,, consumes
approximately
one-fifth the power o
5V Vo,. But, 5V Vco provides the highest reac
performance.
V,, at 3.3V and 5V eliminates the neec
for a separate
12V converter,
while V,,=12\
maximizes block erase and byte write performance
In addition to flexible erase and program voltages
the dedicated V,, pin gives complete data protectior
when V,+V,,,,.
1 INTRODUCTION
This
contains
LH28F008SCT-L12
datasheet
specifications.
Section 1 provides a flash memory
overview.
Sections
2, 3, 4, and 5 describe
the
memory organization
and functionality.
Section 6
covers electrical specifications.
LH28F008SCT-L12
Flash
also
includes
memory
documentation
application
notes
and design
tools which
are
referenced in Section 7.
1.1
New Features
The LH28F008SCT-L12
SmartVoltage Flash memory
maintains
backwards-compatibility
with SHARP’s
28F008SA.
Key enhancements
over the 28F008SA
include:
I
*SmartVoltage
Technology
*Enhanced
Suspend
Capabilities
&r-System
Block Locking
Both devices
share a compatible
pinout, status
register,
and
software
command
set.
These
similarities
enable a clean upgrade
from the
28F008SA to LH28F008SCT-L12.
When upgrading, it
is important to note the following differences:
*Because of new feature support, the two devices
have different device codes. This allows
for
software optimization.
l VPPLK
has been lowered from 6.5V to l.5V to
support 3.3V and 5V block erase, byte write, and
lock-bit configuration operations. The V,, voltage
transitions
to GND is recommended
for designs
that switch V,, off during read operation.
*To take advantage of SmartVoltage
allow V,, connection to 3.3V or 5V.
1.2 Product
technology,
Overview
The LH28F008SCT-L12
is a high-performance
8M-bit
SmartVoltage Flash memory organized as 1 M-byte of
3 bits. The IM-byte of data is arranged in sixteen
SK-byte
blocks
which are individually erasable,
ockable, and unlockable
in-system.
The memory
nap is shown in Figure 3.
Table 1. Vc, and V,, Voltage Combinations
Offered by SmartVoltage
Technology
Vpp Voltage
Vr.r: Voltage
2.7V(‘)
-..
3.3v, 54, l2V
3.3v
5V
5v. 12v
NOTE:
1. Block erase, byte write and lock-bit configuratior
operations with V,o<3.OV are not supported.
Internal
and
VCC
automatically
configures
read and write operations.
detection
Circuitb
the device for optimizec
VP,
A Command
User Interface (CUI) serves as the
interface between the system processor and interna
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary
for
block erase, byte write, and lock-bit configuration
operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.3s (5V V,,, 12V
VP,) independent of other blocks. Each block can be
independently
erased
100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in byte increments
typically within 6u.s (5V Vcc, 12V Vpp). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.
Rev. 1.3
4
LHF08CH3
Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase
and byte write operations,
while the master lock-bit
Lock-bit
Jates
block
lock-bit
modification.
zonfiguration
operations
(Set Block Lock-Bit, Set
and
Clear
Block
Lock-Bits
Master
Lock-Bit,
zommands) set and cleared lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
iinished.
The RY/BY# output gives an additional indicator of
JVSM activity by providing both a hardware signal of
status (versus software polling) and status masking
iinterrupt masking for background
block erase, for
mample).
Status polling using RY/BY# minimizes
30th CPU overhead and system power consumption.
JVhen low, RY/BY#
indicates that the WSM is
3erforming
a block erase, byte write, or lock-bit
zonfiguration. RY/BY#-high indicates that the WSM is
,eady for a new command, block erase is suspended
:and byte write is inactive), byte write is suspended,
3r the device is in deep power-down
mode.
The access
time is 120 ns (tAvav) over the
commercial
temperature
range (0% to +70”(Z) ant
Vc, supply voltage range of 4.5V-5.5V. At lower Vcc
voltages, the access times are 150 ns (3.OV-3.6V:
and 170 ns (2.7V-3.6V).
The Automatic
Power
Savings
(APS)
feature
substantially
reduces active current when the device
is in static mode (addresses
not switching).
In APS
mode, the typical I,,, current is 1 mA at 5V V,,.
When CE# and RP# pins are at V,,, the I,, CMOS
standby mode is enabled. When the RP# pin is a
GND, deep power-down
mode is enabled which
minimizes
power consumption
and provides write
protection
during reset. A reset time (tpHQv) is
required from RP# switching high until outputs arc
valid. Likewise, the device has a wake time (t,,,,:
from RP#-high until writes to the CUI are recognized
With RP# at GND, the WSM is reset and the status
register is cleared.
The device is available in 40-lead TSOP (Thin Smal
Outline Package, 1.2 mm thick). Pinout is shown ir
Figure 2.
Rev.1.0
SHARP
5
LHF08CH3
Figure
1. Block
Diagram
NC
NC
WE#
OE#
RY/BY#
49
Ale
A17
A16
AIS
A14
An
A12
CE#
vcc
VPP
RP#
41
40-LEAD TSOP
STANDARD PINOUT
1Omm x 20mm
TOP VIEW
DQ7
DQ6
DQ5
DQ4
VCC
GND
GND
DQ3
DQ2
Alo
As
43
DQI
DQo
A7
A6
z
A2
A3
A5
A4
Figure
2. TSOP 40-Lead
Pinout
Rev. 1.0
SHARP
6
LHF08CH3
r
I
r Symbol
A,-Al
Type
9
INPUT
DQo-DQ7
INPUT/
OUTPUT
CE#
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
RY/BY#
OUTPUT
SUPPLY
Vcc
SUPPLY
GND
NC
SUPPLY
T
Table 2. Pin Descriptions
Name and Function
ADDRESS
INPUTS: Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS:
Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins float
to high-impedance
when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP
POWER-DOWN:
Puts the device in deep power-down
mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down
sets the device to read array mode. RP# at V,, enables setting of the
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP#=V,,
overrides block lock-bits thereby enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with VIHcRP#<VHH produce spurious results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY#:
Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down
mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION
POWER SUPPLY: For
erasing array blocks, writing bytes, or configuring lock-bits. With V,,<V,,Lk,
memory
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid V,, (see DC Characteristics)
produce spurious results and should not be
attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V
operation. To switch from one voltage to another, ramp V,, down to GND and then ramp
Vco to the new voltage. Do not float any power pins. With Vcc<VLKO, all write attempts
to the flash memory are inhibited. Device operations at invalid Vco voltage (see DC
Characteristics)
produce spurious results and should not be attempted. Block erase, byte
write and lock-bit configuration operations with Vrr<3.0V
are not supported.
GROUND: Do not float any ground pins.
NO CONNECT:
Lead is not internal connected; it may be driven or floated.
Rev. 1.0
SHARP
7
LHF08CH3
2 PRINCIPLES
OF OPERATION
FFFFF
The LH28F008SCT-L12
SmartVoltage Flash memory
includes an on-chip WSM to manage block erase,
byte write, and lock-bit configuration
functions.
It
allows for: 100% TTL-level control inputs, fixed power
supplies during block erasure, byte write, and lock-bit
configuration, and minimal processor overhead with
RAM-Like interface timings.
After initial device power-up
or return from deep
power-down
mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V,, voltage. High
block erasure,
voltage on V,, enables successful
byte writing, and lock-bit configuration. All functions
associated
with altering memory
contents-block
erase, byte write, Lock-bit configuration, status, and
identifier codes-are
accessed
via the CUI and
verified through the status register.
standard
written
using
Commands
are
microprocessor
write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
byte write, and lock-bit configuration.
The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification, and margining of data.
Addresses
and data are internally latch during write
cycles. Writing the appropriate
command outputs
array data, accesses the identifier codes, or outputs
status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and
executed from system RAM during flash memory
updates.
After successful
completion,
reads are
again possible via the Read Array command. Block
erase suspend allows system software to suspend a
block erase to read or write data from any other
block. Byte write suspend allows system software to
suspend a byte write to read data from any other
flash memory array location.
FOOOO
EFFFF
EOOW
DFFFF
DO000
CFFFF
coooo
BFFFF
BOO00
AFFFF
AOOW
SFFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
SFFFF
50000
4FFFF
40000
JFFFF
30000
PFFFF
20000
1 FFFF
10000
OFFFF
FigUre
3.
Memory
Map
2: 1 Data Protection
Depending on the application, the system designer
may choose
to make
the V,,
power
supply
switchable
(available
only when
memory
block
erases, byte writes, or lock-bit configurations
are
required)
or hardwired
to V,,,,,z13.
The device
and
either
design
practice
accommodates
encourages
optimization
of the processor-memory
interface.
memory
contents
cannot
be
When Vpp~VppLK,
altered. The CUI, with two-step
block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V,,.
All write
functions are disabled when Vcc is below the write
lockout voltage VLKO or when RP# is at V,,. The
device’s block locking capability provides additional
protection from inadvertent code or data alteration by
gating erase and byte write operations.
Rev.1.3
SHARP
LHF08CH3
8
3 BUS OPERATION
consuming
completes.
The local CPU reads and writes
flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor
bus cycles.
3.4
active
power
until
operatior
Deep Power-Down
RP# at V,, initiates the deep power-down
3.1
the
mode.
Read
Information can be read from any block, identifier
codes, or status register independent
of the V,,
voltage. RP# can be at either V,, or V,,.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from deep power-down
mode,
the device automatically resets to read array mode.
Four control pins dictate the data flow in and out of
the component: CE#, OE#, WE#, and RP#. CE# and
OE# must be driven active to obtain data at the
outputs. CE# is the device selection control, and
when active enables the selected memory device.
OE# is the data output (DQ,-DQ,)
control and when
active drives the selected memory data onto the I/O
bus. WE# must be at V,, and RP# must be at V,, or
V,,. Figure 15 illustrates a read cycle.
3.2 Output
Disable
JVith OE# at a logic-high level (V,,), the device
outputs are disabled. Output pins DC+,-DQ,
are
olaced in a high-impedance
state.
3.3 Standby
ZE# at a logic-high level (VI,) places the device in
standby mode #which substantially
reduces device
lower consumption.
DQc-DQ, outputs are placed in
I high-impedance
state independent
of OE#. If
deselected during block erase, byte write, or lock-bit
:onfiguration, the device continues functioning, and
In read modes, RP#-low
deselects
the memory
places output drivers in a high-impedance
state ant
turns off all internal circuits. RP# must be held low fo
a minimum of 100 ns. Time tPHQv is required afte
return from power-down
until initial memory acces:
outputs are valid. After this wake-up interval, norma
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During
block
erase,
,“;~low~ritell
o;bo~ck;+;
configuration
modes,
operation.
RY/BY#
remains
low until the rese
operation
is complete.
Memory
contents
beins
altered are no longer valid; the data may be partially
erased or written. Time tPHwL is requirod after RPB
goes to logic-high (V,,) before another command car
be written.
As with any automated
device, it is important tc
assert RP# during system reset. When the systencomes out of reset, it expects to read from the flask
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU resei
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array
data. SHARP’s
flash memories allow proper CPU
initialization following a system reset through the use
of the RP# input. In this application, RP# is controlled
by the same RESET# signal that resets the system
CPU.
Rev. 1.0
LHF08CH3
3.5
Read Identifier
3.6
Codes Operation
The read identifier codes operation
outputs the
device
code,
block
lock
manufacturer
code,
configuration codes for each block, and the master
lock configuration
code (see Figure 4). Using the
manufacturer and device codes, the system CPU can
automatically
match the device with its proper
algorithms.
The block
lock and master
lock
configuration
codes identify locked and unlocked
blocks and master lock-bit setting.
FFFFF
Reserved for
Future Implementation
FOO04
Block 15 Lock Configuration
Write
Writing commands
to the CUI enable reading 01
device data and identifier codes. They also control
inspection and clearing of the status register. When
the CUI additionally controls block
VPP=VPPHli2/3~
erasure, byte write, and lock-bit configuration.
The Block Erase command
requires
appropriate
command data and an address within the block to 5s
erased.
The Byte Write command
requires
the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require ths
command
and address within the device (Master
Lock) or block within the device (Block Lock) to be
locked. The Clear Block Lock-Bits command requires
the command and address within the device.
The CUI does not occupy an addressable
memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a commanc
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled
write operations.
FOO03
FOO02
9
Code
4 COMMAND
DEFINITIONS
When the V,, voltage 5 V,,,,,
Read operations
from the status register, identifier codes, or blocks
are enabled.
Placing V,,,,,,,
on V,,
enables
successful
block erase,
byte write and lock-bii
configuration operations.
Block 1 Lock Configuration
100021
Code
Device operations
are selected by writing specific
commands
into the CUI. Table 4 defines these
commands.
10001
10000
OFFFF
Master Lock Configuration
t
Lock Configuration
00001~
Device Code
00002
Block 0
----------------L------------------------------------
Manufacturer
Figure
4. Device
Identifier
Code
Code
Code
Block (I
Code Memory
Map
L
RPV
I
n
SHARI=
10
LHF08CH3
Mode
Read
Notes
RP#
1,2,3,8
VT Or
HH
Output Disable
3
“I,
Standby
3
“I,
Deep Power-Down
4
Read Identifier Codes
8
“I,
3,6,7,8
“.
Write
Or
Vr#
Or
VHH
V,,
Or
VHH
Or
HH
Table 3. Bus Operations
CE#
OE#
WE#
Address
VPP
D&.-r
DOUT
RY/BY#
X
“IL
“IL
“I,
X
X
“IL
“I,
‘1,
X
X
High Z
X
“I,
X
X
X
X
X
High Z
X
X
X
X
High Z
Vn,,
Note 5
“OH
X
“IL
“IL
vlH
X
See
Figure 4
“IL
“I,
“IL
X
’
X
DlN
‘4OTES:
I. Refer to DC Characteristics.
When Vpp<VppLK, memory contents can be read, but not altered.
!. X can be VI, or VrH for control pins and addresses,
and V,,,,
or VPpHf/2/s for VP,. See DC Characteristics
vPPLK
and
“PPHl12i3
for
voltaw
3. RY/BY# is V,, when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms.
It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write
suspend mode, or deep power-down
mode.
C. RP# at GNDk0.2”
ensures the lowest deep power-down
current.
i. See Section 4.2 for read identifier code data.
i. Command writes involving block erase, write, or lock-bit configuration are reliably executed when Vpp=VppH1/2/3
Block erase, byte write, or lock-bit configuration with V,c<3.OV or VrH<RP#<VHH produce
and vCC=vCC2/3.
spurious results and should not be attempted.
‘. Refer to Table 4 for valid DIN during a write operation.
1. Don’t use the timing both OE# and WE# are VI,.
Rev. 1 .O
LHF08CH3
Read
11Read
Read
Clear
Block
Command
Array/Reset
Identifier Codes
Status Register
Status Register
Erase
IIByte Write
id Byte Write
Table 4. Command Definit ions(g)
First B us Cycle
Bus Cycles
Rea’d.
Notes
Ooer(l)
,1 AdJdr(2)
1 Data(“)
1
1 Write
1
X
1 FFH
1
22
I 4
I Write
I
X
I 90H
2
Write
X
70H
1
Write
X
50H
5
Write
BA
20H
2
40H
2
Write
WA
5,6
l&
1
5
Write
X
Second Bus Cycle
1 Addr12) 1 Datat3)
Oper(‘)
I
Read
Read
I
IA
X
I
ID
SRD
Write
BA
DOH
Write
WA
WD
/I
BOH
I
id Byte Write
1
5
Write
X
DOH
Resume
1
7
60H
Write
BA
OlH
2
Write
BA
Set Block Lock-Bit
2
7
Write
X
60H
Write
X
FlH
Set Master Lock-Bit
Write
X
DOH
2
8
Write
X
60H
Clear Block Lock-Bits
NOTES:
1. BUS operations are defined in Table 3.
2. X=Any valid address within the device.
IA=ldentifier Code Address: see Figure 4.
BA=Address
within the block being erased or locked.
WA=Address
of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and
master lock codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at V,, to enable block erase or byte write operations. Attempts to issue a
block erase or byte write to a locked block while RP# is V,,.
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. If the master lock-bit is set, RP# must be at V,, to set a block lock-bit. RP# must be at V,, to set the master
lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is V,,.
8. If the master lock-bit is set, RP# must be at V,, to clear block lock-bits. The clear block lock-bits operation
simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can
be done while RP# is VI,.
9. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
Rev. 1.0
LHFOSCH3
12
4.1 Read Array Command
4.3
Upon initial device power-up and after exit from deep
Dower-down
mode, the device defaults to read array
node. This operation is also initiated by writing the
Read Array command. The device remains enabled
‘or reads until another command is written. Once the
nternal WSM has started a block erase, byte write or
ock-bit configuration,
the device will not recognize
:he Read Array command until the WSM completes
ts operation unless the WSM is suspended via an
Erase Suspend or Byte Write Suspend command.
The Read Array command functions independently of
:he V,, voltage and RP# can be VI, or V,,.
The status register may be read to determine when E
block erase, byte write, or lock-bit configuration
i:
complete
and whether
the operation
completec
successfully.
It may be read at any time by writing the
Read Status Register command. After writing this
command,
all subsequent
read operations
outpu
data from the status register until another valic
command is written. The status register contents are
latched on the falling edge of OE# or CE#, whichever
occurs. OE# or CE# must toggle to VI, before further
reads to update the status register latch. The Reac
Status Register command functions independently o’
the V,, voltage. RP# can be V,, or V,,.
4.2 Read Identifier
Read Status Register
Command
Codes Command
4.4
The identifier code operation is initiated by writing the
qead Identifier Codes
command.
Following
the
:ommand write, read cycles from addresses shown in
=igure 4 retrieve the manufacturer, device, block lock
:onfiguration
and master lock configuration
codes
see Table 5 for identifier code values). To terminate
:he operation, write another valid command. Like the
?ead Array command, the Read Identifier Codes
:ommand functions independently of the V,, voltage
lnd RP# can be V,, or V,,. Following the Read
dentifier Codes command, the following information
:an be read:
Table 5. Identifier
Codes
Command
Status register bits SR.5, SR.4, SR.3, and SR.l are
set to “1”s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 7). By allowing
system
software
to reset
these
bits, severa
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence:
may be performed. The status register may be pollee
to determine if an error occurre during the sequence.
To clear the status register, the Clear
command (50H) is written. It functions
of the applied V,, Voltage. RP# can
This command is not functional during
byte write suspend modes.
4.5
*Block is Unlocked
@Block is Locked
*Reserved for Future Use
Master Lock Configuration
*Device is Unlocked
ODevice is Locked
*Reserved for Future Use
4OTE:
. X selects the specific block lock configuration
code to be read. See Figure 4 for the device
identifier code memory map.
Clear Status Register
Status Register
independently
be VI, or V,,.
block erase or
Block Erase Command
Erase is executed one block at a time and initiated by
a two-cycle
command. A block erase setup is first
written,
followed by an block erase confirm. This
command sequence requires appropriate sequencing
and an address within the block to be erased (erase
changes
all
block
data
to
FFH).
Block
preconditioning,
erase,
and verify
are handled
internally by the WSM (invisible to the system). After
the two-cycle
block erase sequence is written, the
device automatically
outputs status register data
when read (see Figure 5). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
Rev. 1.0
LHF08CH3
13
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
block lock-bit be cleared or, if set, that RP#=VHH. I
byte write is attempted when the corresponding
bloc1
lock-bit is set and RP#=VrH, SR.l and SR.4 will bc
set to “1 ‘I. Byte write operations with VrH<RP#<Vr+
produce
spurious
results
and should
not bt
attempted.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to “1 ‘I. Also, reliable block erasure
can only occur when Vcc=Vcc2,s
and Vpp=VppH1,2,3.
In the absence of this high voltage, block contents
are protected against erasure.
If block erase is
attempted while V,,IV,,,k,
SR.3 and SR.5 will be
set to “1 ‘I. Successful
block erase requires that the
corresponding block lock-bit be cleared or, if set, that
RP#=V,,.
If block erase is attempted when the
corresponding
block lock-bit is set and RP#=V,,,
SR.l and SR.5 will be set to “1”. Block erase
operations
with V,,<RP#CV,~
produce
spurious
,esults and should not be attempted.
4.7
4.6 Byte Write Command
3yte write is executed by a two-cycle
command
sequence.
Byte write setup
(standard
40H or
alternate 10H) is written, followed by a second write
:hat specifies the address and data (latched on the
ising edge of WE#). The WSM then takes over,
:ontrolling the byte write and write verify algorithms
nternally. After the byte write sequence is written, the
device automatically
outputs status
register data
Nhen read (see Figure 6). The CPU can detect the
:ompletion of the byte write event by analyzing the
qY/BY# pin or status register bit SR.7.
Nhen byte write is complete, status register bit SR.4
;hould be checked. If byte write error is detected, the
;tatus register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
;uccessfully write to “0%. The CUI remains in read
;tatus register
mode until it receives
another
:ommand.
qeliable byte writes can only occur when Vcc=Vcc2/s
In the absence of this high
Ind
VPP=VPPH1/2/3loltage, memory contents are protected against byte
vrites. If byte write is attempted while Vpp~Vpp,,,
status register bits SR.3 and SR.4 will be set to “1”.
juccessful byte write requires that the corresponding
Block Erase Suspend
Command
The
Block
Erase
Suspend
command
allow:
block-erase
interruption to read or byte-write data ir
another block of memory.
Once the block-erase
process
starts, writing the Block Erase Suspenc
command requests that the WSM suspend the bloc+
erase sequence
at a predetermined
point in the
algorithm. The device outputs status register dat:
when read after the Block Erase Suspend commanc
is written. Polling status register bits SR.7 and SR.E
can determine when the block erase operation ha:
been suspended (both will be set to “1”). RY/BY# wil
also transition to VOH. Specification twHr$+ defines
the block erase suspend latency.
At this point, a Read Array command can be writter
to read data from blocks other than that which is
suspended.
A Byte Write command sequence caralso be issued during erase suspend to program data
in other blocks.
Using the Byte Write Suspenc
command (see Section 4.8), a byte write operation
can also be suspended. During a byte write operation
with block erase suspended,
status register bit SR.7
will return to “0” and the RY/BY# output will transition
to V,,. However,
SR.6 will remain “1” to indicate
block erase suspend status.
The only other valid commands while block erase is
suspended
are Read Status Register
and Block
Erase
Resume.
After a Block Erase
Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically
clear and
RY/BY# will return to V,,. After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 7). VP,
must remain at VppHr,2/3 (the same Vpp level used
for block erase) while block erase is suspended. RP#
must also remain at VrH or VHH (the same RP# level
used for block erase). Block erase cannot resume
until byte write operations initiated during block erase
suspend have completed.
Rev. 1.0
SHARP
LHF08CH3
4.8
Byte Write Suspend
Command
The Byte Write Suspend command allows byte write
interruption
to read data in other flash memory
locations. Once the byte write process starts, writing
the Byte Write Suspend command requests that the
WSM
suspend
the byte write sequence
at a
predetermined
point in the algorithm. The device
continues to output status register data when read
after the Byte Write Suspend command is written.
Polling status register
bits 33.7 and SR.2 can
determine when the byte write operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to V,,. Specification t,,,,,
defines the
byte write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended.
The only other valid commands
while
Dyte write is suspended
are Read Status Register
and Byte Write Resume. After Byte Write Resume
:ommand is written to the flash memory, the WSM
NilI continue the byte write process. Status register
3ts SR.2 and SR.7 will automatically
clear and
:;;ize
wi;o;;;;dto
V,,.
4fter thethydrv;;z
IS
wntten,
automatically outputs status register data when read
:see Figure 8). V,, must remain at V,,,,,,,,
(the
same V,, level used for byte write) while in byte write
suspend mode. RP# must also remain at V,, or V,,
:the same RP# level used for byte write).
1.9 Set Block and Master Lock-Bit
Commands
4 flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
naster lock-bit. The block lock-bits gate program and
erase operations
while the master lock-bit gates
Ilock-lock
bit modification. With the master lock-bit
lot set, individual block lock-bits can be set using the
jet Block Lock-Bit
command.
The Set Master
.ock-Bit command,
in conjunction with RP#=V,,,
bets the master lock-bit. After the master lock-bit is
;et, subsequent
setting of block lock-bits requires
joth the Set Block Lock-Bit command and V,, on
the RP# pin. See Table 6 for a summary
and software write protection options.
14
of hardwan
Set block lock-bit and master lock-bit are executed b!
a two-cycle
command sequence. The set block o
master lock-bit setup along with appropriate block o
device address is written followed by either the se
block lock-bit confirm (and an address within tht
block to be locked) or the set master lock-bit confirn
(and any device address). The WSM then control:
the set lock-bit algorithm. After the sequence
i:
written,
the device automatically
outputs
statu:
register data when read (see Figure 9). The CPU car
detect the completion of the set lock-bit event b\
analyzing the RY/BY# pin output or status register bi
SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error iz
detected, the status register should be cleared. The
CUI will remain in read status register mode until i
new command is issued.
This two-step
sequence
of set-up
followed
bb
execution ensures that lock-bits are not accidentall]
set. An invalid Set Block or Master
Lock-Bil
command will result in status register bits SR.4 ant
SR.5 being set to “1 ‘I. Also, reliable operations OCCUI
only when Vcc=Vcc2,3
and VPP=VPPH,,2/3. In the
absence of this high voltage, lock-bit contents are
protected against alteration.
A successful
set block lock-bit operation requires thai
the master lock-bit be cleared or, if the master
lock-bit is set, that RP#=V,,.
If it is attempted with
the master lock-bit set and RP#=V,,, SR.l and SR.4
will be set to “1” and the operation will fail. Set block
lock-bit
operations
while VIHcRP#cV,,
produce
spurious
results and should not be attempted.
A
successful
set master lock-bit operation requires that
RP#=V,,.
If it is attempted with RP#=V,,, SR.l and
SR.4 will be set to “1” and the operation will fail. Set
master
lock-bit
operations
with
V,,cRP#<V,,
produce
spurious
results
and should
not be
attempted.
Rev. 1.0
LHF08CH3
4.10
Clear Block Lock-Bits
Command
i All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits
command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits
command.
If the
master lock-bit is set, clearing block lock-bits requires
both the Clear Block Lock-Bits command and V,, on
the RP# pin. See Table 6 for a summary of hardware
and software write protection options.
Clear block lock-bits
operation is executed by a
two-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically
outputs
status register data
when read (see Figure 10). The CPU can detect
completion
of the clear block lock-bits
event by
analyzing the RY/BY# Pin output or status register bit
SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.
Operation
Block Erase or
Byte Write
Set Block
Lock-Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
-
Master
Lock-Bit
X
15
This two-step
sequence
of set-up
followed
by
execution
ensures
that block lock-bits
are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to “1 I’. Also, a reliable clear
block lock-bits
operation
can only occur when
Vcc=Vcc2,s
and VPP=VPPH1,2,3. If a clear block
lock-bits
operation is attempted while V,,rV,,,,,
SR.3 and SR.5 will be set to “1”. In the absence of
this high voltage, the block lock-bits content are
protected against alteration. A successful
clear block
lock-bits operation requires that the master lock-bit is
not set or, if the master lock-bit is set, that RP#=V,,.
If it is attempted with the master lock-bit set and
RP#=V,,,
SR.l and SR.5 will be set to “1” and the
operation will fail. A clear block lock-bits operation
with V,,cRP#cV,,
p reduce spurious
results and
should not be attempted.
If a clear block lock-bits operation is aborted due to
V,, or Vcc transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined
state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents
to
known values. Once the master lock-bit is set, it
cannot be cleared.
Table 6. Write Protection
Alternatives
Block
Lock-Bit
RP#
Effect
0
V,, or VHH
Block Erase and Byte Write Enabled
1
V,,
Block is Locked. Block Erase and Byte Write Disabled
Block Lock-Bit Override. Block Erase and Bvte Write
\I
‘HH
Enabled
X
VIH or VHH
Set Block Lock-Bit Enabled
X
V,,
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
VHH
Master Lock-Bit Override. Set Block Lock-Bit Enabled
X
V,,
Set Master Lock-Bit Disabled
Vr+
Set Master Lock-Bit Enabled
X
V,, , or V,,
Clear Block Lock-Bits Enabled
X
V,H
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled
.,--1--l
--I~m.rh
-...-I- hl-“,--,L# --I _.I
rvrasrer LOCK-~
uvernae. Lrear DIOCK LOCK-ms
‘HH
Enabled
/
Rev. 1.0
1
.16
LHFOSCH3
Table 7. Status Register
WSMS
1
7
ESS
1
ECLBS
6
( BWSLBS
4
5
1
Definition
VPPS
3
1
BWSS
2
1
DPS
R
1
0
NOTES:
SR.7 = WRITE STATE MACHINE
1 = Ready
0 = Busy
STATUS
Check RY/BY# or SR.7 to determine block erase, byte
write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7=“0”.
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are “1 “s after a block erase or
lock-bit configuration attempt, an improper command
sequence was entered.
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.3 does not provide a continuous indication of V,,
level. The WSM interrogates and indicates the V,, level
only after Block Erase, Byte Write, Set Block/Master
Lock-Bit, or Clear Block Lock-Bits command sequences.
SR.3 is not guaranteed to reports accurate feedback
only when V,,#V,,,,,,,,.
SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS
1 = Error in Byte Write or Set Master/Block
Lock-Bit
0 = Successful Byte Write or Set Master/Block
Lock-Bit
SR.3 = V,,
1 = V,,
0 = V,,
STATUS
Low Detect, Operation
OK
Abort
SR.2 = BYTE WRITE SUSPEND STATUS
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit
Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED
FOR FUTURE
and/or RP# Lock
ENHANCEMENTS
SR.l does not provide a continuous indication of master
and block lock-bit values. The WSM interrogates the
master lock-bit, block lock-bit, and RP# only after Block
Erase, Byte Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set, master
lock-bit is set, and/or RP# is not V,,. Reading the block
lock and master lock configuration codes after writing
the Read Identifier Codes command indicates master
and block lock-bit status.
SR.0 is reserved for future use and should be masked
out when polling the status register.
SHARI=
LHFOSCH3
Bus
Operation
Commenk
Command
I
write
Erase Setup
Ems.3
COtlfilll7
write
Read Status
I
Data=MH
Addr=Wlthm
Block lo be Erased
DateDOH
Addr=Within
Block to be Erased
Status Register
Read
*
I
I
I
I
I
Data
I
1.,,
Check SR.7
ISWSM Ready
o=WSM Busy
Repeat for subsequent
block erasures.
Full status check can be done after each block erase or alter a sequence
block erasures.
Write FFH after the last operation
to place device I” read array mode.
of
FULLSTATUSCHECKPROCEDURE
Comments
Command
I
I
Standby
Check
l=Vpp
Standby
Check SR. 1
t&evice
Protect Detect
RP#=V,,,Blwk
Lock-Bit IS Set
Only required for systems
implemenbng
lock-bit configuration
Standby
Check SR.4.5
Both t=Command
I
SR.3
Error Detect
Sequence
Error
I
Standby
I
I
Check SR.5
l=Block Erase Error
SR.S.SR.4.SR.3
and SR.l are only cleared by the Clear Status
Register Command
in cases where multiple blocks are erased
before full status is checked.
If error is detected. clear the Status Register before attempbng
reby or other error recovery.
Figure
5.
AuIomaTea
UIOCK
trase
rlowcnan
Rev.
1.0
SHARI=
LHFOSCH3
Comments
Command
Setup
write
write
Byte Wnte
Byte Wnte
Data40H
Addr=Location
to Be Written
Data=Data to Be Written
Ackfr=Locabon
to Be Written
Data and Address
Status Register
Read
Suspend
Byte
Check
Standby
Data
SR.7
l=WSM Ready
O=WSM Busy
Repeat for subsequent
byte writes.
SR full stat”s check can be done after each byte write, or after a sequence
byte writes.
Write FFH after the last byte write operahon to place device I”
read array mode.
FULL STATUS
CHECK
of
PROCEDURE
Read Status Aeglster
Data(See Above)
BUS
Operation
Deuce
Comments
Command
Standby
Check
l=Vpp
SR.3
Error Detect
Standby
Check SR. 1
l=Devlce
Protect Detect
RP#=V,,+Block
Lock-Bit 1s Set
Only requtred for systems
implemenbng
lock-bit configuration
Standby
Check SR.4
t=Data Wnte Error
Protect Error
SR.4SR.3
command
and SIX, are only cleared by the Clear Status Register
in cases where multiple locations are written before
full status is checked.
If error is detected, clear the Status Regtster
before attempting
retry or other error recovery.
Byte Write Successful
Figure 6. Automated
Byte Write
Flowchart
Rev. 1.0
SHARP
LHF08CH3
Bus
Operation
Comments
Command
Data=BOH
Addr=X
Status Regtster
Addr=X
Check SR.7
l=WSM Ready
O=WSM Busy
Standby
Check SR.6
l=Block Erase Suspended
Standby
O&lock
Erase Completed
Data=DOH
Addr=X
Write
Byte write
Data
Loop
Figure
7. Block
Erase Suspend/Resume
Flowchart
Rev.1.0
LHF08CH3
Bus
0per&l0ll
Byte Write
Suspend
write
w
SR.7=
0
Standby
1
SR.Z=
0
Data&OH
Addr=X
Status Register
Addr=X
Read
Standby
Comments
Command
Data
I---Check SR.7
l=WSM Ready
o=WSM Busy
Check SR.2
t=Byte Write Suspended
04yte
Write Completed
Byte Write Completed
Read Array locations othel
than that being written.
Read
1
c
Figure
8. Byte Write Suspend/Resume
Flowchart
21
LHF08CH3
T
BUS
Operation
Block/Dewce
Address
Block/Device
Address
Command
Write
set
Block/Master
Lock-Bit Setup
Write
Block or Master
set
Lock-Bit
Confirm
Data&OH
Addr=Blcck
Address(Biock).
Dewce Address(Master)
Data=OlH(Block),
FlH(Master)
Addr=Btock Address(Block).
Dewce Address(Master)
f
Read
Status Register
1::3
0
SR.7=
Read
Status Register
Standby
Check SR.7
l=WSM Ready
o=WSM Busy
Data
1
Check if Desired
PULL STATUS
CHECK
qepeat for subsequent
lock-bit set operations.
%ll status check can be done after each lock-bit set operahon
or after a sequence of lock-bit set operations.
Wnte FFH after the last lock-bit set operatmn to place dewce I”
read array mode.
PROCEDURE
Read Status Register
Data(See Above)
BUS
Operation
Comments
Command
Check SR.3
l=Vpp Error Detect
Standby
Check SR.l
l=Dewce
Protect Detect
RP#=V,,
(Set Master Lock-EN Operation)
RP#=VIH, Master Lock-Bit is Set
Standby
(Set Block Lock-Blt
Operation)
Check SR.4.5
Both l=Command
Sequence
Error
Check SR.4
t=Set Lock-Bit
Error
SRS,SR.4.SR.3
and SR., are only cleared by the Clear Status
Register command III cases where multiple lock-bits are set before
full status is checked.
If error IS detected, clear the Status Register before attempting
retry or other error reccweiy.
Figure 9. Set Block
and Master
Lock-Bit
Flowchart
RPV
1 n
.
SHARP
22
LHF08CH3
Bus
Operation
Write
Clear Block
Lock-Bits Setup
Data=GOH
Addr=X
write
Clear Block
Lock-Bits Confirm
Data=DOH
Addr=X
Read
Status Register
Standby
Check SR.7
l=WSM Ready
a;WSM Busy
Write FFH after the Clear Block Lock-Bits
place device
FULL STATUS
CHECK
Comments
Command
operation
Data
to
I” read array mode.
PROCEDURE
Bus
Operation
Device
Command
Protect Error
Sequence
Error
Command
Comments
Standby
Check SR.3
l=Vpp Error Detect
Standby
Check SR. 1
l=Device
Protect Detect
RP#=+,
Master Lock-Bit
Standby
Check SR.4.5
Both l=Command
Sequence
Error
Standby
Check SR.5
l&lea
Block Lock-Bits
1s Set
Error
3R.S.SR.4.SR.3
and SR.l are oniy cleared by the Clear Status
Register command.
I f error IS detected,
clear the Status Register before attempting
retry or other error recovely.
L
Clear Block Lock-Bits
Error
Figure
10. Clear Block
Lock-Bits
Flowchart
Rev. 1.0
LHF08CH3
5 DESIGN CONSIDERATIONS
5.1 Three-Line
Output
RY/BY# is also VOH when the device is in block erase
suspend (with byte write inactive), byte write suspend
or deep power-down
modes.
Control
The device will often be used in large memory arrays.
control
SHARP
provides
three
inputs
to
accommodate
multiple
memory
connections.
Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention
not occur.
will
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory
devices
have
active
outputs
while
deselected
memory devices are in standby mode.
RP#
should
be
connected
to the
system
POWERGOOD
signal to prevent unintended writes
during system
power transitions.
POWERGOOD
should also toggle during system reset.
5.2
23
RY/BY# and Block Erase, Byte Write,
and Lock-Bit Configuration
Polling
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, byte write
and lock-bit configuration
completion. It transitions
low after block erase,
byte write,
or lock-bit
configuration commands
and returns to VOH when
the WSM
has finished
executing
the internal
slgorithm.
5.3
Power Supply
Decoupling
Flash memory power switching characteristics
require
careful device decoupling.
System designers
arc
interested
in three supply current issues; standb
current levels, active current levels and transien
peaks produced by falling and rising edges of CEI
and OE#. Transient current magnitudes depend OI
the device outputs’ capacitive and inductive loading
Two-line
control and proper decoupling capacito
selection will suppress transient voltage peaks. Eacl
device should have a 0.1 pF ceramic capacito
connected between its V,, and GND and between it:
V,, and GND. These high-frequency,
low inductance
capacitors should be placed as close as possible tc
package leads. Additionally, for every eight devices
a 4.7 pF electrolytic capacitor should be placed at thf
array’s power supply connection between V,, ant
GND. The bulk capacitor
will overcome
voltage
slumps caused by PC board trace inductance.
5.4
Vpp Trace on Printed
Circuit
Boards
Updating flash memories that reside in the targe
system
requires
that the printed circuit boarc
designer pay attention to the V,, Power supply trace
The V,, pin supplies the memory cell current for byte
writing and block erasing. Use similar trace width:
and layout considerations
given to the V,, powel
bus. Adequate V,, supply traces and decoupling wil
decrease V,, voltage spikes and overshoots.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
Rev. 1.0
SI-IARP
LHF08CH3
5.5 Vcc, Vpp, RP# Transitions
Block erase, byte write and lock-bit configuration are
not guaranteed if V,, falls outside of a valid VPPH,,z3
range, V,, falls outside of a valid Vcc,,s range, or
RP##V,H or V,,.
If V,, error is detected, status
register bit SR.3 is set to “1” along with SR.4 or SR.5,
depending
on the attempted
operation.
If RP#
transitions to V,, during block erase, byte write, or
lock-bit configuration,
RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-down.
The aborted
operation
may leave data partially
altered. Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to V,, clear the status
register.
The CUI latches
commands
issued by system
software and is not altered by V,, or CE# transitions
or WSM actions. Its state is read array mode upon
Dower-up, after exit from deep power-down
or after
Vcc transitions below V,,,.
After
3ven
must
4rray
array
block erase, byte write, or lock-bit configuration,
after V,, transitions down to V,,,,,
the CUI
be placed in read array mode via the Read
command if subsequent access to the memory
is desired.
5.6 Power-Up/Down
Protection
The device is designed to offer
sccidental block erasure,
byte
:onfiguration
during
power
lower-up, the device is indifferent
protection against
writing, or lock-bit
transitions.
Upon
as to which power
24
supply (V,, or Vcc) powers-up first. Internal circuitry
resets the CUI to read array mode at power-up.
A system designer
must guard against spuriou
writes for V,, voltages above VLKO when V,, i!
active. Since both WE# and CE# must be low for (
command write, driving either to V,, will inhibit writes
The CUl’s two-step command sequence architectun
provides
added level of protection
against datz
alteration.
In-system
block lock and unlock capability prevent!
inadvertent
data alteration. The device is disablec
while RP#=V,, regardless of its control inputs state.
5.7
Power Dissipation
When designing portable systems, designers
mus
consider battery power consumption not only during
device operation, but also for data retention during
system
idle time. Flash
memory’s
nonvolatilio
increases usable battery life because data is retainec
when system power is removed.
In addition,
deep power-down
mode ensures
extremely low power consumption.even
when systerr
power is applied. For example, portable computing
products and other power sensitive applications tha,
use an array of devices for solid-state storage car
consume
negligible power by lowering RP# to VI,
standby or sleep modes. If access is again needed
the devices can be read following the tPHQV ant
t,,,,
wake-up
cycles required after RP# is firs!
raised to V,,. See AC CharacteristicsRead Only
and Write Operations and Figures 15, 16 and 17 for
more information.
Rev. 1.0
SI-IARP
LHF08CH3
6 ELECTRICAL
6.1
Absolute
SPECIFICATIONS
Maximum
*WARNING:
Stressing
the device
beyond
tht
“Absolute Maximum Ratings” may cause permanen
damage. These are stress ratings only. Operation
“Operating
Conditions”
is
no
beyond
the
recommended
and extended exposure beyond the
“Operating Conditions” may affect device reliability.
Ratings*
Operating Temperature
During Read, Block Erase, Byte Write
and Lock-Bit Configuration .. . . .. . .. . . 0°C to +70X(‘)
Temperature under Bias . .. . .. . . .. . .. . . -10°C to +8O”C
Storage Temperature
_.......................
Voltage On Any Pin
(except V,,, V,,,
V,,
25
NOTES:
1. Operating
temperature
is
for
commercia
temperature product defined by this specification.
2. All specified voltages are with respect to GND
Minimum DC voltage is -09
on input/output pin:
and -0.2V
on Vcc and V,,
pins. During
transitions,
this level may undershoot to -2.OV fol
periods
c20ns.
Maximum
DC voltage
or
input/output
pins and V,, is Vcc+OSV
which
during transitions, may overshoot to Vc.c+2.0V fol
periods <20ns.
3. Maximum
DC voltage on V,,
and RP# ma)
overshoot to +14.OV for periods <20ns.
4. Output shorted for no more than one second. NC
more than one output shorted at a time.
-65°C to +125”C
and RP#) . .. .. . . -2.OV to +7.0Vt2)
Supply Voltage . .. . .. . .. .. . .. . .. . . . .. .. . . -2.ov to +7.ov(2)
V,, Update Voltage during
Block Erase, Byte Write and
Lock-Bit Configuration . . .. . .. . . .. -2.OV to +14.0V(2v3)
RP# Voltage with Respect to
GND during Lock-Bit
Configuration Operations . . . .. . -2.OV to +14.0V(293)
Output Short Circuit Current . .. . .. . . .. . .. . .. . .. . .. . . 100mA(4)
5.2 Operating
Conditions
IOTE:
. Block erase, byte write and lock-bit configuration
i.2.1
operations
with Vccc3.OV
should not be attempted.
CAPACITANCE(‘)
Symbol
C,N
cn, ,T
SOTE:
. Sampled,
Parameter
Input Capacitance
Output Capacitance
T/,=+25%,
Typ.
6
8
f=l MHz
Max.
8
12
Unit
pF
pF
Condition
v,,=o.ov
vn, ,,=o.ov
not 100% tested.
Rev. 1.2
SHARP
LHF08CH3
2.2
AC INPUT/OUTPUT
26
1
TEST CONDITIONS
~~~~~~)(~
AC test inputs are driven at 2.7V for a Logic “1” and O.OV for a Logic
input rise and fall times (10% to 90%) <IO ns.
Figure
11. Transient
Input/Output
Reference
“0.” Input timing
Waveform
begins,
and output
timing
ends,
at 1.35V.
timing
ends,
at 1.W.
for Vcc=2.7V-3.6V
1
~~~~iqzq(~
AC test inputs are driven at 3.OV for a Logic “1” and O.OV for a Logic
Input rise and fall times (10% to 90%) ~10 ns.
Figure
12. Transient
Input/Output
Reference
“0.” Input timing
Waveform
begins,
and output
for VCc=3.3Vi0.3V
o::T~~~~~
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins
(2.0 V~L) and VIL (0.8 V~L). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) ~10 ns.
Figure
13. Transient
Input/Output
Reference
Waveform
Test Confi
for Vcc=5V*0.5V
uration
Ca acitance
Loadin
Value
1
1.3v
l-
T
at V+
IN914
DEVICE
UNDER
TEST
0
OUT
CL Includes Jig
Capacitance
Figure
14. Transient
Equivalent
Load Circuit
Testing
Rev.
1.2
SHARP
LHF08CH3
i.2.3
Sym.
27
DC CHARACTERISTICS
‘LI
Parameter
Input Load Current
‘LO
Output Leakage Curreni t
‘cc,
V,,
Notes
DC Characteristics
Vcc=2.7V
1 Vcc=3.3V
Typ. 1 Max. 1 Typ. 1 Max.
/
h&Dnep
‘cc,
V,,
210
PA
12
7
12
17
35
mA
18
8
18
20
50
mA
* -
17
17
‘3
12
-
-
-F
1-i
li
-
35
30
30
25
mA
mA
mA
mA
mA
mA
Power-Down
Read Current
CIA
CMOS Inputs
Vcc=VccMax.
CE#=RP#=V,,+0,2V
TTL lnouts
Vcc=VccMax.
CE#=RP#=V,,,
RP#=GND*0.2V
InI ,,(RY/BY#)=OmA
CMOS Inputs
Vcc=VccMax.
CE#=GND
f=5MHz(3.3V,
2.7V),
’ 8MHz(5V)
InI IT=OmA
TTL Inputs
Vcc=VccMax.
CE#=GND
f=5MHz(3.3V, 2.7V),
8MHz(5V)
In, ,,=OmA
\J,+3.3V+O.3V
\
\Jpp=12.0V+0.6V
\Jpp=3.3V?0.3V
\Jpp=5.OV+O.5V
\Jpp=12.0V&0.6V
Standby Current
‘CCD
FF
&l
1
100
20
100
25
100
PA
2
0.2
2
0.4
2
mA
10
PA
1,5,6
i-t
ccw
CCE
ccws
PPS
PPR
PPD
PPW
PPE
\J,, Byte Write or
:jet Lock-Bit Current
\J,, Block Erase or
(Zlear Block Lock-Bits
(hrrent
\J,, Byte Write or Block
EErase Suspend Current
\/pp Standby or Read
(hrrent
\/pp Deep Power-Down
(hrrent
\/pp Byte Write or Set
1-ock-Bit Current
\/pp Block Erase or
(Zlear Lock-Bit Current
1,7
12
-
-
-
t
12
-
d=
- 1
1
1,7
1.7
1
6
1
10
mA
(3E#=V,,
*2
10
+15
200
-c2
10
-cl5
200
&
10
*15
200
pA
PA
\J,,<V,,
\Jpp>Vcr.
0.1
5
0.1
5
0.1
5
PA
E
qP#=GND,0.2V
t- -
~-
---I=I
\/pp Byte Write or Block
J Irase Suspend Current
1
I -
-
10
I
\Jpp=3.3V*0.3V
\Jpp=5.0v+o.5v
\Jpp=12.0V+0.6V
\JoD=3.3v*o.3v
\
\
40
40
15
20
20
15
-
PPWS
PPFS
Test
Conditions
V,,=V,,Max.
VIN=VcT: or GND
200
I
10 1 200 1 PA
I
\
I
Rev. 1.3
SHARP
LHF08CH3
Sym.
V,,
VI,
Parameter
Input Low Voltage
Input High Voltage
Notes
7
7
VOL
Output Low Voltage
3,7
DC Characteristics
(Continued)
Vcc=2.7V
V,,=3.3V
Vc,=5V
Min.
Max.
Min.
Max.
Min.
Max.
-0.5
0.8
-0.5
0.8
-0.5
0.8
Vcc
2.0
vcc
20
vcc
2.0
+0.5
.
+0.5
+0.5
0.4
0.4
VoH,
VOH2
Output High Voltage
VW
3,7
Output High Voltage
(CMOS)
3,7
V,,,,
V,, Lockout during
Normal Operations
V,,,,,
V,, during Byte Write,
Block Erase or
Lock-Bit Operations
VPPH2 V,, during Byte Write,
Block Erase or
Lock-Bit Operations
V,,,,
V,, during Byte Write,
Block Erase or
Lock-Bit Operations
V, kn
Vcr: Lockout Voltage
RP# Unlock Voltage
‘HH
2.4
2.4
2.4
0.85
Vnc
Vcc
-0.4
0.85
Vcc
0.85
Vnr.
vcc
-0.4
497
!$,c
1.5
1.5
v
V
V
v
1.5
v
-
-
3.0
3.6
-
-
V
-
-
4.5
5.5
4.5
5.5
v
-
-
11.4
12.6
11.4
12.6
V
2.0
8,9
0.45
-
2.0
-
11.4
2.0
12.6
11.4
Test
Conditions
Unit
V
v
Vcc=VccMin.
loL=5.8mA(Vcc=5V)
loL=2.0mA
(Vcc=3.3V, 2.7V)
Vcc=VccMin.
lo,=-2.5mA(Vcc=5V)
lo,=-2.0mA(Vcc=3.3V)
lnH=-1 .5mA(V,,=2.7V)
Vcc=VccMin.
In,=-2.0mA
;C”yoCoCM;n.
-
IJ
V
12.6
V
Set master lock-bit
Override master and
block lock-bit
NOTES:
1. All currents
2*
3.
4.
5.
6.
7.
8.
9.
are in RMS unless otherwise noted. Typical values at nominal V,, voltage and TA=+25”C.
are specified with the device de-selected. If read or byte written while in erase suspend mode,
the device’s current draw is the sum of lccws or IccEs and lCCR or I,,,,
respectively.
Includes RY/BY#.
Block erases, byte writes, and lock-bit configurations are inhibited when V,,<V,,L,,
and not guaranteed in the
range between VPPLK( max.) and V,,,,(min.),
between V,,Ht(max.)
and V,,H,(min.),
between Vppr+(max.)
and VppHs(min.), and above vppH3(maX.).
Automatic Power Savings (APS) reduces typical lCCR to 1 mA at 5V Vcc and 3mA at 2.7V and 3.3V Vcc in static
operation.
CMOS inputs are either Vcc- +0.2V or GND+0.2V. TTL inputs are either V,, or VI,.
Sampled, not 100% tested.
Master lock-bit set operations are inhibited when RP#=VrH. Block lock-bit configuration operations are inhibited
when the master lock-bit is set and RP#=VrH. Block erases and byte writes are inhibited when the corresponding
block-lock bit is set and RP#=VrH. Block erase, byte write, and lock-bit configuration operations are not
guaranteed with Vcc <3.OV or VrH<RP#<VHH and should not be attempted.
RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
‘CCWS
and
‘CC,,
Rev. 1.3
LHFOSCH3
6.2.4
AC CHARACTERISTICS
- READ-ONLY
OPERATIONS(‘)
Vc,=2.7V-3.6V,
Sym.
1
1Read Cycle Time
See 5.OV V,,
Read-Only
Operations
tr,
0"
hny
t&jQ7
tr,,
nx
tncln7
bH
1 Notes
Read Cycle Time
Address to Output Delay
CE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
CE# to Output in Low Z
CE# High to Output in High Z
OE# to Output : in Low Z
OE# High to Output in High Z
Output Hold from Address, CE# or OE# Change,
Whichever Occurs First
NOTE:
See 5.OV V,,
Read-Only
Operations
LH28F008SGL170
Min.
Max.
170
Unit
ns
LH28FOOSSGL150
Min.
Max.
150
150
150
600
55
0
55
0
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
T ,=O”C to +70X
Versiond4)
Parameter
1
to +70X
for notes 1 through 4.
Vc,=3.3V&0.3V,
Sym.
t*“n”
tA”n”
fF, 0”
tpH()”
TpO”C
Versiond4)
Parameter
1 Notes
2
2
3
3
3
3
3
1
(
0
ns
for notes 1 through 4.
Rev. 1.0
SHARI=
LHF08CH3
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t ELQv-bLQv after the falling edge of CE# without impact on tELOv.
3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
Rev. 1.0
SliARP
LHF08CH3
Device
Address
Data Valid
. ..I..#...
Stable
tAVAV
4-
b
VIH
CE#(E)
VIL
VIH
OE#(G)
,,,,.,..I.
VIL
. ..#...I..
VIH
WE#(W)
VIL
VOH
DATA( D/Q)
(DQo-DQ7)
VOL
vcc
tPHQV
VIH
t
RP#(P)
“““““7
VIL
Figure 15. AC Waveform
for Read Operations
RPV
1 n
LHF08CH3
6.2.5
AC CHARACTERISTICS
- WRITE
OPERATION(‘)
Vc,=2.7V-3.t
Sym.
1
32
,=O”C
to +7O”C
Version&)
___-.-_.-
LH28F008SGLi
Parameter
Min.
170
Notes
70
Max.
Unit
ns
:ovety to WE# Going Low
NOTE:
See 5.OV V,,
Sym.
1
NOTE:
See 5V V,,
WE#-Controlled Writes for notes 1 through 5.
Vc,=3.3V+0.3V,
[email protected])
Parameter
Ta=O”C to +7O”C
1 Notes
LH28F008SGL150
Min.
Max.
Unit
AC Characteristics - Write Operations for Notes 1 through 5.
Rev. 1.2
SliARI=
LHF08CH3
v(-.,=sv*o.s\
Sym.
tAvnv
(
( Write Cycle Time
[email protected])
__._. -.._
Parameter
J, T,=O”C
33
to +70X
1 Notes
LH28F008SGL120
Min.
Max.
120
Unit
ns
NOTES:
1. Read timing characteristics
during block erase, byte write and lock-bit configuration operations are the same as
during read-onry operations. Refer to AC Characteri! sties for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A,, and DIN for block erase, byte write, or lock-bit configuration.
4. V,, should be held at V,,H,12,3 ( and if necessary RP# should be held at V,,) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
RPV
13
SHARI=
LHF08CH3
2
1
6-0
3
VIH
ADDRESSES(A)
VIL
VIH
CE#(E)
VIL
VIH
OH(G)
DATA(D/Q)
RY/BY#(R)
VHH
RP#(P)
NOTES:
1. Vcc power-up
2. Write block
3. Write block
4. Automated
5. Read status
6. Write Read
VIH
and standby.
erase or byte write setup.
erase confirm or valid address
erase or program
delay.
register data.
Array command.
-
and data.
Figure 16. AC Waveform
for WE#-Controlled
Write Operations
Rev. 1.0
LHF08CH3
6.2.6
Ic
I Sm.
tA”*”
tpHF,
t
ALTERNATIVE
CE#-CONTROLLED
WRITES(‘)
Vcc:=2.7V-3.f
VetGods)
-~ _.-.~Parameter
I
iv, T,,= :o”c to +7O”C
1 Notes
Write Cycle Time
RP# High Recovery to CE# Going Low
WE# Setuo to CE# Goina Low
I
1
2
Wi
I High
I to CE# Going High
‘ram CE# High
E# High
frorn CE# High
Witdth High
very before Read
LH28FOOSSGLi
- ..--_ ----Min.
I
170
1
c-l
-_.-70
Max.
Sym.
tFHRl
tFHnl
Wc,=3.3V+0.3V,
1
1Write Cycle Time
[email protected])
Parameter
1CE# High to R
1Write Recovery before Read
1Vpp Hold from Valid SRD, RY/BY# High
RP# VHH Hold from Valid SRD, RY/BY# High
I
1
50
5
I
T
5
0
25
0
Unit
IX
IS
ns
70
50
3
NOTE:
See 5.OV Vc-. Alternative CE#-Controlled Writes for notes 1 through 5.
I,
I
I
ns
ns
ns
ns
ns
ns
ns
ns
T,pO”C to +7O”C
1 Notes
1
LH28FOOSSGL150
Min.
Max.
----I- ---1 -~--b0
I
2,4
I
I
2,4
0
Unit
ns
ns
ns
1NOTE:
See 5V Vcc Alternative CE#-Controlled Writes for Notes 1 through 5.
Rev. 7.0
II
SHARP
LHF08CH3
Vo,=5ViO.5
V, TpO”C
to +7O”C
VersiansW
_-_-_ -._-
Sym.
1b
tpHF,
tw, I-,
tr, pc(
hFH
t”pFH
fl\“F, I
, tn”FH
II tFHnx
tFHnx
t
tFHG,
?2vvl
bVPH
1
Parameter
1Write Cycle Time
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
RP# V,,,, Setup to CE# Going High
VP,, Setup to CE# Go ing High
Address Setup to CE# Going High
Data Setup to CE# Going Hig Ih
1 Data Hold frr- rE* Uinh
1Address HOI ” ll”lll ULir r ,KJl,
WE# Hold from CE# Hiah
Write Recovery before Read
Vpp Hold from Valid SRD, RY/BY# High
RP# VHH Hold from Valid SRD, RY/BY# High
1 Notes
I
LH28F008SGL120
Min.
Max.
120
1
0
50
100
100
40
40
E
I
I
I
I
I
1
2
I
I
2
2
3
3
I
2,4
2,4
0
0
0
Unit
ns
I
pi
ns
ns
ns
ns
ns
ns
cl.2
I13
ns
ns
ns
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and
inactive WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A,, and Dl, for block erase, byte write, or lock-bit configuration.
4. V,, should be held at V,,,,,z,s
(and if necessary RP# should be held at V,,) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
Rev. 1.0
II
I
I
LHF08CH3
r
--
--
--
--
VIH
ADDRESSES(A)
tEHAX
VIH
WE#(W)
I
VIH
tEHGL
OE#(G)
i
I
CE#(E)
DATA(D/Q)
VHH
RP#(P)
NOTES:
1. Vcc power-up
2. Write block
3. Write block
4. Automated
5. Read status
6. Write Read
VIH
and standby.
erase or byte write setup.
erase confirm or valid address
erase or program
delay.
register data.
Array command.
Figure
--
and data.
17. AC Waveform
for CE#-Controlled
Write Operations
Rev. 1.0
SHARP
38
LHF08CH3
6.2.7
RESET OPERATIONS
“IJH
RY/BY#(
~~
R)
VOL
VIH
RP#(P)
VIL
(A)Reset
During
Read
Array
Mode
VOH
RY/BY#(R)
VOL
VIH
RP#(P)
VIL
(B)Reset
2.7Vl3.3Vl5V
During
Block
Erase,
Byte Write,
or Lock-Bit
Configuretion
t
vcc
VIL
-
b35VPH
2
VIH
RP#(P)
!
7
VIL
(C)RP#
Figure
18. AC Waveform
rising
Timing
for Reset
Operation
Sym.
tPLPH
tPLRH
t235VPH
I‘JOTES:
I. If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset
will complete within 1OOns.
2!. A reset time, tpHQv, is required from the latter of RY/BY# or RP# going high until outputs are valid.
:3. When the device power-up, holding RP# low minimum 100ns is required after Vcc has been in predefined range
and also has been in stable there.
Rev. 1.3
LHF08CH3
5.2.8
BLOCK
ERASE,
BYTE WRITE AND LOCK-BIT
t
WHQVs
tFHn”2
t
WHQV4
fFH()“4
twHRH1
~
Clear Block Lock-Bits
iwHRH2
Erase Suspend
Set Lock-Bit Time
Byte Write Suspend
Read
Time
Latency Time to
Latency Time to Read
CONFIGURATION
PERFORMANCE(3y4)
2
12
150
10
100
lJ=
2
1.1
5
1
4
S
5.6
7
5.2
7.5
lJ=
9.4
13.1
9.8
12.6
I.=
FHRH7
‘4OTES:
I. Typical values measured at TA=+25”C and nominal voltages. Assumes corresponding
lock-bits are not set.
Subject to change based on device characterization.
!. Excludes system-level
overhead.
3. Sampled but not 100% tested.
I. Block erase, byte write and lock-bit configuration operations with Vccc3.OV and/or VPPc3.0V are not
guaranteed.
Rev. 1.3
LHF08CH3
7 ADDITIONAL
7.1 Ordering
40
INFORMATION
Information
Product line designator for all SHARP Flash products
I
I
I
~L~H/2181F10~0~8/SIC~(H~T/
L
Device Density
008 = B-Mbit
Architecture
S = Regular Block
Power Supply Type
C = SmartVoltage Technology
Operating Temperature]
Blank = 0°C - +7O”C
H = -40°C - +85”C _
Option
1
Order Code
L!-l28F008SCT-L12
V,,=2.7-3.6V
5OpF load,
1.35V I/O Levels
LH28F008SC-L170
I
-IL/l
I
121
L
Aczs
Speed (ns)
85:85ns(5V,30pF),
90ns(5V),
120ns(3.3V), 150ns(2.7V)
12:120ns(5V), 150ns(3.3V)
170ns(2.7V)
Package
T = 40-Lead TSOP
R = 40-Lead TSOP(Reverse
N = 44-Lead PSOP
B = 42 or 48-Ball CSP
Bend)
Valid Operational
Combinations
v,,=5.0*0.5v
v,p3.3+0.3v
5OpF load,
1 OOpF load,
TTL l/O Levels
1.5V I/O Levels
LH28F008SC-L120
LH28F008SC-L1.50
Rev. 1.0
SHARP
8 Package and packing
LHFOSCH3
41
specification
)
1. Package Outline Specification
Refer to drawing No.AAl
2.
Markings
2 - 1. Marking contents
( 1 ) Product name :
( 2 ) Company name :
( 3 ) Date code
YY
(Example)
10
5
LH28F008SCT-L
SHARP
ww
xxx
12
Indicates
the product
was manufactured
(01,02,03,
* - - * * 52,53)
- Denotes the product ion year.
(Lower two digit of the year.)
- Denotes the product ion ref.code
(No marking , A , B , c>
(4)
“JAPAN” is marked on the package when both wafer and assemb ly processes
are
the country of origin.
done in Japan , indicating
2-2.
Marking layout
Refer drawing No.AAl
10 5
(This layout does not define the dimensions
of marking character
and marking position.)
3.
Packing
Specification
(Dry packing for surface
mount packages)
Dry packing is used for the purpose of maintaining
IC quality
after
mounting
packages on the PCB (Printed
Circuit
Board).
When the epoxy resin which is used for plastic
packages is stored at high
humidity,
it may absorb 0.15% or more of its weight
in moisture.
If the surface
mount type package for a relatively
large chip absorbs a large amount of moisture
between the epoxy resin and insert material
(e.g. chip, lead frame) this moisture
may suddenly vaporize
into steam when the entire package is heated during the
soldering
process (e.g. VPS). This causes expansion and results
in separation
between the resin and insert material,
and sometimes cracking
of the package.
This dry packing is designed to prevent the above problem from occurring
in
surface mount packages.
3 - 1 . Packing Materials
Material
Name
Material
Specificaiton
Purpose
Tray
Conductive plastic
(50devices/tray)
Fixing of device
Upper
cover
tray
Conductive
plastic
(ltray/case)
Fixing
of device
_-__________----_-__~~~----.--~~~.~..~--.~~---------~~~-~-.----~~~~~~~-~~-------...~~.~.~~~~~~~....~.~~~~~.....~~~-~...~~~~~--.-~~~~~------~~~~~..~~~~~~........
Laminated aluminum .__-.-._-__......_-_~~~...........~~~~...........-..--..---~~---~....~~~~-...-~~~~~----~-~~~...~-~~~......-----.~....-~~~~~~~
bag Aluminum polyethylene
(lbag/case)
Drying of device
Silica
gel
Drying
of device
Desiccant
_....._--_---___......--~~.~.~......-~..-.--~~~~....~--~~~~~~........--~~~~~~~~.--...............~~.~.......~~.-..-~~~-------~~...~---~.....-..---.....--------P
P
band
Polypropylene
(3pcs/case)
Fixing
of
tray
_____._-_----..-____..------~~.......~~~~.----~~~~~~~~----.~~~~~~.~~.--------~~-~~~~~~~~~~.~~.....~~~~~.....~.~~.-.~.~~~~------~~~~---.~~.~...----~.....-.-----Inner case
Card board
(500devices/case)
Packaging of device
_______-.-.....-____..---~--~~.......~-~~.~.------~.~~~---.------~--.--~.---..-....................~....
_......._.__......__~.~~~~.~~..~~~~~.....~~~~~....~...~
Label
Paper
Indicates
part number, quantity
and date of manufacture
Outer case
Card board
Outer packing of tray
(Devices shall be placed into a tray in the same direction.)
SHARP
LHF08CH3
42
1
3-2.
Outline dimension of tray
Refer to attached drawing
Storage and Opening of Dry Packing
4.
4-l.
Store under conditions shown below before opening t he dry packing
(1)
Temperature range : 5-40°C
(2)
Humidity
: 80% RH or less
4 - 2. Notes on opening the dry packing
(1)
Before opening the dry packing, prepare a working table which is
grounded against ESD and use a grounding strap.
(2)
The tray has been treated to be conductive or anti-static.
If the
device is transferred to another tray, use a equivalent tray.
4 - 3. Storage after opening the dry packing
Perform the following to prevent absorption of moisture after opening.
( 1) After opening the dry packing, store the ICs in an environment with a
temperature of 5--25°C and a relative humidity of 60% or less and
mount ICs within 72 hours after opening dry packing.
4 - 4.
Baking (drying) before mounting
(1)
Baking is necessary
(A)
If the humidity indicator in the desiccant becomespink
(B)
If the procedure in section 4-3 could not be performed
( 2) Recommended
baking conditions
If the above conditions (A) and (B) are applicable,
bake it before
mounting. The recommendedconditions are 16-24 hours at 120°C.
Heat resistance tray is used for shipping tray.
5. Surface Mount Conditions
Please perform the following
quality.
conditions
when mounting ICs not to deteriorate
IC
5-l .Soldering
conditions(The following conditions are valid only for one time soldering.)
Measurement Point
1Mounting Method Temperature and Duration
IC package
Reflow solder ing Peak temperature of 230°C or less,
(air)
duration of less than 15 seconds.
surface
200°C or over,durat ion of less than 40 seconds.
Temperature increase rate of I--4”C/second
260°C or less, duration of less
IC outer lead
Manual soldering
surface
(soldering iron)
than 10 seconds.
5-2.
Conditions for removal of residual
( 1) Ultrasonic washing power
(2)
Washing time
(3)
Solvent temperature
flux
: 25 Watts/liter
or less
: Total 1 minute maximum
: 15-40°C
SHARP
LHF08CH3
43
I
gi
LH28FOO8SCT-L12
i-l
N
dI
z
PKG.BASE
ISEE DETAIL
____
PLANE
A
DETAIL A
~~&&%6$$&0?--3{~&
:cEz : UJ APAN
NOTES: Marking specification
when “JAPAN" is marked.
ml;
II - r;‘lkk.
NAME: TSOP40-P-1020 LEAD FINISH
@(iL
UNIT
DRAWINGNO. j AA1105
\ TIN-LEAC .$%% -95X$73~~s~-9fi#?rir;l~,
/U @%[email protected]!%i.,
i PLATING NOTE Plastic body dimensions do not include burr
of resin.
;
/ mm
StiARl=
LHF08CH3
PKG .dASE
i
Pt. ANE
18. 4+0. 2
/SEE DETAIL
A
DETAIL A
p&-g2
:
5 J AP ANfl ~%WZ?t%[email protected]~-?3tt#%
NOTES : Marking specification
when “JAPAN” is not marked.
lAME [ TSOP40-P-1020
DRAWING NO.
LEAD FINISH ; PLATING NOTE Plastic
body dimensions
g-I2
/
of resin.
i AA1105
UNIT
j
mm
do not include
burr
LHF08CH3
SHARP
4
.o
,
3
(
aJ
-_
I
I
J
:
C1
)
-.
I
I
I
)
I
-
$331
tic%
iAME;TSOP40-lOZOTCM-RH
stiz j
DRAWING
NO. 1 CV644
UNIT !
NOTE
mm
SHARI=
(Supplementary
LHF08CH3
46
data)
LHF08CH3
Recommended mounting
Product name(Package)
Packing specification
Wount ing method
Reflow soldering
conditions
Measurement
Storage
point
conditions
conditions
for two time reflow
soldering
.
LH28F008SCT-L12(TS0P40-P-1020)
Tray (Dry packing)
Reflow soldering
(Air)
Peak temperature
of 230°C or less.
200°C or over, duration
of less than 40 seconds.
Preheat temperature
of 1‘25-150”C,duration
of less
than 180 seconds. Temperature
increase rate of
l--4”C/second.
IC package surface
After opening the dry packing,
store the ICs in
an environment
with a temperature
of 5--25°C and
a relative
humidity of 60% or less.
If doing reflow
soldering
twice,do
the first
reflow
soldering
within
72 hours after opening
dry packing and do the second reflow soldering
within
72 hours after the first
reflow
soldering.
If the above storage conditions
are not
applicable,
bake it before reflow
soldering.
The recommended conditions
are 16-24 hours
at 120°C.
(Heat resistance
tray is used for shipping tray.)
Note
Recommended Reflow
Soldering(Air)
Temperature
Peak
Profile
temoe
rature
Temperaturi
increase
rate
1 -4”C/second
(NO. 990414-X11)
SHARP
LHF08CH3
47
Flash memory LHFXXCXX family Data Protection
Noises having a level exceeding the limit specified in the specification
may be
generated under specific operating conditions on some systems.
Such noises, when induced onto WEBsignal or power supply, may be interpreted as false
commands, causing undesired memory updating.
To protect the data stored in the flash memory against unwanted overwriting,
systems
operating with the flash memory should have the following write protect designs, as
appropriate:
1) Protecting
data in specific
block
When a lock bit is set, the corresponding block is protected against overwriting. By
using this feature, the flash memory space can be divided into the program
section(locked section) and data section(unlocked section). The master lock bit can
be used to prevent false block bit setting.
By controlling RP$, desired blocks can be locked/unlocked through the software.
For further information on setting/resetting
block bit and controlling of IQ’%, refer
to the spec i f icat ion. (See chapter 4.9 and 4.10)
2) Data protection through Vpp
When the level of Vpp is lower than VPPLK (lockout voltage), write operation on the
flashmemory is disabled. Allblocksare lockedandthedata
intheblocksarecompletely
write protected.
For the Iockout voltage, refer to the specification. (See chapter 6.2.3.)
3) Data protection through RP#
When the RP# is kept low during power up and power down sequence such as voltage
transition,
write operation on the flash memory is disabled, write protecting all
blocks.
For the details of RP#control, refer to the specifi cat ion. (See chapter 5.6 and 6.27. >
Rev 1.3