SHARP LZ2336

LZ2336
Two-power supply (+5 V and +12 V) operation
1 / 3 type B/W CCD Area Sensor for EIA
LZ2336
PIN CONNECTIONS
DESCRIPTION
U2336 is a 1 /3-type (6.0 mm) solid-state image
sensor that consists of PN phote-diodes and
CCDS (charge-coupled devices) driven by only
positive voltages. Having approximately 190000
pixels (horizontal 384 X vertical 492), the sensor
provides a stable B/W image.
16-PIN SDIP
FEATURES
d RS
RD
,——_— ——— ——— — ,
GND
● Number of pixels : 362 (H) X 492 (V)
Pixel pitch : 13.6 Mm (H) X 7.5 Am (V)
Number of optical black pixels
: Horizontal; front 2 and rear 20
● Low fixed pattern noise and lag
● No sticking and no image distortion
TOP VIEW
,
1
0s
OD
d
I
.—. ——— ——— ———
H2B
J
$ H2
● Blooming suppression structure
● Built-in output amplifier
dHIB
● Variable electronic shutter (1 /60 to 1/1 O 000S)
● Compatible with EIA standard
● Package : 16-pin SDIPICERDIP](WDIPO1 6-N-0500B)
OFD
GND
dTG
0s
OD RD d
,S
dH1
+H2
dHIB
dH2B
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149
LZ2336
PIN DESCRIPTION
w-
SYMBOL
PIN NAME
I Reset transistor drain
OD
I
Output transistor drain
0s
Video outl)ut
&-
] Reset transistor gate clock
I
Vertical shift register gate clock
dVl, dV2Yd V3, dV4
4HI,4H2,4H16,4H213
Horizontal shift register gate clock
d TG
Transfer gate clock
OFD
Overflow drain
TI
Test terminal
GND
Ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
(Ta = 2SC )
SYMBOL
RATING
UNIT
Out~ut transistor drain voltage
VOD
Oto
+15
v
Reset transistor drain voltage
V RD
Oto
+15
v
Test terminal, TI
VT1
Oto
+15
v
+15
v
Vertical shift register clock voltage
Vdv
–0.3 to +15
v
Horizontal shift register clock voltage
V4H
–0.3 to +15
v
–0.3
Reset sate clock voltage
vdRs
Transfer qate clock voltage
VdTG
Overflow drain voltage
Vom
–0.3
to
to
+15
v
O to
+27
v
Storage temperature
Tstg
– 4 0 t o +85
‘c
ODeratina ambient tem~rature
Topr
–20
‘c
150
to
+70
LZ2336
RECOMMENDED OPERATING CONDITIONS
SYMSOL
PARAMHER
Operating ambient tem~rature
Topr
Output transistor drain voltage
Vm
Reset transistor drain voltage
VRO
Overflow
drain
voltage
When N is applied
When pulse is applied
p-p level
Test terminal, TI
Ground voltage
Transfer gate clock
Vertical shift
register clock
Horizontal shift
register clock
TYP.
MAX.
12.0
12.5
14.0
Voo
Vom
3,0
V40M
12.0
12.5
UNIT
v
v
12.0
v
1
14.0
v
2
VT1
VOD
v
GND
0.0
v
V 4TGL
–0.05
0.0
0,05
v
HIGH level
V 4TGH
12.0
12.5
14.0
v
LOW level
V4v14L
HIGH level
V4v1-4H
LOW level
V 4H1-2L, V+ HIB-2BL
HIGH level
v
4H1-2H, VdHIB-ZBH
v4m
v4R2n
HIGH level
0.05
v
5.0
6.0
v
0.05
0,0
0.05
v
4.7
5.0
6.0
v
0.0
Vm - 10,5
v
VRO -6.0
9.5
–
kHz
f+ Hi-2, f+ H1E2B
6.75
MHz
f+m
6.75
twl, tw2
0.0
5.0
a
8
u
~ L
MHz
10.0
ns
[
fi
@
j
v
15.73
Reset gate clock frequency
Horizontal shift register clock phase
0.0
f+v14
Vertical shift register clock frequency
Horizontal shift register clock frequency
0,05
4.7
–
NOTE
‘c
25.0
LOW level
LOW level
Reset gate clink
MIN.
3
NOTES :
1. When DC voltage is applied, shutter speed is 1/@ seconds.
2. When pulse is applied, shutter speed is less than 1/60 seconds.
3“ n_rL ‘Hi”
~
‘H” “
:, ::,,
151
LZ2336
ELECTRICAL CHARACTERISTICS (Drive method : Field Accumulation)
(Ta=25°C, Operating conditions : typical values for the recommended operating conditions, Color
temperature of light source : 3200 K / IR cut-off filter (CM-500, 1 mmt))
PARAMETER
Photo response non-uniformity
Saturation signal
SYMBOL
MIN.
TYP.
PRNU
Vsat
MAX.
UNIT
15
‘?/0
2
mV
3
500
NOTE
Dark output voltage
Vdark
5.0
15.0
mV
1, 4
Dark signal non-uniformity
DSNU
1.5
5.0
mV
1, 5
mV
6
– 76
dB
7
1.0
0/0
8
5.0
mA
Sensitivity
Smear ratio
Image lag
Blooming suppression ratio
R
160
SMR
220
– 85
Al
ABL
1000
9
Output transistor drain current
iOD
2.5
Output impedance
Ro
400
. Tt?e standard output voltage is defined as 150 mV by the
average output voltage under uniform illumination.
● The standard exposure level is defined when the average
output voltage is 150 mV under uniform illumination.
NOTES :
1. Ta : +60CC
2. The image area is divided into 10x 10 segments. The segment’s voltage is the average output voltage of all the
pixels within the segment. PRNU is defined by (Vmax –
Vmin)/Vo, where Vmax and Vmin are the maximum and
the minimum values of each segment’s voltage respectively, when the average output voltage Vo is 150mV.
3. The image area is divided into 10x 10 segments.
The saturation signal is defined as the minimum of each
segment’s voltage which is the average output voltage of
all the pixels with!n the segment, when the exposure level
is set as 10 times, compared to standard level,
4. The average output voltage under a non-exposure condition.
5. The image ~ea is d!vlded into 10x 10 segments. DSNU is
defined by (Vdmex – Vdmin) under the non-exposure con-
152
6
7
8
9
Q
dition where Vdmax and Vdmin are the maximum and the
minimum values of each segment’s voltage, respectively,
that is the average output voltage over all pixels in the
segment.
The average output voltage when a 10W Iux I ight source
attached with a 90”A reflector is imaged by a lens of F4,
f50 mm.
The sensor is adjusted to poslt(on a V/l O square at the
center of image area where V is the vertical length of the
image area, SMR is defined by the ratio of the output
voltage detected during the vertical blanking period to the
maximum of the pixel voltage in the V/l O square.
The sensor is exposed at the exposure level corresponding to the standard condition preceding non-exposure condition. Al is defined by the ratio between the output voltage measured at the 1st field during the non-exposure
period and the standard output voltage.
The sensor is adjusted to position a V/l O square at the
center of image area. ABL is the ratio between the exposure at the standard condition and the exposure at a
point where a blooming is observed.
W2336
PIXEL STRUCTURE
OPTICAL BLACK
(2 PIXELS)
362 (H) X 492
OPTICAL BLACK
(20 PIXELS)
(v)
SPECTRAL RESPONSE EXAMPLE
100
80
/
\
20
o
400
800
1 Wo
1200
WAVE LENGTH (rim)
153
LZ2336
TIMING DIAGRAM EXAMPLE
VERTICAL TRANSFER TIMING
(ODD FIELD)
HD
VD
525 1
mu
10
n
n
n
n
n n n
n n
n
n
n
17
n n
n n
u u u u u u u
u
u 1
u
u
u
u
u
u
u
u
u
u
u
u
u
u 1
1
u
u
u
u
[ u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n n
n
n
n
n
n
n
n
n
n
n
n II
n
n
n
n
n
n n
n
n
n
n
n n
n
n
n
17
n
n
n
n
n
n
n
n
n
6TG
~
~ +4 a + 6 ~ + 8 4 0
0s
n n n
I
492
3 5 7 9 1 1
i+++++
2
4
6
8
10
12
485487489491
JI
II
II
(EVEN FIELD)
II
Iu
II
263
272
HD
VD
~~~1
4 V1
1
v
1
u u
u
u
u
u
u
u
u
u
u
u
u
u
u
[ II
II Il.
279
n
n n n n
u
u
n n
n
u
u
u~ u
u
n
n n n
u
u
u
u 1
u
u
u
u
1
u
u
u
u
u
u
u
u
u
u
~~~~
U!l n
n
n
n
n
n
n n
n
d TG
JI
483485467489491
0s
&26
n
n
n n
n
n
n
6 8 1 0
::+++
& 4 ; 0 4 ; 2
II
HORIZONTAL TRANSFER TIMING
HD
I
I
dH1
4,2
d es
0s
m~
...............362 OB(20)
0B(2) 1...0UTPUT(362) . . . . . . . . . . . . . . . . . . . . . .
I
I
I
I
U2336
READOUT
(ODD FIELD)
4V4
dTG
n
I
I
(EVEN FIELD)
HD
d VI
d V2
r--
155
I
I
o
LZ2336
“$
——
CCD OUT
O
+RS
O
VOD
O
I
I
L
I
o