SE4100L PointCharger™ GPS Receiver IC Preliminary Information Applications Product Description The SE4100 is an integrated GPS receiver designed to receive the L1 signal at 1575.42MHz. The receiver has a low IF architecture, and integrates all of the amplifier, oscillator, mixer and demodulation functions. Mobile phone & PDA accessories Portable navigation Personal security Security systems Asset tracking Telematics equipment The external component count is low, requiring just a 16.368MHz crystal and 11 passive components in its minimum configuration. This and the 24 pin LPCC package result in a very small circuit footprint, which is complemented by just 30mW operating power. Features 30 mW power consumption 4x4mm 24 pin LPCC package Single conversion radio with integrated IF filters On-chip, Gain switchable LNA Low LNA noise figure, 1.3dB typ. On chip crystal oscillator can be powered up independently Fully integrated VCO, VCO tank circuit and PLL. Remote antenna current detection Two digitally controlled shutdown modes enable either to part to be powered down entirely or for just the 16 MHz clock supply to the baseband processor to be maintained. A switchable gain LNA enables the SE4100 to be used with a local passive antenna or with a remote active antenna without changing the circuit configuration. The on-chip VCO and PLL generates the required LO frequency from the external 16.368MHz crystal. All of the VCO and LO chain is integrated. An image reject mixer downconverts the RF signal to a 4.092MHz IF. The integrated IF filter feeds a combiner, limiter and output latch. The output signal is a 1-bit quantized 4.092 MHz digital IF at CMOS levels. Ordering Information Type Package Remark SE4100L-R 24 Pin LPCC Shipped in Tape & Reel Functional Block Diagram ~ ~ ~ RF Amp LNA LNAIn MixIn Mixers ~ ~ ~ AntOK AntDetP ÷96 AntDetN Xtal1 Ant current monitor I Phase Det. Rev 1.3 Aug 6/02 Phase Shift / Combiner +45° / -45° Σ Clk ~ Vtune RxEnb Xtal Oscillator OscEnb 27-DST-01 Q Quadrature ÷2 ~ Xtal2 IF Filter VCO D Q DataOut D-type ClkOut LNAOut LowGain SE4100 Block Diagram 1 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information 2 17 Vtune AntDetN 3 16 VDD LNAIn 4 15 LowGain 5 AntOK 6 27-DST-01 VccRF Vss2 LNAOut 22 23 24 18 1 VccLNA Vtune 17 2 AntDetP VDD 16 3 AntDetN Xtal1 Xtal1 15 4 LNAIn 14 Xtal2 Xtal2 14 5 LowGain 13 R3 R3 13 6 AntOK SE4100L Bottom View 10 11 12 12 11 10 9 8 7 R0 R1 R2 R2 R1 R0 RxEnb ClkOut DataOut Die Pad 9 8 ClkOut Rev 1.3 OscEnb RxEnb 7 DataOut SE4100L Top View Vss1 VccVCO 19 AntDetP 21 MixIn 20 OscEnb MixIn Vss1 21 18 20 VccRF 22 1 VccVCO Vss2 23 VccLNA 19 LNAOut 24 Pin Out Diagram Aug 6/02 2 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Pin Out Description Pin No. Name Description 1 VccLNA Power supply connection for LNA 2 AntDetP Connection to battery side of antenna current sensing resistor 3 AntDetN Connection to antenna feed side of antenna current sensing resistor 4 LNAIn 5 LowGain 6 AntOK 7 DataOut 8 ClkOut Buffered version of Xtal Osc output / D-type clock 9 RxEnb Enable control for Receiver (all circuits except Reference oscillator and Data Registers), active high input 10 R0 Reserved internal connection, must be tied to VDD for normal operation 11 R1 Reserved internal connection, must be tied to VDD for normal operation 12 R2 Reserved internal connection, must be tied to VDD for normal operation 13 R3 Reserved internal connection, must be tied to VDD for normal operation 14 Xtal2 Connection to crystal 15 Xtal1 Connection to crystal 16 VDD 17 Vtune 18 OscEnb Enable control for Reference oscillator, active high input 19 VCCVCO Decoupling connection for VCO power supply 20 MixIn Mixer input signal, 50Ω single ended 21 VSS1 Ground 22 VCCRF 23 VSS2 24 LNAOut Die Pad Gnd 27-DST-01 Rev 1.3 LNA Input LNA Gain control, High = low gain Antenna OK output flag (high = antenna current OK) Data Output Power supply for digital circuits (Xtal Oscillator, Data Registers and Bias circuits) Charge pump output / VCO control voltage input Power supply connection for all RF circuits except the LNA Ground LNA Output, 50Ω single ended Ground connection for all circuits via die pad Aug 6/02 3 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Functional Description LNA The internal LNA consists of two transistors cascaded. The biasing, gain switching circuit and output matching to 50Ω is contained on the IC. A conceptual diagram of the internal circuit is shown below. VccLNA Vbias2 The state of the logic output on the AntOK pin is dependent on the voltage drop between AntDetP and AntDetN pins, AntDetP being the higher dc voltage. The current setting this voltage is adjusted by changing the value of the external current sense resistor between these pins. Voltage between AntDetP and AntDetN (∆VANT) <0.125 0.25>∆V>0.5 >0.75 Logic Output AntOK Low High Low Vbias1 LNAOut LNAIn Gain Control The AntOK pin is a CMOS output designed to interface directly to the LowGain input pin, so that in the event the supply to the external active antenna is either shorted or open circuited, the internal LNA gain is switched to the high gain setting. The external current sense resistor should be chosen according to the typical current of the external antenna IANT, using the formula: R EXT = The input match to 50Ω requires three external components, two capacitors and an inductor. The inductor should be a high Q type, e.g. wirewound or microstrip; otherwise the low noise figure of the LNA will not be obtained. The output match is optimized to allow for a short length of narrow track between the IC package and a filter. Exact lengths and track widths will depend on the board material and thickness. The gain of the amplifier is switched between high and low settings by the CMOS level compatible LowGain input pin. Internally, this reduces the gain of the second stage only in the low gain setting, which maintains a low noise figure for the amplifier. The power supply for the amplifier is provided through the VccLNA pin. Care should be taken with the PCB layout to ensure that the power supply cannot act as a bypass around any filter between the LNA output and the mixer input. 0.375 I ANT Mixer RF Input The mixer RF input pin, MixIn, is a single ended 50Ω input, designed to either interface to the LNAOut pin or to the output of an external filter using only a dc blocking capacitor, and without additional matching components. The input is a common base configuration providing a wideband 50Ω termination. A conceptual diagram of the input circuit is shown below: Vbias1 0.5mA MixIn 800Ω Antenna Current Monitor The antenna current monitor is a window comparator designed to operate with common mode input voltages above the chip VCC. It is designed to monitor the supply current to an external active antenna and provide a logic output indicating if the current is within the desired range. 27-DST-01 Rev 1.3 Aug 6/02 4 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information The filter type chosen should require a termination impedance of 50+j0Ω. Examples of suitable types are shown on the application schematic diagram. The PCB layout should keep the track from the filter to the MixIn pin as short as possible to minimize pickup and mismatch (if the track is not 50Ω). A dc blocking capacitor should be used, even if the filter does not present a dc path, as the MixIn pin has 0.4V dc present which may be detrimental to the filter. A filter will improve the performance of the receiver in the presence of out of band blocking signals, but is not essential if operation in the presence of such signals is not critical. If the filter is not fitted, the LNAOut pin should be connected to the MixIn pin via a coupling capacitor. The PCB layout should keep the track from the Vtune pin to the loop filter as short as possible to minimize noise pickup. Crystal Oscillator The crystal oscillator is a Pierce configuration, as shown in the diagram below. The application circuit is designed to work with parallel resonant crystals with a load capacitance of 12pF. Xtal1 Xtal2 PLL and Loop Filter The entire phase-locked loop generating the local oscillator for the mixer is contained on-chip, with the exception of the loop filter. Values provided on the application circuit should be used, as these will provide optimum performance under all conditions. The capacitors may be ceramic dielectric types, with either COG/NP0 or X7R dielectric. Higher capacitance per unit volume dielectrics should be avoided as the absolute tolerance and temperature stability may compromise system performance. 27-DST-01 Rev 1.3 Aug 6/02 The PCB layout should minimize the lengths of the tracks to Xtal1 and Xtal2 pins. The capacitors at each terminal of the crystal should be mounted adjacent to the crystal and have a low impedance connection to the ground plane. 5 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Absolute Maximum Ratings These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of the device. Avoid operating the device outside the recommended operating conditions defined below. This device is ESD sensitive. Handling and assembly of this device should be at ESD protected workstations. Symbol VCC, VDD VAntDetP, VAntDetN TSTG Parameter Min. Max. Unit Supply Voltage -0.3 +4.6 V Voltage On Any Pin With Respect To VSS except AntDetP and AntDetN Pins -0.3 VDD+0.3 V Voltage On AntDetP and AntDetN Pins With Respect To VSS -0.3 +6.0 V Storage Temperature Range -65 +150 °C Recommended Operating Conditions Symbol TA VCC, VDD Parameter Min. Typ. Max. Unit Operating Temperature -40 +25 +85 °C Supply Voltage 2.7 3.6 V Max. Unit DC Electrical Characteristics Symbol ICC Parameter Total Supply Current, All Circuits Active ICC(OSC) Supply Current, Oscillator Only Active ICC(OFF) Supply Current, No Circuits Active 27-DST-01 Rev 1.3 Aug 6/02 Min. Typ. 9 mA 1.0 mA 10 µA 6 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information AC Electrical Characteristics LNA Symbol VCCLNA Parameter LNA Supply Voltage Note Min. Typ. 2.7 Max. 3.6 Unit V ICC Supply Current , RxEnb = ‘1’ 1.2 mA S21 Forward Gain, fRF=1570MHz to 1580MHz, LowGain = ‘0’, Pin = -80dBm 20 dB NF Noise Figure, fRF=1570MHz to 1580MHz, LowGain = ‘0’ 1.3 dB S21LOW Forward Gain, fRF=1570MHz to 1580MHz, LowGain = ‘1’, Pin = -80dBm 7 dB NF Noise Figure, fRF=1570MHz to 1580MHz, LowGain = ‘1’ 2.5 Z11 Input Impedance, Single Ended Input, With External Matching Circuit S22 Output Return Loss, 50Ω system, Single Ended Output IIP3H High Gain Mode Input IP3, Tones At 1575 ± 5MHz @ –60dBm -25 dBm IIP3L Low Gain Mode Input IP3, Tones At 1575 ± 5MHz @ –60dBm -15 dBm P1dB Input Power At Which Gain Falls By 1dBm -34 dBm tR Recovery Time From –3dBm Input Overload Signal VIL Input Low Level, LowGain Input VIH Input High Level, LowGain Input IIN LowGain Input Current 27-DST-01 Rev 1.3 Aug 6/02 4 Ω 30-j75 -10 4 dB 10 µsec 0.6 V VDD-0.6 -0.1 dB V 0.1 µA 7 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Receiver Symbol Parameter Note Min. Typ. Max. Unit ICC Supply Current , RxEnb = ‘1’ 8.0 mA NF Noise Figure, fRF=1570MHz To 1580MHz, Input to ‘MixIn’ 10 dB IIP3 Input IP3, Tones 1575 ± 5MHz @ -40dBm (Mixer and IF Filter Only) -15 dBm S11 Input Return Loss, 50Ω System tR Recovery Time From –30dBm Input Overload Signal fIF IF Centre Frequency 4 -10 dB 10 µsec 4.092 MHz BW -3dB Bandwidth 2.0 MHz ∆Tg Group Delay Variation, fC ± BW/2 0.1 µsec Av2 Attenuation At fC ± BW 11 dB Av4 Attenuation At fC ± 2.BW 27 dB VCO and Local Oscillator Symbol Parameter Note Min. Typ. Max. Unit fVCO VCO Centre frequency MHz L1k LO SSB Phase noise at 1kHz offset -65 dBc/Hz L10k LO SSB Phase noise at 10kHz offset -65 dBc/Hz L100k LO SSB Phase noise at 100kHz offset -85 dBc/Hz 3142.656 Crystal Oscillator Symbol Parameter ICC Supply Current, Crystal Oscillator And Clock Buffers, OscEnb = ‘1’ fXTAL Oscillator Frequency Note Min. Typ. Max. Unit 1.0 mA 16.368 MHz Crystal Parameters Mode Parallel fund. Frequency 16.368 ESR CLOAD tSTART 27-DST-01 Oscillator Startup Time To 95% Of Final Amplitude And Within 10ppm Of Final Frequency Rev 1.3 Aug 6/02 MHz 50 12 Ω pF 100 µsec 8 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Antenna Current Monitor Symbol Parameter ∆VANT Voltage Between AntDetP And AntDetN For AntOK = High ∆VANT Voltage Between AntDetP And AntDetN For AntOK = Low For Low Current Condition ∆VANT Voltage Between AntDetP And AntDetN For AntOK = Low For High Current Condition VAntDetP Voltage Range On AntDetP For Normal Operation Vcc-0.5 5.25 V VAntOK AntOK Output Voltage, Antenna OK, 1mA Current Source Vcc-0.5 Vcc V VAntOK AntOK Output Voltage, Antenna Not OK, 1mA Current Sink 0 0.5 V 27-DST-01 Rev 1.3 Aug 6/02 Note Min. 0.25 Typ. Max. Unit 0.5 V 0.125 V 0.75 V 9 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Timing Characteristics Symbol Parameter Note Min. Typ. Max. Unit tPEr Clock Period 60 nsec tPWL Clock Low Width 20 nsec tPWH Clock High Width 20 nsec tDEL Clock To Data Delay Time 5 tSETUP Setup Time 21 tHOLD Hold Time 26 nsec nsec 31 nsec tR Rise Time, 10-90% 8 nsec tR/F Rise and Fall Time, 10-90% 8 nsec Output Data Timing Diagram tPER = 60ns min tPWH = 20ns min CLKOut tDEL= 5ns max tR(10-90%) = 8ns max tPWL= 20ns min tSETUP = 21ns min tHOLD = 31ns max, 26ns min DataOut tR/F(10-90%) = 8ns max 27-DST-01 Rev 1.3 Aug 6/02 10 of 16 OscEnb RxEnb ClkOut 22p C1 L2 47nH 10% C12 10n C2 1p C13 22p L1 TBD 10% R2 39Ω C3 100p 6 5 4 3 2 1 AntOK LowGain LNAIn AntDetN AntDetP VccLNA ~ ~ ~ IC1 SE4100 C4 22p R3 Xtal2 Xtal1 VDD Vtune OscEnb 13 14 15 1n C8 580pF 17 16 C6 C5 100p 18 C9 10n d pa DataOut Antenna +5V (Antenna LNA Supply) Vcc 23 Vss2 24 LNAOut DataOut 7 RxEnb 9 ClkOut 8 22 VccRF 21 Vss1 R0 10 MixIn 19 R1 11 Aug 6/02 VccVCO Rev 1.3 ie D 12 27-DST-01 R2 20 1575.42MHz Filter eg. Sawtek 855969 or Murata SAFCC1G57AA0S00 X1 16.368MHz C10 22pF 120pF 6.8K C7 R1 C11 9pF PointCharger™ GPS Receiver IC Preliminary Information SE4100L Figure 1: Typical Schematic Diagram 11 of 16 OscEnb RxEnb ClkOut DataOut Antenna 22p C1 C2 1p L1 TBD 10% 6 5 4 3 2 AntOK LowGain LNAIn AntDetN AntDetP VccLNA 7 1 24 LNAOut DataOut Vcc 10p C4 8 IC1 SE4100 R0 23 Vss2 ClkOut 21 Vss1 22 VccRF RxEnb 9 C5 100p R3 Xtal2 Xtal1 VDD Vtune OscEnb pa 20 11 ie 10 19 MixIn R1 Aug 6/02 VccVCO Rev 1.3 R2 27-DST-01 D 12 C3 100p C9 10n 13 14 15 16 17 18 1n C8 X1 16.368MHz C10 22pF 6.8k 580pF C11 9pF 120pF C7 R1 C6 PointCharger™ GPS Receiver IC Preliminary Information SE4100L Figure 2: Minimum Component Count Application Schematic Diagram d 12 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Typical PCB Layout (With Filter And Antenna Current Sensing) Total size of layout = 15.5 x 10.5mm 15.5mm VCC R1 C12 Antenna VCC F1 C11 C7 C4 C5 C6 10.5mm C13 C8 X1 R2 C3 L2 SiGe Antenna SE4100 C1 L1 C2 C9 C10 C Osc Enable C12 F1 C11 C7 C4 C5 C13 C6 C8 X1 C3 R2 SiGe L2 Rx Enable Clock Out Data Out R1 a C a SE4100 C1 L1 C2 C9 C10 Actual size Typical PCB Layout (Minimum Component Count) Total size of layout = 12.5 x 9.0mm 12.5mm C11 VCC R1 C6 C9 C3 C2 C4 C5 9.0mm C1 X1 C7 Antenna SiGe C8 L1 SE4100 C10 R1 C6 C9 C3 C2 C5 X1 C7 SiGe SE4100 C8 L1 Osc Enable Rx Enable Clock Out Data Out C11 C4 C1 C10 Actual size (R2, C12, C13, L2, F1 not used) Note: These layouts are for illustration purposes only. Reference designs and layout information are available from SiGe Semiconductor. 27-DST-01 Rev 1.3 Aug 6/02 13 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Typical Bill Of Materials for Application PCB Layout Component Value IC1 27-DST-01 Rev 1.3 Type Manufacturer SE4100 SiGe C1 22pF 0402 ceramic C2 1pF 0402 ceramic C3 100pF 0402 ceramic C4 22pF 0402 ceramic C5 100pF 0402 ceramic C6 580pF 0402 ceramic C7 120pF 0402 ceramic C8 1nF 0402 ceramic C9 10nF 0402 ceramic C10 22pF 0402 ceramic C11 9pF 0402 ceramic C12 10nF 0402 ceramic C13 22pf 0402 ceramic L1 TBD 10% 0402CS-??NXJ Coilcraft L2 47nH, 10% 0402CS-47NXK Coilcraft R1 6.8kΩ 0402 R2 39Ω 0402 F1 1575.42MHz 855969 Sawtek X1 16.368MHz KSX series AVX Aug 6/02 14 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information Package Information 27-DST-01 Rev 1.3 Aug 6/02 15 of 16 SE4100L PointCharger™ GPS Receiver IC Preliminary Information http://www.sige.com Headquarters: Canada Phone: +1 613 820 9244 Fax: +1 613 820 4933 2680 Queensview Drive Ottawa ON K2B 8J9 Canada [email protected] San Diego United Kingdom Phone: +1 858 668 3541 Fax: +1 858 668 3546 South Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire CM23 5DB Hong Kong Phone: +1 852 9177 1917 Phone: +44 1279 464 200 Fax: +44 1279 464 201 Product Preview The datasheet contains information from the product concept specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Preliminary Information The datasheet contains information from the design target specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Final The datasheet contains information from the final product specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Production testing may not include testing of all parameters. Information furnished is believed to be accurate and reliable and is provided on an “as is” basis. SiGe Semiconductor Inc. assumes no responsibility or liability for the direct or indirect consequences of use of such information nor for any infringement of patents or other rights of third parties, which may result from its use. No license or indemnity is granted by implication or otherwise under any patent or other intellectual property rights of SiGe Semiconductor Inc. or third parties. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SiGe Semiconductor Inc. products are NOT authorized for use in implantation or life support applications or systems without express written approval from SiGe Semiconductor Inc. RangerChargerTM, StreamChargerTM, PointChargerTM, and LightChargerTM are trademarks owned by SiGe Semiconductor Inc. Copyright 2002 SiGe Semiconductor All Rights Reserved 27-DST-01 Rev 1.3 Aug 6/02 16 of 16