SII S2100

Contents
Features........................................................... 1
Applications...................................................... 1
Pin Assignment ................................................ 1
Block Diagram.................................................. 1
Terminal Description ........................................ 2
Mode Table ...................................................... 2
Absolute Maximum Ratings ............................. 2
Recommended Operating Conditions.............. 2
DC Electrical Characteristics ........................... 3
AC Electrical Characteristics............................ 3
Read Mode Operation...................................... 4
Counter Hold Mode Operation ......................... 4
Program Mode Operation ................................ 5
Input Priority ..................................................... 6
Notes................................................................ 6
Dimensions ...................................................... 7
Characteristics ................................................. 8
S-2100R
64-bit FUSE ROM
The S-2100R is a CMOS 64-bit serial FUSE ROM. It has a low standby
current (0.3 mA max., VDD=1.5 V) and has a wide operating voltage
range. Data can be read serially by clock pulses from address 1 to
address 64. All the addresses are initialized at “H” so writing into “L”
can be done only once.
n Features
·
·
n Applications
Low standby current (0.3 mA max.,
Wide operating voltage range
·
·
·
VDD=1.5 V)
Pager ID ROM
Cordless telephone
Security equipment
n Pin Assignment
8-pin DIP
Top view
8-pin SOP
Top view
DATA
1
8
VDD
CE/PE
2
7
RST
3
6
CLK
COUNTER
OUT
VSS
4
5
DATA
1
8
VDD
CE/PE
2
7
RS
3
6
CL
4
5
PD/VPP
COUNTER
OUT
PD/VPP
VSS
Figure 1
n Block Diagram
COUNTER
OUT ƒ
CLK
RST
COUT
CL
†
‡
6-BIT
COUNTER
RS
READ /
WRITE
CONTROL
VP
ROW
DECODER
DIN
COLUMN
DECODER
A1
A0
DE
64-BIT
FUSE ROM
MEMORY
CELL
MATRIX
SENSE
AMP.
DOUT
CE/PE ‚
DATA •
A2
A3
A4
A5
VPP
DATA
CONTROL
VPP
CONTROL
ˆVDD
„VSS
VPI
…
PD/VPP
Figure 2
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1
64-bit FUSE ROM
S-2100R
n Terminal Description
Table 1
Pin No.
Symbol
1
DATA
Data input/output terminal
Tri-state data input/output terminal
2
CE/PE
Mode select terminal
Mode select terminal
(Refer to operation mode table)
3
Pin Name
Description
COUNTER
Counter output terminal
OUT
6-bit counter; 64th bit detection output terminal
4
VSS
Negative power supply terminal
Normally, connected to GND.
5
PD/VPP
Program voltage input terminal
Input terminal of writing voltage to FUSE memory at 21 V.
(Refer to operation mode table.) Pull-down resistor built
in.
6
CLK
Clock input terminal
Clock input terminal of 6-bit counter.
falling edge.
Operates at the
7
RST
Reset input terminal
Reset input terminal of 6-bit counter.
Operates at “L”.
8
VDD
Positive power supply terminal
Normally, connected to +1.1 to +5.5 V.
n Mode Table
Table 2
Terminal
CE/PE
PD/VPP
Read
VSS
VSS
Input possible
Input possible
Data output
Counter hold
VDD
VSS
Input impossible
Input impossible
High impedance
Program
VDD
VPP
Input impossible
Input impossible
Data input
Read
CLK
n Absolute Maximum Ratings
RST
DATA
Table 3
Parameter
Symbol
Ratings
Unit
Power supply voltage
VDD
-0.3 to +6.5
V
PD/VPP input voltage
VPP
-0.3 to 26
V
Input voltage
VIN
VSS -0.3 to VDD+0.3
V
Output voltage
VOUT
VSS -0.3 to VDD+0.3
V
Storage temperature
under bias
Vbias
-30 to +85
°C
Storage temperature
Vstg
-40 to +125
°C
n Recommended Operating Conditions
Table 4
Parameter
Power supply voltage
High level input voltage
2
Symbol
VDD
VIH
Low level input voltage
VIL
Operating temperature
Vopr
Conditions
tCH=15ms
Min.
Typ.
Max.
Unit
V
Ta=25°C,
Read,
1.1
1.5
5.5
Ta=25°C,
Write
4.5
5.0
5.5
V
Ta=25°C,
Read
VDD-0.3
¾
VDD
V
Ta=25°C,
Write
VDD-0.3
¾
VDD
V
Ta=25°C,
Read
-0.3
¾
0.3
V
Ta=25°C,
Write
-0.3
¾
0.5
V
-20
¾
70
°C
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64-bit FUSE ROM
S-2100R
n DC Electrical Characteristics
Table 5
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
fCLK=50 kHz
¾
¾
20
mA
¾
¾
0.3
mA
20
21
22
V
Operating current
consumption
IDDO
VDD=1.5 V,
Standby current
consumption
IDDS
VDD=1.5 V, RST=VDD
CLK=VDD, CE/PE=VSS
PD/VPP input voltage
VPP
¾
¾
150
mA
IOH
VDD=1.1 to 5.5 V, VOH=VDD-0.3 V
-300
¾
¾
mA
IOL
VDD=1.1 to 5.5 V, VOH=0.3 V
300
¾
¾
mA
RD
VDD=1.5 V
0.1
0.2
0.4
MW
PD/VPP input current
IPP
Output current
Pull-down resistance
n AC Electrical Characteristics
1. Read mode
Table 6
(Ta=25°C, VDD=1.5 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
RST hold time
tRH
5.0
¾
¾
ms
Read cycle time
tRC
2.0
¾
¾
ms
CLK hold time
tCH
5.0
¾
¾
ms
Access time
tACC
¾
¾
5.0
ms
CE/PE setup time
tCES
2.0
¾
¾
ms
RST setup time
tRS
5.0
¾
¾
ms
CLK setup time
tCS
5.0
¾
¾
ms
CE access time
tCE
¾
¾
5.0
ms
Output disable time
tWZ
¾
¾
500
ns
CLK and RST inhibit time
tCRI
¾
¾
500
ns
Load : 60 pF
2. Write mode
Table 7
(Ta=25°C, VDD=5.0 V, VPP=21 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
CE-data setup time
tCDS
0.5
¾
¾
ms
Data setup time
tDS
0.5
¾
¾
ms
Data hold time
tDH
0
¾
¾
ms
CE-data hold time
tCDH
2.0
¾
¾
ms
VPP rise time
Program pulse width
VPP rise slope
tr
20
¾
¾
ms
tPW
8.0
¾
¾
ms
DVPP
¾
¾
4
V/ms
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64-bit FUSE ROM
S-2100R
Read Mode Operation
1
By setting the CE/PE terminal to “ L” level, the S-2100R enters the read mode. * Next, adding an RST pulse causes the
contents of the memory bit of address 1 to be output at the DATA terminal; the rising of the RST pulse latches the data and
2
3
stabilizes it. * Reading of addresses from 2 to 64 can be done by adding a CLK pulse sequentially after reading address 1. *
As soon as address 64 has been read, the COUNTER OUT terminal outputs “ H” level. When it finishes reading address 64, it
does not accept any more CLK pulses and the counter does not operate. The data of address 64 is maintained till address 1 is
read by the RST pulse.
CE/PE
tCES
tRH
tRS
RST
tRC
CLK
tCH
tRC
tRC
tACC
tCE
DATA
tACC
Address 1 output
Address 2 output
Address 3 output
Address 1 output
Figure 3 Read mode timing
*1
*2
*3
When both the CLK and RST terminals are at “ H” level.
When the RST terminal is at “ L” level, the latch is transparent and the data is recognized by the rising of the RST pulse.
Data read by the CLK pulse is latched at its rising.
Counter Hold Mode Operation
By setting the CE/PE terminal to “ H” level, the S-2100R enters the counter hold mode and the DATA terminal becomes high
4
impedance.
*
In counter hold mode, the CLK and RST pulses which fall while the CE/PE terminal is at “ H” level are recognized to be invalid
and there is no change in counter and data output. When the CE/PE terminal is set to “ L” level again, it returns to the
condition in which it was before the counter hold mode.
tCES
CE/PE
tCRI
RST
tCS
CLK
DATA
tWZ
Address M
output
Address M+1 output
Figure 4 Counter hold mode timing
4
*
4
When both the CLK and RST terminals are at “ H” level.
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Address M+1 output
64-bit FUSE ROM
S-2100R
n Program Mode Operation
By setting the CE/PE terminal to “H” level, the S-2100R enters the counter hold mode and at the same time enters the program
mode. *5
Writing is done in program mode after selecting the address in read mode. *6 Select the address, and supply “H” level to the
CE/PE terminal and “L” level to the DATA terminal, with the writing pulse VPP being supplied to the PD/VPP terminal. “L” level can
be written into the selected address only once. *7 *8
If you coutinue writing from address 1 to 64, the output of the COUNTER OUT terminal goes to “H” level, just like in the read mode,
and no more CLK pulses or writing pulses in program mode can be accepted.
CE/P
RS
CL
DATA
tCDH
tCDS
Address 1
output
Address 1
output
Data input
Address 2
output
Data input
tDH
tDS
PD/VPP
tPW
Figure 5
*5
*6
*7
*8
Program mode timing
In program mode, operate at VDD=5.0 V to assure reliability of the data writing.
The selection of addresses is possible only in read mode. Address 1 is selected by RST pulses and writing proceeds
sequentially from address 1 by CLK pulse.
All the memories are initially at “H” level, so writing into “L” can be done. When data is at “H” level, writing voltage cannot
be supplied to the memory.
Address 1 is selected again by the RST pulse. The addresses which are not written to “L” level are at “H” level, so writing
“L” level in these addresses is possible.
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64-bit FUSE ROM
S-2100R
n Input Priority
In read mode, priority is given to either the CLK or RST terminal, whichever is entered first. Whichever pulse is input earlier is
recognized to be valid from the rising till the end of the operation. If the pulse input later is at “L” level, the signal is ignored, even
though the effective pulse input earlier rises. *9
If the CLK and RST pulses are input, the mode shifts from read mode to counter hold mode when both the CLK and the RST
terminals go to “H” level. *10
If the CLK and RST pulses which are input in the counter hold mode are still at “L” level after setting the CE/PE terminal to “L” level,
these CLK and RST terminals are ignored. The mode shifts to read mode and data which is held before the shift is output at the
DATA terminal. *11
In program mode, inputting the DATA terminal before the CE/PE terminal goes to “H” level is prohibited. Also, charging the
writing voltage from the PD/VPP terminal is prohibited when the CE/PE terminal is at “L” level. In program mode, input to the DATA
terminal muse be decided before charging the writing voltage. *12
*9 Input of the CLK and RST pulses is not recognized as valid unless both pulses are input at “H” level.
*10 The counter hold mode is entered when reading of the CLK and RST pulses has been finished and DATA output has been
stabilized .
*11 No more CLK or RST pulses are accepted unless both the CLK and RST terminals are at “H” level.
*12 If data input is changed while writing voltage is supplied, the S-2100R does not accept the changed data.
n Notes
Memory should not be accessed for at least 10 ms after voltage is supplied and goes to VDD.
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Seiko Instruments Inc.
64-bit FUSE ROM
S-2100R
n Dimensions
1. 8-pin DIP
8.8 (9.2 max.)
5
8
6.4
4
1.5
1
1.0
7.62
3.4±0.25
4.5 max.
0.51 min.
2.54
2.69 min.
0.46±0.15
0°~15°
0.25±0.15
Unit:mm
Figure 6
2. 8-pin SOP
8
5.0 (5.15 max.)
5
0.55
5.0
1
6.8±0.4
0.15 +0.1
-0.05
4
1.6±0.15
2.15 max.
0 min.
1.27
0.35 +0.1
-0.05
Unit: mm
Figure 7
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64-bit FUSE ROM
S-2100R
n Characteristics
1. Standby current consumption IDDSAmbient temperature Ta
104
VDD=
6.0V
4.0V
2.0V
1.0V
103
IDDS
(nA)
102
101
100
-40
-10
20
50
80
Ta (°C)
2. Access time tACC-
3. Access time tACCPower supply voltage VDD
Power supply voltage VDD
0.7
8
-40°C
-10°C
20°C
50°C
80°C
6
tACC
(ms)
80°C
50°C
20°C
-10°C
-40°C
0.6
tACC
(ms)
0.5
0.4
4
0.3
0.2
2
0.1
0
0
1.0
1.5
2.0
2
VDD (V)
8
3
4
VDD (V)
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6