® SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator FEATURES PGND 1 10 LX ■ 1A Output Current SGND 2 9 PVIN SP6652 ■ 1.2MHz Constant Frequency Operation 8 SVIN FB 3 ■ 97% Efficiency Possible 10 Pin MSOP 7 SYNC COMP 4 ■ Pin Selectable Forced PWM or PWM/PFM Modes 6 MODE 5 SD ■ Ultra Low Quiecent Current in PFM Mode: 50µA ■ 500nA (Max.) Shutdown Current Now Available in Lead Free Packaging ■ Output Adjustable Down to 0.75V ■ No External FET's or Schottky Diode Required APPLICATIONS ■ Uses Small Value Inductors and Ceramic ■ Mobile Phones Output Capacitors ■ PDA's ■ Low Dropout Operation: 100% Duty Cycle ■ DSC's ■ Soft Start and Thermal Shutdown Protection ■ MP3 Players ■ Easy Frequency Synchonization ■ USB Devices ■ Small 10 Pin MSOP and 10 Pin DFN Package ■ Point of Use Power DESCRIPTION The SP6652 is high efficiency, synchronous buck regulator ideal for portable applications using one Li-Ion cell, with up to 1A output current. The 1.2MHz switching frequency and PWM control loop are optimized for small value inductor and ceramic output capacitor, for space constrained portable designs. At light load, the SP6652 can operate in either PFM mode for high efficiency, or PWM mode for constant frequency. In addition, the input voltage range of 2.7V to 5.5V; excellent transient response, output accuracy, and ability to transition into 100% duty cycle operation, further extending useful battery life, make the SP6652 a superior choice for a wide range of portable power applications. The output voltage is externally programmable down to 0.75V. A logic level shutdown control, external clock synchronization, and forced-PWM or automatic control inputs are provided. Other features include soft-start, over current protection and 140(C over-temperature shutdown. TYPICAL APPLICATION SCHEMATIC VOUT 3.3V at 1A 4.7µF 340k 100k 8k 10µF 1 2 3 4 5 PGND LX SGND PVIN FB SP6652 SVIN COMP SYNC SD MODE 10 9 8 7 6 VIN 10µF 6.2nF ENABLE SHUTDOWN Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 1 © Copyright 2004 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. PVIN,SVIN ........................................................................... -0.3V to 0.3V PGND to SGND ...................................................................... -0.3V to 0.3V LX to PGND ................................................................ - 0.3V to PVIN+0.3V Storage Temperature .................................................. -65 °C to 150 °C Operating Temperature ................................................. -40°C to +85°C Lead Temperature (Soldering, 10 sec) ....................................... 300 °C ELECTRICAL CHARACTERISTICS VIN=UVIN=VSDN=3.6V, VOUT=VFB, IO = 0mA, TAMB = -40°C to +85°C, typical values at 27°C unless otherwise noted. PARAMETER Input Voltage Operating Range FB Set Voltage FB Input Voltage Overall FB Accuracy FB Set Voltage (PFM Mode) Switching Frequency SYNC Tracking Frequency SYNC Input Current SYNC Logic Threshold Low SYNC Logic Threshold High PWM On-Time Blanking PMOS Switch Resistance NMOS Switch Resistance Inductor Current Limit (PWM Mode) Inductor Current Limit (PFM Mode) LX Leakage Current SVIN Quiecent Current MIN UVLO TYP MAX 5.5 UNITS V 0.735 0.75 0.765 V -1 -4 0.01 1 4 µA % V MHz MHz µA Ω 1 1 -1 1.4 1.4 1 0.6 TA = 27°C, FB = COMP VFB = 0.8V FB = COMP 1.7 50 0.25 0.25 1.4 300 0.1 60 2 1 102 3 100 TBD 500 TBD ns Ω Ω A mA µA µA nA mA µA 2.6 1 2.7 500 2.8 V 1 -1 6 2 0.01 1.2 PVIN Quiecent Current UVLO Undervoltage Lockout Threshold, VIN falling UVLO hysteresis Soft Start Current SD\, MODE Input Current SD\, MODE Logic Threshold Low SD\, MODE Logic Threshold High Slope Compensation Rising Over-Temperature Trip Point Over-Temperature Hysteresis ERROR AMPLIFIER Error Amplifier Transconductance Error Amplifier Output Impedance Error Amplifier Max Sink Current Error Amplifier Max Source Current 0.758 1.2 1.2 0.01 0.3 CONDITIONS 0.6 0.6 1.6 3 1 0.4 1.6 700 140 14 0.5 15 15 1 1 40 40 1.5 60 60 % µV µA V V mA/µs °C °C SD\=0V PFM Mode PWM Mode Shutdown, SD\=0V VCOMP = 0.6V ILX = 0 PWM Mode VCOMP = 1V mS mΩ µA µA Note: This thermal Resistance Figure Applies only to a package with the exposed pad soldered to a PCB. Faliure to do this results in, approximately, a three-fold increase in thermal resistance. Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 2 © Copyright 2004 Sipex Corporation PIN DESCRIPTION PIN NUMBER PIN NAME 1 PGND Power Ground Pin. Synchronous rectifier current returns through this pin. 2 SGND Internal Ground Pin. Control circuitry returns current to this pin. 3 FB 4 COMP Compensation pin for error loop. Connect an R and C in series to ground to control open loop pole and zero. 5 SD\ Shutdown control input. Tie pin to VIN for normal operation, tie to ground for shutdown. TTL input threshold. 6 MODE Connect this pin to VIN to force PWM operation and to SGND for automatic PWM/PFM selection, for a better light load efficiency. 7 SYNC An external clock signal can be connected to this to synchronize the switching frequency. The part runs in PWM mode in the precence of a sync clock. 8 SVIN Internal supply voltage. Control circuitry is powered from from this pin. Use an RC filter close to the pin to cut down supply noise. 9 PVIN Supply voltage for the output driver stage. Inductor charging current passes through this pin. 10 LX Date:5/25/04 DESCRIPTION External feedback network input connection. Connect a resistor from to ground and from FB to output voltage to control the output voltage. Regulation point at FB=0.75V Typical. Inductor switching node. Inductor tied between this pin and the output capacitor to create regulated output voltage. SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 3 © Copyright 2004 Sipex Corporation Date:5/25/04 4 0.3V 0.75V FB DCHG A=3 Pre-amp 0.75V 0.75V 0.3V 0.75V REFOK Low Vo Indicator NOSWITCH VREF V0P3R Reference VIN FB_LO PWM/PFM Inductor Current Clamp CLAMP PARK PFM PFM Node Park Clamp Gm R S Qn Q Q1 SOFT STRT 2uA +V Internal Supply COMP BLIM Soft Start CHG PFM Loop Comparator Error Amp REFOK 7.5mV GO PWM +V SVIN 7.5mV PWM Mode Comparator Shutdown SD A Translator 300mA M Charging PMOS Replica MODE Q2 SOFT STRT GO PFM GO PWM CLK RST CLR OSC FB_LO CLK CHG - by 2 CLR + - + - +V DCHG Driver CLK Peak and Trough Current Detector CNTR S R Current Loop Comparator GO PFM PWM/PFM Clock Generator SYNC SYNC S R ILPK Slope Compensation Mode Select PVIN Changing PMOS Internal GND 0mA LX 100mA LX SGND PGND L1 SD Co RL RF2 RF1 VOUT FUNCTIONAL DIAGRAM SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corporation DETAIL DESCRIPTION keep the effective current slope compensation constant (remembering current is being compensated, not voltage) the voltage slope must be proportional to RPMOS. To account for this, the slope compensation voltage is internally generated with a bias current that is also proportional to RPMOS. Current Mode Control and Slope Compensation The SP6652 is designed to use low value ceramic capacitors and low value inductors, to reduce the converter’s volume and cost in portable devices Current mode PWM control was, therefore, chosen for the ease of compensation when using ceramic output capacitors and better transient line rejection, which is important in battery powered applications. Current mode control spreads the two poles of the output power train filter far apart so that the modulator gain crosses over at -20dB/decade instead of the usual -40dB/decade. The external compensation network is, simply, a series RC connected between ground and the output of the internal transconductance error amplifier. Over Current Protection In steady state closed loop operation the voltage at the COMP pin controls the duty cycle. Due to the current mode control and the slope compensation, this voltage will be: V(COMP) (ILPK* RPMOS + MCV *TON+ VBE(Q1) The COMP node will be clamped when the its voltage tries to exceed V(BLIM) + VBE (Q1). The VBE(Q1) term is cancelled by VBE(Q2) at the output of the translator. The correct value of clamp voltage is, therefore: It is well known that an unconditional instability exists for any fixed frequency current-mode converter operating above 50% duty cycle. A simple, constant-slope compensation is chosen to achieve stability under these conditions. The most common high duty cycle application is a Li-Ion battery powered regulator with a 3.3V output (D ≥ 90%). Since the current loop is critically damped when the compensation slope (denoted MCV) equals the negative discharge slope (denoted M2V), the amount of slope compensation chosen is, therefore: V(BLIM) = IL(MAX)* RPMOS + MCV *tON The IL(MAX) term is generated with a bias current that is proportional to RPMOS, to keep the value of current limit approximately constant over process and temperature variations, while the MCV *TON is generated by a peak-holding circuit that senses the amplitude of the slope compensation ramp at the end of TON. M2 = dIL/dTOFF =-VOUT/L = -3.3V/4.7µH = -702mA/µs There is minimum on-time (TON) generated even if the COMP node is at 0V, since the peak current comparator is reset at the end of a charge cycle and is held low during a blanking time after the start of the next charge cycle. This is necessary to swamp the transients in the inductor current ramp around switching times. The minimum TON (50ns, nominally) is not sufficient for the COMP node to keep control of the current when the output voltage is low. The inductor current tends to rise until the energy loss from the discharge resistances are equal to M2V = M2*RPMOS MCV = -M2V = 702mA/µs*0.2Ω = 140mV/µs, for RPMOS = 0.20Ω The inductor current is sensed as a voltage across the PMOS charging switch and the NMOS synchronous rectifier (see BLOCK DIAGRAM) During inductor current charge, V(PVIN)-V(LX) represents the charging current ramp times the resistance of the PMOS charging switch. To Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 5 © Copyright 2004 Sipex Corporation DETAIL DESCRIPTION: Contunued the energy gained during the charge phase. For this reason, the clock frequency is cut in half when the feedback pin is below 0.3V, effectively reducing the minimum duty cycle in half. Above V(FB)=0.3V the clock frequency is normal (see TYPICAL OPERATIONG CHARACTERISTICS: Inductor current vs. VOUT) Automatic Mode Selection PFM Control for Light Loads If the MODE pin is connected to SVIN, the part will be forced into a PWM-only regulation mode. If the MODE pin is connected to SGND, the mode selection circuitry decides whether the converter should be in PWM or PFM mode, depending on the load. Light loads call for the PFM loop, which is forced into DCM as well. Medium to heavy loads activate the PWM loop. If the MODE pin is connected to SGND, under light load conditions the SP6652 will transition to a PFM regulation mode. In this mode of operation, V(FB) is compared to the reference voltage plus 7.5mV, nominally (see BLOCK DIAGRAM). This sets the regulation point 1% higher than the PWM regulation voltage to prevent bouncing between modes at loading conditions near threshold. Starting from a PWM state, the Peak and Trough Current Detector window comparator monitors the peak inductor current during charge and the trough inductor current during discharge. Both the peak and trough are monitored because the ripple current varies considerably across the application spectrum. The lossless inductor current ripple is: When VOUT falls below the PFM regulation point the voltage loop comparator issues a command to turn on the PMOS switch to the output stage logic. The current sensing comparator compares the voltage across that switch to a reference set up by a biased replica of the PMOS switch, to set the peak PFM inductor current (nominally 300 mA). This comparator stops the charging cycle and initiates the discharge through the synchronous NMOS rectifier. IL(RIPPLE)=(VIN-VOUT)*(VOUT/VIN)*(1/L *fCLK) Where fCLK is the switching frequency (1.2MHz, nominally). If the peak inductor current is below 100mA or the trough reaches 0mA (or less) during one cycle, then the current is defined as low enough for PFM mode. This has to happen during 32 consecutive clock cycles before the output signal goes high and switches modes. This delay is to avoid prematurely switching into PFM mode during a negative load transient. Any new charging cycles are inhibited until a third comparator, the under-current comparator, which is setup to detect the instant when the inductor is fully discharged (NMOS VDS >0) enables the voltage loop. This keeps the PFM mode in discontinuous conduction mode (DCM). Once in PFM mode, the regulated output voltage will be 1% higher than in PWM and continue regulating there, as described in the PFM Control For Light Loads section. When the load increases past the point where the PFM mode can regulate while remaining in DCM (which is l 1/2 of the peak inductor current in PFM, or 1/ 2*300mA=150mA), the output voltage will start dropping. When it falls 1% below the reference voltage, that is 2% below the PFM regulation point, the PWM Mode Comparator will switch and set the Mode Control latch to PWM mode. A timer disables both the Current Loop and Trough Current comparators 7µs after entering DCM, to save supply current under very light load conditions. The normal light load supply current is, nominally, 135µA whereas the very light load supply current is 60µA. Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 6 © Copyright 2004 Sipex Corporation DETAIL DESCRIPTION: Contunued The low frequency pole for L1=5µH is 4kHz, the second pole is 500kHz, and the gain-bandwidth is 20kHz. The total loop crossover frequency is chosen to be 200kHz, which is 1/6th of the clock frequency. This sets the 2nd modulator pole at 2.5 times the crossover frequency. Therefore the gain of the error amplifier can be 200kHz/20kHz = 10 at the first modulator pole of 4kHz. The error amp transconductance is 1mS, so this sets the RZ resistor value in the compensation network at 10/1mS = 10kΩ. The zero frequency is placed at the first pole to provide at total system response of -20dB/decade (the zero from the error amp cancels the first modulator pole, leaving the 1 pole rolloff from the error amp pole). The compensation capacitor becomes: Voltage Loop and Compensation in PWM Mode The voltage loop section of the circuit consists of the error amplifier and the translator circuits (see functional diagram). The input of the voltage loop is the 0.75V reference voltage minus the divided down output voltage at the feedback pin. The output of the error amplifier is translated from a ground referred signal (the COMP node) to a power input voltage referred signal. The output of the voltage loop is fed to the positive terminal of the Current Loop comparator, and represents the peak inductor current necessary to close the loop. The total power supply loop is compensated with a series RC network connected from the COMP pin to ground. Compensation is simple due to current-mode control. The modulator has two dominant poles: one at a low frequency, and one above the crossover frequency of the loop, as seen in the graph below, Linearized Modulator Frequency Response vs. Inductor Value. Cc = 1/(2*π*Rz*pole1) = 1/(6.28*10kΩ*4kHz) = 4nF 1 20K 2 2.0M 3 50K 16K 1.6M 40K 12K 1.2M 30K 8K 0.8M 20K 4K 0.4M 10K 0 0 >> 0 3u 2u 4u 5u 6u 1 Mod_pole1 2 Mod_pole2 3 Gbw_modfb L1VAL 7u 8u 9u 10u Conditions: VIN=5V, VOUT=3.3V, fCLK=1.2MHz, COUT=10µF, and MCV=132mV/µs. The inductor is varied from 2µH to 10µH Linearized Modulator Frequency Response vs. Inductor Value. Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 7 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION L1 VOUT 4.7µH R C3 10µF 1 PGND 2 SGND FBH R 3 FB 4 COMP FBL Cc 8k 5 SD LX PVIN SVIN SYNC MODE 10 9 8 7 6 R1 VIN 10Ω C2 1µF C1 10µF SP6652 Rz 16.2nF SD MODE SYNC Complete Application Circuit. Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 8 © Copyright 2004 Sipex Corporation PACKAGE: 10 PIN MSOP (ALL DIMENSIONS IN MILLIMETERS) D e1 Ø1 E/2 R1 R E1 E Gauge Plane L2 Ø1 Seating Plane Ø L L1 1 2 e Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2) Dimensions in (mm) 10-PIN MSOP JEDEC MO-187 (BA) Variation MIN NOM MAX A - - 1.1 A1 0 - 0.15 A2 0.75 b 0.17 - 0.27 c 0.08 - 0.23 0.85 D 3.00 BSC E 4.90 BSC 0.95 E1 3.00 BSC e 0.50 BSC e1 2.00 BSC L WITH PLATING c 0.4 0.60 0.80 L1 - 0.95 - L2 - 0.25 - N - 10 - R 0.07 - - R1 0.07 - Ø 0º Ø1 0º (b) BASE METAL D A2 - A 8º - b 15º A1 1 Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 9 © Copyright 2004 Sipex Corporation PACKAGE: 10 PIN DFN Bottom View Top View D b e D/2 1 2 E/2 E2 E K L D2 Pin 1 identifier to be located within this shaded area. Terminal #1 Index Area (D/2 * E/2) A A1 A3 Side View DIMENSIONS Minimum/Maximum (mm) 10 Pin DFN (JEDEC MO-229, VEED-5 VARIATION) COMMON HEIGHT DIMENSION SYMBOL A A1 A3 b D D2 e E E2 K L MIN NOM MAX 0.80 0 0.90 1.00 0.02 0.05 0.20 REF 0.18 0.25 0.30 3.00 BSC 2.20 2.70 0.50 PITCH 3.00 BSC 1.40 1.75 0.20 0.30 0.40 0.50 10 PIN DFN Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 10 © Copyright 2004 Sipex Corporation ORDERING INFORMATION Part Number Operating Temperature Range Package Type SP6652EU .................................................. -40°C to +85°C ........................................................ 10 Pin MSOP SP6652EU/TR ............................................ -40°C to +85°C ........................................................ 10 Pin MSOP SP6652ER .................................................. -40°C to +85°C ........................................................... 10 Pin DFN SP6652ER/TR ............................................ -40°C to +85°C ........................................................... 10 Pin DFN Available in lead free packaging. To order add "-L" suffix to part number. Example: SP6652EU/TR = standard; SP6652EU-L/TR = lead free /TR = Tape and Reel Pack quantity is 2,500 for MSOP and 3,000 for DFN. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 11 © Copyright 2004 Sipex Corporation