AN069 Fixed Frequency Flyback Controller with Ultra-low No Load Power Consumption The Future of Analog IC Technology Design Guidelines for Flyback Converter Using HFC0400 Application Note Prepared by San Chen Dec, 2012 AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION ABSTRACT This paper presents design guidelines for flyback power supply with HFC0400 of MPS as shown in Figure1. Design of a flyback converter with peak current control is quite simple and straightforward through the step-by-step design procedure described in this application note. Experimental results based on the design example are presented in the last part. T1 Output Input 85~265Vac VCC * TIMER FB CS GND 1 8 HV 2 HFC0400 3 6 4 5 VCC VCC DRV * The circuit in red is optional. Implements external OVP and OTP function by pulling the TIMER pin down. Figure 1: Flyback converter using HFC0400 AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION INDEX 1. HFC0400 INTRODUCTION ............................................................................................................... 4 2. FREQUENCY FOLDBACK ................................................................................................................ 4 3. X-CAP DISCHARGE FUNCTION ...................................................................................................... 4 4. DESIGN PROCEDURE ..................................................................................................................... 5 A. Predetermine Input and Output Specifications............................................................................ 5 B. Determine the Startup Circuitry .................................................................................................. 6 C. Reflected output voltage VRO, Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Selection......................................................................................................................................... 7 D. Primary side Inductance Lm ....................................................................................................... 8 E. Current Sense Resistance.......................................................................................................... 9 F. Transformer Design.................................................................................................................. 10 F-1. Transformer Core Selection............................................................................................ 10 F-2. Primary and Secondary Winding Turns .......................................................................... 11 F-3. Wire size ........................................................................................................................ 11 F-4. Air gap............................................................................................................................ 12 G. Design the RCD snubber ......................................................................................................... 12 H. Design the Output Filters.......................................................................................................... 14 I. Low-pass Filter on CS Pin ......................................................................................................... 15 J. Jittering Period .......................................................................................................................... 15 K. X-cap Discharge Time Estimate ............................................................................................... 15 L. External OTP or OVP Circuit by TIMER Pin Latch-off (Optional)............................................... 17 5. DESIGN SUMMARY........................................................................................................................ 18 6. EXPERIMENTAL VERIFICATION ................................................................................................... 20 7. REFERENCES ................................................................................................................................ 24 AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION 1. HFC0400 INTRODUCTION HFC0400 is a current mode controller with full features. The controller supports continuous conduction mode (CCM) with a wide input voltage range as the built in slope compensation helps to avoid subharmonic oscillation when duty is larger than 0.5. The IC implements a frequency foldback down to 25 kHz at light load condition for excellent efficiency at all load range. HFC0400 offers frequency jittering for better EMI performance which helps to spread out energy in conducted noise. At very light load, the controller enters burst mode to achieve very low standby power consumption. HFC0400 also has the XCAP discharge function, through the HV Pin signal motoring, it can discharge the X-CAP when the input is unplugged, and the power loss caused by the X-CAP discharge resistors can be eliminated. Variable protections like Vcc under Voltage Lockout (UVLO), Over Load Protection (OLP), Over Voltage Protection (OVP), Over Temperature Protection (OTP) and Brown-Out Protection are integrated in the IC to minimize the external component count. This paper presents practical design guidelines for an off-line flyback converter employing HFC0400. Step-by-step design procedure for flyback converter using HFC0400 is introduced in this application note, mainly including transformer design, output filter design and the key components selection. 2. FREQUENCY FOLDBACK Figure 2 shows the switching frequency vs. FB and peak current vs. FB. At heavy load condition (FB>2V), the switching frequency is fixed with frequency jittering for EMI reduction. The FB voltage regulates the primary side peak current signal (sensed by sensing resistor) connected to CS pin with an internal 1/3 voltage gain. When the load decreases to a given level (1.33V<FB<2V), the controller freezes the peak current (0.67V) and reduces the switching frequency down to 25kHz which helps to reduce the switching loss. If the load continues to decrease, the switching frequency is fixed to 25kHz and the peak current decreases with decreasing of FB voltage to avoid audible noise. When the load continues to decrease to very light or no-load, HFC0400 enters burst-mode operation. The controller stops the gate switching signal when the FB voltage drops below the lower burst threshold VBRUL— 0.32V. And the output voltage starts to decrease which causes the FB voltage to increase again. Once the FB voltage exceeds the higher burst threshold VBRUH—0.46V, the switching resumes. The FB voltage then falls and rises repeatedly. The burst mode operation alternately enables and disables the switching of the MOSFET thereby reducing switching loss at no load or light load conditions. Figure 2: Frequency and Peak Current vs. FB 3. X-CAP DISCHARGE FUNCTION X capacitors are usually connected across input terminals of AC-DC power supply to filter out differential mode EMI noise. These X capacitors may present a safety hazard because they can store unsafe levels of high-voltage energy for long period of time after the AC is disconnected. To meet safety standards, the traditional method is placing resistors in parallel with the X capacitor (if the X-cap is larger than 0.1μF) to discharge the X-cap in a specified time. The time constant of the X-cap and paralleled resistor should meet C X ⋅ R discharge < 1sec . Considering the tolerance of X-cap (±10% or ±20% typical) and discharge resistors (±1% or ±5% typical) in application, there should be certain margin for AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION the time constant C X ⋅ R discharge ≤ 0.78 sec . However, these bleeding resistors produce a power loss while the AC is connected, for example, if Rdischarge=2MΩ, there will be 35mW loss at 265Vac RMS input. The loss is a significant contributor to no-load and standby input power consumption. The following table shows power loss of bleeding resistor with different X-cap. Table 1: Power loss of bleeding resistor vs Cx Cx (Deviation ±20%) Bleeding resistance (Deviation ±5%) Power loss at 265VAC input 0.22μF 3.4MΩ 20.7 mW 0.33μF 2.2MΩ 31.9 mW 0.47μF 1.5MΩ 46.8 mW 1μF 780kΩ 90 mW HFC0400 implements a novel X-cap discharge function without the bleeding resistors. When the AC voltage is applied, internal high voltage current source turns off to block current flow into the HV Pin and the IC will continuously monitor the HV voltage. When the AC voltage is unplugged, the IC will turns on high voltage current source after a delay time to discharge the X-cap. So the traditional bleeding resistors can be removed and the standby power loss of system is significantly reduced. 4. DESIGN PROCEDURE A. Predetermine Input and Output Specifications z Input AC voltage range: Vac(min), Vac(max), for example 85Vac~265Vac RMS Note: due to the brown-out function in HFC0400, the minimum input should be larger than 82VacRMS. z DC bus voltage range: Vin(max), Vin(min). z Output: Vo, Io(min), Io(max), Pout. z Estimated efficiency: η, It is used to estimate the power conversion efficiency at lowest input voltage to calculate the maximum input power. Generally, η is set to be 0.75~0.85 according to different input range and output applications. Then the maximum input power can be given as: Pin = Pout η (1) Figure 3 shows the typical waveform of DC bus voltage. The DC input capacitor Cin is usually set as 2μF/W of input power Pin for the universal input condition. For 230Vac single range application, the capacitance can be 1μF/W of input power. Vin VDC(max) DC input Voltage VDC(min) AC input Voltage T1 t Figure 3: Input Voltage Waveform AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION From the waveform above, the AC input Voltage VAC and DC input Voltage VDC can be got as: VAC (Vac ,t) = 2 ⋅ Vac ⋅ cos(2 ⋅ π ⋅ f ⋅ t) VDC (Vac ,t) = 2 ⋅ Vac 2 − 2 ⋅ Pin ⋅t Cin (2) (3) By setting |VAC|=VDC, T1 where DC input voltage had reached to its minimum VDC(min) can be solved by (2) and (3). VDC(min) = VDC (Vac(min) ,T1) (4) Then, the minimum average DC input voltage Vin(min) can be got as: Vin(min) = 2 ⋅ Vac(min) + VDC(min) 2 (5) The maximum average DC input voltage Vin(max) can be got as: Vin(max) = 2 ⋅ Vac(max) (6) B. Determine the Startup Circuitry Figure 4 shows the startup circuit, when power is on, the internal high voltage current source charges C1 from AC line by R1, D1 and D2. As soon as VCC voltage reaches VCCOFF (14.5V typically), the current source turns off and controller detects the voltage on HV pin. Once voltage on HV pin is higher than HVON before VCC drops down to VCCSS (11.5V typically), the controller starts switching, or brownout is defaulted to lock driver output, VCC will drop down to 5.3V and the current source turns on to recharge C1. The supply of the IC is taken over by the auxiliary winding of the transformer after the controller starts switching. If VCC falls back below 8.0V, switching pulse is stopped and the current source turns on again (see Figure 5). The value of R1 and C1 determines the start up delay time of system, the larger R1 or C1, the larger start up delay. For example, if R1 is chosen as 20kΩ, C1 is chosen as 47μF, the start up delay time is about 700ms at 85VAC input. Furthermore, the time duration of Vcc drops from VccOFF to VccSS for brown-out detection should be larger than half of input period, the Vcc capacitance can be got as equation(7), where ICC(noswitch) is the inner consumption close to ICClatch, Tinput is period of AC input. As a result, Vcc capacitance is recommended to be larger than 10μF. C1 > AN069 Rev. 1.0 12/30/2013 ICC(noswitch) ⋅ 0.5 ⋅ Tinput VCCOFF − VCCSS www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (7) 6 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION Input 85~265Vac D1 D2 R1 1 8 HV 2 HFC0400 GND 3 6 4 5 VCC C1 * Figure 4: The Startup Circuit of HFC0400 Figure 5: The Startup and VCC UVLO of HFC0400 C. Reflected output voltage VRO, Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Selection VRO is the reflected output voltage to primary side during secondary diode conduction: VRO = N ⋅ (VO + VF ) , where VF is the forward voltage drop of secondary diode. Considering the efficiency and voltage stress on MOSFET and secondary diode, the optimal selection of VRO depends on the output specification. For lower voltage output applications (such as 5V), VRO is recommended at 80V~110V. For higher voltage output application (such as 19V), VRO is recommended at 100V~135V. Once VRO is set, the turns ratio N can be obtained. AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION Figure 6 shows the typical Drain-Source voltage waveform of the primary MOSFET and secondary rectifier diode in a flyback converter. From the waveform, the primary MOSFET Drain-Source voltage rating VP-MOS can be got as: VP −MOS = Vin(max) + VRO + 60V (8) k where k is the derating factor which is typically selected as 0.9, 60V spike voltage is assumed here. The secondary rectifier diode voltage rating VDIODE can be got as: VDIODE = Vin(max) / N + VO + 20V (9) k 20V spike voltage is assumed here. VDS-Pri Spike Vin+VRO Vin VDS-Sec Vin/N+VO t t Figure 6: Drain-Source voltage of Primary MOSFET and Secondary Rectifier Diode D. Primary side Inductance Lm At heavy load condition, the switching frequency is fixed with frequency jittering. With build-in slope compensation, HFC0400 can operate under CCM when duty cycle is larger than 0.5. Assume the ratio of primary side ripple current to peak current is KP as shown in Figure 7 (0<KP≤1, KP=1 at DCM). Smaller KP can reduce RMS current, but it needs larger inductance which may increase transformer size. For trade off consideration, KP is recommended at 0.6~0.8 for universal input range and 0.8~1 for 230Vac single input range. Figure 7: Typical primary current waveform AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION If the flyback converter is designed in CCM at minimum input, the duty cycle of converter is shown as equation (10). D= (VO + VF ) ⋅ N (VO + VF ) ⋅ N + Vin(min) (10) Ton = D ⋅ Ts (11) Turn-on time of MOSFET is given as Where Ts is the nominal switching period without considering the frequency jittering, 1 = f s = 65kHz . Ts The average, peak, ripple and valley value of primary side current can be got as follows: Pin Vin(min) Iav = Ipeak = Iav K (1 − P ) ⋅ D 2 (12) (13) Iripple = K P ⋅ Ipeak (14) Ivalley = (1 − K P ) ⋅ Ipeak (15) The primary inductance Lm can be obtained by equation (16). Lm = Vin(min) ⋅ Ton Iripples (16) E. Current Sense Resistance a) Peak current comparator circuit AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION b) Typical waveform Figure 8: Peak current comparator circuit in HFC0400 The circuit diagram of peak current mode control is shown in Figure 8. When voltage of sensing resistor plus the internal slope reaches Vpeak, the comparator outputs high level to reset R-S flip flop， DRV pin is pulled down to turn off MOSFET. The maximum current limit point of HFC0400 is Vlim it = 0.95V . The build-in slope compensation is Vslope = 25mV / μs typically. Considering the margin, take 95%*Vlimit as Vpeak at full load. The voltage of sensing resistor can be got as follow: Vsense = 95% ⋅ Vlim it − Vslope ⋅ Ton (17) So the sensing resistance is Rsense = Vsense Ipeak (18) The current sense resistor with the proper power rating should be chosen based on the power loss given Psense ⎡⎛ Ipeak + Ivalley ⎞2 1 2⎤ = ⎢⎜ ⎟ + (Ipeak − Ivalley ) ⎥ ⋅ D ⋅ Rsense 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 (19) F. Transformer Design F-1. Transformer Core Selection Firstly, a proper core for certain output power should be selected. Ferrite is usually adopted in flyback transformer. The core area product (AeAW) which is the product of core cross-sectional area and core window area for windings, is widely used for an initial estimate of core size for a specific application. A rough indication of the required area product is given by following: AE ⋅ A W ⎛ Lm ⋅ Ipeak ⋅ Ipri−rms × 10 4 ⎞ =⎜ ⎟⎟ ⎜ B ⋅K ⋅K ⋅ f max u j s ⎝ ⎠ 4/3 cm4 (20) where Ku is window utilization factor. In application, AC-DC product is required to keep safety isolation between primary and secondary side, the transformer needs enough insulation, which reduce the available area for windings. Ku is usually set 0.2~0.3 for an off-line transformer with triple insulated wire, 0.05~0.15 for the transformer with 6mm margin tape. Kj is the current-density coefficient (typically 400~450 for ferrite core). Bmax is the allowed maximum flux density which should be lower than the AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION saturation flux density of the core material within the operating temperature range, is usually presetted to (0.3T~0.4T). Ipri-rms is the RMS current of primary inductance given as follow Ipri−rms ⎡⎛ Ipeak + Ivalley ⎞ 2 1 2⎤ = ⎢⎜ + − I I ( peak valley ) ⎥ ⋅ D ⎟ 2 12 ⎢⎣⎝ ⎥⎦ ⎠ (21) F-2. Primary and Secondary Winding Turns With a given core size and Bmax, the turns can be calculated. The normal saturation specification is ET or volt-second rating. The E-T rating is the maximum voltage, E, which can be applied over a time of T seconds. (The E-T rating is identical to the product of inductance L and peak current) Equation (22) defines a minimum value of NP for the transformer primary winding to avoid the core saturation: NP = Lm ⋅ Ipeak Bmax ⋅ A E (22) Where: Lm = the primary inductance of the transformer AE= the effective cross sectional area of core Ipeak= the peak current in the primary side of the transformer, which is given in (13). Secondary turns count is a function of turn ratio N and primary turns NP: NS = NP N (23) F-3. Wire size Once all the winding turns have been determined, wire size must be properly chosen to minimize the winding conduction loss and leakage inductance. The winding loss depends on the RMS current value, the length and the cross section of wire. The wire size could be determined by the RMS current of the winding. For a flyback converter, the RMS current on secondary side is: Isec −rms ⎡⎛ Ipeak + Ivalley ⎞2 1 2⎤ ⎢ = N⋅ ⎜ ⎟ + (Ipeak − Ivalley ) ⎥ ⋅ (1 − D ) 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 (24) Then, the wire size required on primary and secondary side is got by equation (25) and equation (26) Spri = S sec = Ipri−rms J Isec −rms J (25) (26) Here J is the current density of the wire which is 500-700A/cm2 typically. Due to the skin effect and proximity effect of the conductor, the diameter of the wire selected is usually less than 2*Δd (Δd: skin effect depth): 1 (27) Δd = π ⋅ fs ⋅ μ ⋅ σ AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION where μ is the magnetic permeability of the conductor, which is usually equals to the permeability of vacuum for most conductor, i.e. 4π × 10 −7 H/m, σ is the conductivity of the wire (for copper, σ is typically 6 × 10 7 S/m at 0 ˚C, σ will be larger as temperature increases, which means the Δd will get smaller). Sometimes the size of selected wire is less than required; it needs to add parallel windings. The number of primary and secondary windings can be got as follows: npri = nsec = Spri 1 πdpri2 4 Ssec 1 πdsec 2 4 (28) (29) where dpri and dsec are the wire diameter of primary and secondary winding respectively. After the wire sizes have been determined, it is necessary to check whether the window area with selected core can accommodate the windings calculated in the previous steps. The window area required by each winding should be calculated respectively and added together, the area for interwinding insulation, spaces existing between the turns and area of margin tape (if margin tape is placed) should also be taken into consideration. The fill factor, means the winding area to the whole window area of the core, should be well below 1 due to these inter-winding insulation and spaces between turns. It is recommended that a fill factor no greater than about 30% be used. For transformers with multiple outputs this factor may need to be reduced further. Based on these considerations, the total required window area is then compared to the available window area of a selected core. If the required window area is larger than the selected one, either wire size must be reduced, or a larger core must be chosen. Of course, a reduction in wire size leads to more copper loss of the transformer. F-4. Air gap With the selected core and winding turns, the air gap of the core is given as: NP 2 lc la = μ0 ⋅ AE ⋅ − Lm μr (30) where AE is the cross sectional area of the selected core, μ0 is the permeability of vacuum which equals 4π × 10−7 H/m. Lm and NP is the primary winding inductance and turns respectively, lc is the core magnetic path length and μr is the relative magnetic permeability of the core material. For Ferrite core, μr is very large, so la can be approximately calculated as equation (31). NP2 la = μ0 ⋅ AE ⋅ Lm (31) G. Design the RCD snubber In application, a small amount of energy is stored in the leakage inductor of the transformer, which cannot be transferred to the output side in flyback converter. This amount of energy may result in a high voltage spike on the drain-source of the MOSFET when it turns off, which should be well clamped to protect the MOSFET from breakdown. AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION The RCD snubber is usually adopted to clamp the drain-source voltage as shown in Figure 9. The value of the capacitor, Csn, and resistor, Rsn, depend on the energy stored in the parasitic inductor, as the energy must be dissipated by the RC network during each cycle. Figure 10 shows the typical waveform of snubber during turn-off phase. isec Vsn Rsn Csn + Dsn isn Lk iD Coss Figure 9: RCD snubber on primary side Figure 10: Waveform of MOSFET and RCD snubber AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION When the MOSFET turns off and Vds is charged to Vin+N*(Vo+VF), the secondary diode turns on, and the current of secondary winding increases from 0. The primary current continues to flow through the snubber diode (Dsn) to Csn. The voltage stress of MOSFET is clamped to Vin+Vsn. Therefore, the voltage across Lk is Vsn-N*(Vo+VF). The slope of isn is given by equation (32). disn V − N ⋅ (Vo + VF ) = − sn dt Lk (32) Where isn is the current that flows through Dsn, Vsn is the voltage across the snubber capacitor Csn, Lk is the leakage inductance of the transformer. The time ts is obtained by equation (33). ts = Lk ⋅ Ipeak Vsn − N ⋅ (Vo + VF ) (33) Vsn is usually set as 1.5~2 times of N*(Vo+VF), the power dissipated in the snubber circuit is obtained by equation (34). Psn = Vsn Ipeak ⋅ t s 2 fs = Vsn 1 LkIpeak 2 fs 2 Vsn − N ⋅ (Vo + VF ) (34) Since the power consumed in the snubber resistor (Rsn) is Vsn2/Rsn, the resistance is obtained by: Rsn = Vsn2 Vsn 1 LkIpeak 2 f 2 Vsn − N ⋅ (Vo + VF ) s (35) The snubber resistor with the proper rated power should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained equation (36). ΔVsn = Vsn Csn ⋅ Rsn ⋅ fs (36) Generally, a 5~10% ripple voltage is reasonable. Therefore, the snubber capacitance can be calculated. H. Design the Output Filters The RMS current of the output capacitor can be obtained as: Icap−out = Isec −rms2 − Iout 2 (37) where Iout is the output current and Irms-sec is the secondary RMS current in (24). The RMS current should be smaller than the RMS current specification of the selected capacitor. The voltage ripple on the output can be estimated by: ΔVout = Iout ⋅ (Ts − Tsec on ) + ESR ⋅ (N ⋅ Ipeak − Iout ) Cout (38) where Tsecon is the conduction time of secondary diode, ESR is the equivalent series resistance of output cap. By setting a voltage ripple, the value of output capacitor is derived by the upper equation. The output capacitor can be electrolytic capacitor. If the electrolytic capacitor is used, due to its high ESR and ESL, a film capacitor or ceramic capacitor is usually paralleled to the electrolytic capacitor to AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION provide a low impendence current path for high frequency current ripple. To further reduce the output voltage ripple, a small LC filter can be inserted between the output capacitor and output terminal. I. Low-pass Filter on CS Pin Figure 11: Low-pass Filter on CS Pin A small capacitor is usually connected to CS pin to form a low-pass filter with Rseries for noise filtering at MOSFET turn-on and turn-off, as shown in Figure 11. The resistance in series to CS pin Rseries is recommended to be less than 1kΩ. The Rseries*Cf of low-pass filter on CS pin should be no larger than 1/3 of leading edge blanking for SCP (LEB2, 250ns), or else the real sense voltage is filtered so can’t touch SCP point (1.5V) to trigger SCP when short circuit at output occurs. J. Jittering Period Frequency jittering is an effective method to reduce EMI by spreading energy over a wide frequency range. The bandwidth of n order harmonic of noise is BTn = n ⋅ (2 ⋅ Δf + fjitter ) , where Δf is the amplitude of frequency jittering, fjitter is the jitter frequency. If BTn is larger than resolution bandwidth (RBW) of spectrum analyzer (200Hz for noise frequency less than 150 kHz, 9 kHz for noise frequency between 150k~30MHz), the energy of noise received by spectrum analyzer reduces. The period of frequency jittering is determined the capacitor connected to TIMER pin. A 10uA current source charges the capacitor, when the TIMER voltage reaches 3.2V, it is discharged to 2.8V with another 10uA current source, then charged and discharged repeatedly. The jittering period can be got as follow: Tjitter = 1 f jitter = 2 ⋅ CTIMER ⋅ (3.2V − 2.8V) 10μA (39) Where CTIMER is the capacitor connected to TIMER pin. In theory, the smaller fjitter, the better harmonic suppression effect. However, due to measurement bandwidth requirements, fjitter should be large compared to spectrum analyzer RBW for effective EMI reduction [2]. Also, fjitter should be less than the control loop gain crossover frequency to avoid disturbing the regulation of output voltage. As a result, fjitter is recommended between 200Hz~400Hz. K. X-cap Discharge Time Estimate When the AC voltage is unplugged, the IC turns on high voltage current source after 31~32 TIMER cycles to discharge the energy of X-cap. The first discharge duration is 16 TIMER cycles, then IC turns off current source for 16 TIMER cycles to detect whether the input is re-plugged to AC line. If AC input is still disconnected, the IC will turn on current source for 48 TIMER cycles and then re-detect for 16 AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION TIMER cycles repeatedly until the voltage on X-cap drops to Vcc. Once the reconnected AC input is detected, high voltage current source won’t turn on until Vcc drops to 5.3V then recharge Vcc for restart of system. Figure 14 shows the waveforms of discharge function. The max time of discharge occurs at high-line input and no-load condition because the energy on X-cap is only released but can’t be delivered to bulk capacitor. Figure 14: X-cap discharge function The max delay time of discharge action is Tdelay = 32 ⋅ Tjitter (40) When high voltage current source turns on, a constant supply current IHV (1.6mA minimum) flows into HV pin. On time of the current source discharging the X-cap to 37% of peak voltage can be estimated by: Tdischarge = C X ⋅ 63% ⋅ 2 ⋅ Vac(max) IHV (41) Where CX is capacitance of the X-cap, Vac(max) is RMS value of the max AC input. The first discharging section is 16*Tjitter, others are 48*Tjitter since the second. The times of section can be calculated: n= Tdischarge − 16 ⋅ Tjitter 48 ⋅ Tjitter +1 (42) Rounded n is the times of detecting section, as every section is 16*Tjitter, the detecting time is shown as follow: Tdetect = 16 ⋅ Tjitter ⋅ n (43) AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION As a result, the total discharge time can be got as equation (44). Ttotal = Tdelay + Tdischarge + Tdetect (44) The total discharge time is relative to Tjitter. For example, if CTIMER is 47nF, Tjitter=3.7ms, in order to discharge the X-cap in 1 second due to the value deviation of X-cap, the X-cap should be less than 3.3μF. Though the X-cap is discharged, high voltage may be maintained on the bulk capacitor. For safety, make sure it is released before the board is debugged. L. External OTP or OVP Circuit by TIMER Pin Latch-off (Optional) If voltage on TIMER pin gets less than 1V for 12μs, the controller enters latch-off mode. OTP or OVP also can be realized by adding external circuit shown in Figure 15 on TIMER pin. Take OVP for an example, when output loop is open, Vcc voltage rises as well as output. If the voltage on gate of MOSFET dividing Vcc by zener and resistors exceeds gate threshold VGS(th), MOSFET turns on so TIMER voltage is pulled down to latch the controller. Figure 15: External OTP or OVP circuit AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION 5. DESIGN SUMMARY • The transformer used in this design has a turn ratio of 57:9:3:9 (Np:Naux:Ns1:Ns2) with 870μH primary inductance. The transformer size selected is ER28. The winding structure is shown as Figure 18, 19 and Table 2. 2 3 2 3 1 A detailed reference design of flyback converter with HFC0400 controller is shown in Figure 16 and 17. The input voltage is 85Vac to 265Vac and the outputs are 5V/3A and 16V/1.5A. 4 • Figure 16: Schematic of HFC0400 Application for Multiple output a) Top View AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 18 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION b) Bottom View Figure 17: PCB Layout Figure 19: Winding Diagram Figure 18: Connection Diagram Table 2: Winding order Tape(T) Winding Margin Wall PRI side Terminal Start—>End Margin Wall SEC side Wire Size (φ) Turns (T) N1 2mm 3—>2 2mm 0.27mm*2 28 N6 2mm 1—>NC 2mm 0.3mm*1 20 N4 2mm 7,8—>9,10 2mm 0.33mm*12 3 N3 2mm 11,12—>7.8 2mm 0.33mm*5 6 N2 N5 2mm 2mm 5—>6 2—>1 2mm 2mm 0.27mm*1 0.27mm*2 9 29 1 1 3 1 3 1 2 AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 19 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION 6. EXPERIMENTAL VERIFICATION To verify design procedure presented in this application note and the performance, a prototype based in Figure 16 is built and tested with specified input/output condition(Input: 85Vac~265Vac; Output: 5V/3A, 16V/1.5A). The converter is designed to operate at CCM at 85Vac input and full load. Figure 20 and 21 show the current and drain-source voltage waveform of primary MOSFET. With built-in slope compensation, there is no sub-harmonic oscillation when duty is larger than 0.5. Figure 22 shows the conducted EMI of the prototype, Figure 23 to Figure 27 shows the protections of converter with HFC0400 at different fault condition. With various integrated protections, the converter is more reliable under fault conditions. Figure 28 shows the measured efficiency. From the efficiency curve, the efficiency is still high at light load condition due to decreased switching frequency. Figure 29 shows waveform of the x-cap discharge when input is plugged. Figure 30 shows the burst mode operation at no-load condition. The power consumption at standby mode is given in Table 3. Due to the x-cap discharge function and burst mode operation, the power loss at no load condition is very small, even at high line input. Figure 20: Drain Voltage and Current of MOSFET at 85VAC Input Figure 21: Drain Voltage and Current of MOSFET at 265VAC Input AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 20 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION Att 10 dB dBµV RBW 9 kHz MT 20 ms PREAMP OFF 1 MHz 120 Att 10 dB dBµV 10 MHz 110 120 RBW 9 kHz MT 20 ms PREAMP OFF 1 MHz 10 MHz 110 SGL 1 PK CLRWR 2 AV CLRWR SGL 1 PK CLRWR 100 90 TDS 2 AV CLRWR 100 90 TDS 80 80 70 70 EN55022Q EN55022Q 60 60 EN55022A 6DB EN55022A 50 50 40 40 30 30 20 20 10 6DB 10 0 0 150 kHz 30 MHz 150 kHz 30 MHz EMI, L-Wire EMI, N-Wire Figure 22: Conducted EMI Test Result (230VAC Input) CH1: VDS CH2: VCC CH3: VFB CH4: VOUT2 a) SCP Entry b) SCP Recovery Figure 23: Output Short Circuit Protection (230VAC Input, 16V Shorted) CH1: VDS CH2: VCC CH3: VFB CH4: VOUT2 a) 5V Over Load b) 16V Over Load Figure 24: Over Load Protection (230VAC Input) AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 21 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION a) OVP, No Load b) OVP, Full Load Figure 25: Output Over Voltage Protection (230VAC Input) a) OTP Entry b) OTP Recovery Figure 26: Over Temperature Protection (230VAC Input) a) Brown-in, VIN=75VAC b) Brown-out, VIN=72VAC Figure 27: Brown-out Protection AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 22 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION Efficiency 90.0 Efficiency(%) 89.0 88.0 87.0 86.0 85.0 84.0 25 50 75 100 %Load 115Vac/60Hz 230Vac/50Hz Figure 28: Efficiency of Prototype CH1: VX-CAP CH1: VX-CAP b) 265VAC input, full load a) 265VAC input, no load Figure 29: X-cap Discharge of HFC0400 CH1: VFB CH2: VDS Figure 30: Burst Mode Operation of HFC0400 (230VAC Input, no load) AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 23 AN069 – FIXED FREQUENCY FLYBACK CONTROLLER WITH ULTRA-LOW NO LOAD POWER CONSUMPTION Table 3: No Load Consumption at Different Input Vin (VAC/Hz) 5V/0A, 16V/0A Pin (mW) 5V/6mA, 16V/0A 85/60 26.35 71.92 115/60 27.59 72.72 230/50 32.40 80.70 265/50 35.26 84.83 7. REFERENCES [1]. Lloyd H. Dixon, “Magnetics Design for Switching Power Supplies,” in Unitrode Magnetics Design Handbook, 1990. [2]. F.Lin, D.Y. Chen, “Reduction of Power Supply EMI Emission by Switching Frequency Modulation,” IEEE Trans. Power Electronic., vol.9, pp 132-137, Jan 1994. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN069 Rev. 1.0 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 24