SLS SL74HCT125D

SL74HCT125
Quad 3-State Noninverting Buffers
High-Performance Silicon-Gate CMOS
The SL74HCT125 is identical in pinout to the LS/ALS125. The
SL74HCT125 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The SL74HCT125 noninverting buffers are designed to be used with
3-state memory address drivers, clock drivers, and other bus-oriented
systems. The devices have four separate output enables that are activelow.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT125N Plastic
SL74HCT125D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
PIN 14 =VCC
PIN 7 = GND
Output
A
OE
Y
H
L
H
L
L
L
X
H
Z
X = don’t care
Z = high impedance
SLS
System Logic
Semiconductor
SL74HCT125
MAXIMUM RATINGS *
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
IOUT
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, t f
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
-55
+125
°C
0
500
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HCT125
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VOUT= VCC-0.1 V
IOUT≤ 20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
Maximum Low -Level
Input Voltage
VOUT=0.1 V
IOUT ≤ 20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VIN=VIH
IOUT ≤ 20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
VIN=VIH
IOUT ≤ 6.0 mA
4.5
3.98
3.84
3.7
VIN=VIL
IOUT ≤ 20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIL
IOUT ≤ 6.0 mA
4.5
0.26
0.33
0.4
Symbol
Parameter
VIH
Minimum High-Level
Input Voltage
VIL
VOH
VOL
Guaranteed Limit
Maximum Low-Level
Output Voltage
Test Conditions
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
±0.1
±1.0
±1.0
µA
IOZ
Maximum Three-State
Leakage Current
Output in High-Impedance
State
VIN=VIL or VIH
VIN=VCC or GND
5.5
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
5.5
4.0
40
160
µA
∆ICC
Additional Quiescent
Supply Current
VIN = 2.4 V, Any One Input
VIN=VCC or GND, Other
Inputs
≥-55°C
25°C to
125°C
mA
2.9
2.4
IOUT=0µA
SLS
System Logic
Semiconductor
5.5
SL74HCT125
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input t r=t f=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25 °C to
-55°C
≤85°C
≤125°C
Unit
tPLH, t PHL
Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 3)
18
23
27
ns
tPLZ, t PHZ
Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4)
24
30
36
ns
tPZL, t PZH
Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4)
18
23
27
ns
tTLH, t THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
15
15
15
pF
CIN
COUT
Power Dissipation Capacitance (Per Buffer)
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Figure 1. Switching Waveforms
Typical @25°C,VCC=5.0 V
48
pF
Figure 2. Switching Waveforms
SLS
System Logic
Semiconductor
SL74HCT125
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
SLS
System Logic
Semiconductor