SLS SL74LV573D

SL74LV573
OCTAL D-TYPE TRANSPARENT LATCH (3-State)
By pinning SL74LV573 are compatible with SL74HC573 and
SL74HCT573 series. Input voltage levels are compatible with
stadard CMOS levels.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Voltage supply range from 1.2 to 5.5 V
• LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• Output current 8 mÀ
• Latch current: not less than150 mÀ at Ò = 125 °Ñ
• ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Outputs
OE
1
20
VCC
OE
LE
D
Q
D0
2
19
Q0
L
H
H
H
D1
3
18
Q1
L
H
L
L
D2
4
17
Q2
L
L
X
no change
D3
5
16
Q3
H
X
X
Z
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
Q7
10
11
LE
H -HIGH voltage level
L - LOW voltage level
X - don’t care
Z - High impedance state
SLS
ORDERING INFORMATION
SL74LV573N Plastic DIP
SL74LV573D SOIC
TA = -40° to 125° C
for all packages
System Logic
Semiconductor
GND
SL74LV573
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Unit
-0.5 to +7.0
V
Conditions
Vcc
Supply voltage
Iik,
Input diode current
±20
mA
VI<-0.5 V or VI>Vcc>+0.5 V
Iok
Output diode current
±50
mA
V0<-0.5 V or VI>Vcc>+0.5 V
Output current bus drivers
±35
mA
-0.5 V<Vo<Vcc+0.5 V
DC Vcc or GND current for types
bus driver outputs
±70
mA
IGND
GND current
±50
mÀ
Tstg
Storage temperature range
-65 to +150
î
Io
Icc
PD
Power dissipation per package:
DIP
SO
750
500
Ñ
mW
Notes:
Power dissipation value decreases for:
DIP - 12 mW°C the range from 70 to 125°Ñ
SO - 8 mW°C the range from 70 to 125°Ñ
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
1.0
5.5
V
V
Vcc
Supply voltage
VI
Input voltage
0
Vcc
Vî
Output voltage
0
Vcc
T
Operating temperature range
tr,tf
Input rise and fall times
-40
+125
500
200
100
50
Conditions
V
o
C
ns/V
Vcc= 1.0
Vcc= 2.0
Vcc= 2.7
Vcc= 3.6
÷ 2.0 V
÷ 2.7 V
÷ 3.6 V
÷ 5.5 V
Note - The IC function down to Vññ = 1.0 V (input levels - VIL=0 V, VIH=Vcc); DC characterisics are
guaranteed at Vcc=1.2 ÷ 5.5 V.
SLS
System Logic
Semiconductor
SL74LV573
DC CHARACTERISTICS
Sym
bol
Conditions
Parameter
Vcñ
VI
Limits
+85 îÑ
-40 to +25°C
+125 îÑ
Unit
(V)
Min
Max
Min
Max
Min
Max
VIH
HIGH level
input voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
0.9
1.4
2.0
0.7 Vcc
-
0.9
1.4
2.0
0.7 Vcc
-
0.9
1.4
2.0
0.7 Vcc
--
V
VIL
LOW level
output
voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
-
0.3
0.6
0.8
0.3 Vcc
-
0.3
0.6
0.8
0.3 Vcc
-
0.3
0.6
0.8
0.3 Vcc
V
VOH HIGH level
output
voltage
1.2
2.0
2.7
3.6
5.5
VIH IO =-100 µÀ
or
VIL
1.05
1.85
2.55
3.45
5.35
-
1.0
1.8
2.5
3.4
5.3
-
1.0
1.8
2.5
3.4
5.3
-
V
VOH HIGH level
output
voltage; BUS
driver outputs
3.0
4.5
VIH IO =-8 mA
or IO =-16 mA
VIL
2.48
3.70
-
2.40
3.60
-
2.20
3.50
-
V
VOL LOW level
output
voltage
1.2
2.0
2.7
3.6
5.5
VIH IO =100µÀ
or
VIL
-
0.15
0.15
0.15
0.15
0.15
-
0.2
0.2
0.2
0.2
0.2
-
0.2
0.2
0.2
0.2
0.2
V
VOL LOW level
voltage; BUS
driver outputs
3.0
4.5
VIH IO =8 mA
or IO =16 mA
VIL
-
0.33
0.40
-
0.40
0.55
-
0.50
0.65
V
Input leakage
current
5.5
Vññ
or
GND
-
±1.0
±1.0
-
±1.0
µÀ
IOZ
OFF-state
current
5.5
VIH
or
VIL
-
±0.5
±5.0
-
±10.0
µÀ
Icc
Supply
current
5.5
Vññ Io = 0
or
GND
8.0
80
160
µÀ
Icc
Additional
supply
current per
input
0.2
0.5
0.85
mA
II
SLS
2.7 äî 3.6 VI = Vcc-0.6V
System Logic
Semiconductor
-
-
SL74LV573
AC CHARACTERISICS (CL=50 pF, RL=1 KΩ, tLH = tHL = 2.5 ns)
Sym
bol
Conditions
Parameter
Vcc
Limits
-40 to +25°C
+85°C
+125°C
Min
Max
Min
Max
Min
Max
Unit
tPHL/PLH
Propagation
delay Dn to
Qn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
150
30
23
18
15
-
160
39
29
23
19
-
170
49
36
29
24
ns
tPHL/PLH
Propagation
delay LE to
Qn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
160
34
28
20
17
-
180
43
31
25
21
-
190
53
34
31
26
ns
tPZH/PZL
3-state
output enable
time OE to
Qn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
140
28
22
17
14
-
160
37
28
22
18
-
170
48
35
28
23
ns
tPHZ/PLZ
3-state
outpiut
disable time
OE to Qn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
160
31
23
20
17
-
160
39
29
24
20
-
170
48
36
29
24
ns
tW
LE pulse
width HIGH
1.2
2.0
2.7
3.0
4.5
100
29
21
17
15
-
125
34
25
20
18
-
150
41
30
24
21
-
ns
tsu
Setup time
Dn to LE
1.2
2.0
2.7
3.0
4.5
50
15
11
8
6
-
75
17
13
10
8
-
100
20
15
12
10
-
ns
th
Hold time Dn
to LE
1.2
2.0
2.7
3.0
4.5
40
8
8
8
8
-
40
8
8
8
8
-
40
8
8
8
8
-
ns
CI
Input
capacitance
5.0
Ò=+25 îÑ
7.0
-
ns
CPD
Power
dissipation
capacitance
per package
5.5
Ò=+25 îÑ
VI = Vcc or
GND
52
-
ns
SLS
System Logic
Semiconductor
SL74LV573
1.9 mm
18
17
16 15
19
14
13
On-chip marking
1.51 mm
20
12
11
74LV573/574
1
10
9
2
3
4
5
6
7
8
Drawing of the chip
Pads allocation Table
Pad
number
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
SLS
coordinates (counted from lower left corner), mm
Y
X
0.128
0.545
0.128
0.229
0.330
0.120
0.576
0.120
0.738
0.120
1.054
0.120
1.216
0.120
1.466
0.120
1.682
0.314
1.682
0.533
1.682
0.839
1.682
1.108
1.422
1.274
1.149
1.274
0.971
1.274
0.811
1.274
0.633
1.274
System Logic
Semiconductor
Pad size, mm
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
SL74LV573
18
19
20
0.360
0.128
0.128
1.274
1.108
0.854
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
SLS
System Logic
Semiconductor