SLS SL74LV245D

SL74LV245
OCTAL BUS TRANSCEIVER (3-State)
By pinning SL74LV245 are compatible with SL74HC245 and SL74HCT245 series. Input voltage levels
are compatible with standard CMOS levels.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
N SUFFIX
• Supply voltage range: 2.0 to 3.2 V
PLASTIC
• Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• Output current 8 mÀ
• Latch current value: not less 150 mÀ at Ò = 125 °Ñ
20
• ESD acceptable values: not less than 2000 V as per HBM and
1
D SUFFIX
not less 200 V as per ÌÌ
SOIC
•
20
1
ORDERING INFORMATION
SL74LV245N Plastic DIP
SL74LV245D SOIC
TA = -40° to 125° C
for all packages
BLOCK DIAGRAM
DIR
01
OE
02
03
04
05
06
07
08
09
A0
DIR
B0
A1
B1
A2
18
17
01
20
VCC
A0 02
19
OE
A1 03
18
B0
A2 04
17
B1
16
B2
A4 06
15
B3
A5 07
14
B4
A6 08
13
B5
A7 09
12
B6
GND 10
11
B7
A3 05
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
Pin 20=VCC
Pin 10 = GND
SLS
PIN ASSIGNMENT
19
System Logic
Semiconductor
16
15
14
245
13
FUNCTION TABLE
12
11
Inputs
Inputs/Outputs
OE
DIR
À
Â
L
L
A=B
input
L
H
input
B=A
H
X
Z
Z
SL74LV245
ABSOLUTE MAXIMUM RATINGS*
Symbol
VCC
Parameter
Supply voltage
Rating
Unit
-0.5 to +5.0
V
1
Input diode current
±20
mÀ
2
IOK *
Output diode current
±50
mÀ
IO *3
Output source or sink current
±35
mÀ
ICC
VCC current
±70
mÀ
IGND
GND current
±70
mÀ
PD
Power dissipation per package:
Plastic DIP *4
SOIC *4
750
500
IIK *
Tstg
mW
Storage temperature range
°C
-65 to +150
*
In absolute maximum ratings modes functioning is not guaranteed. Vpon lifting the absolute
maximum ratings functioning is guaranteed at the recommended operating conditions.
*1 Provided VI < -0.5 V or VI > VCC + 0.5 V.
*2 Provided VO < -0.5 V or VO > VCC + 0.5 V.
*3 Provided -0.5 V < VO < VCC + 0.5 V.
*4 When operating in the temperature range of 70°Ñ to 125°C power dissipation value decreases:
- for Plastic DIP by 12 mW/°C
- for SOIC by 8 mW/°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
1.2
3.6
V
VCC
Supply voltage
VIN
Input voltage
0
VCC
V
Output voltage
0
VCC
V
-40
125
°C
0
1000
700
500
400
ns
VOUT
TA
tLH, tHL
Operating ambient temperature range. For all
package types
Input rise and fall times
VCC =1.2 V
VCC =2.0 V
VCC =3.0 V
VCC =3.6 V
SLS
System Logic
Semiconductor
SL74LV245
DC CHARACTERISTICS
Symbol
Parameter
Test
VCC,
conditions
V
25°C
-40°C to
85°C
125°C
Unit
min
max
min
max
min
max
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
0.9
1.4
2.1
2.5
-
0.9
1.4
2.1
2.5
-
V
VIH
HIGH level input
voltage
VIL
LOW level output VO =0.1 V
voltage
1.2
2.0
3.0
3.6
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
V
VOH
HIGH level output VI = VIH or VIL
voltage
IO = -50 µÀ
1.2
2.0
3.0
3.6
1.1
1.92
2.92
3.52
-
1.0
1.9
2.9
3.5
-
1.0
1.9
2.9
3.5
-
V
VI = VIH or VIL
IO = -8 mÀ
3.0
2.48
-
2.34
-
2.20
-
V
LOW level output VI = VIH or VIL
voltage
IO = 50 µÀ
1.2
2.0
3.0
3.6
-
0.09
0.09
0.09
0.09
-
0.1
0.1
0.1
0.09
-
0.1
0.1
0.1
0.09
V
VI = VIH or VIL
IO = 8 mÀ
3.0
-
0.33
-
0.4
-
0.5
V
VI = VCC or 0 V
3.6
-
±0.1
-
±1.0
-
±1.0
µÀ
IOZ
OFF-state current 3-state outputs
VI = VIL or VIH
VO =VCC or 0 V
3.6
-
±0.5
-
±5
-
±10
µÀ
ICC
Supply current
3.6
-
8.0
-
80
-
160
µÀ
SLS
System Logic
Semiconductor
VOL
II
Input current
VO = VCC-0.1 V
Limits
VI =VCC or 0 V
IO = 0 µÀ
SL74LV245
AC CHARACTERISTICS(CL=50 pF, tLH = tHL = 6.0 ns)
Symbol
Parameter
Test
VCC,
conditions
V
Limits
25°C
-40°C to
85°C
min max min
125°C
max
min
max
Unit
tPHL, tPLH
Propagation
from An to
delay
Bn,
from Bn to An
Figure 1
1.2
2.0
3.0
-
100
23
14
-
125
28
18
-
140
34
21
ns
tPHZ tPLZ
3-state output
from OE, DIR enable time
to An, Bn
Figure 2
1.2
2.0
3.0
-
120
30
20
-
140
37
24
-
160
43
28
ns
tPZH tPZL
from OE to
An, Bn
3-state output
disable time
Figure 2
1.2
2.0
3.0
-
120
28
17
-
140
35
21
-
160
43
26
tTHL, tTLH
HIGH-to-LOW
and LOW-to
HIGH transition
time
Figure 1
1.2
2.0
3.0
-
60
15
10
-
75
20
13
-
90
24
15
CI
Input
capacitance
For inputs
01,19
3.0
-
7
-
-
-
-
CI/Î
Input
capacitance
For inputs/
outputs
02-09,
11-18
3.0
-
20
-
-
-
-
CPD
Power
VI = 0 V or
dissipation
VCC
capacitance (per
one channel)
3.0
-
50
-
-
-
-
SLS
pF
System Logic
Semiconductor
SL74LV245
tLH
tHL
0.9
0.9
An, Bn
V1
VCC
V1
0.1
GND
0.1
tPLH
tPHL
0.9
0.9
V1
Bn, An
V1
0.1
tTHL
tTLH
0.1
0V
B
V1 = 0.5V CC
Figure 1 -Time diagram of AC parameters control tPLH, tPHL.
OE, DIR
tHL
tLH
0.9
0.9
V1
VCC
V1
0.1
tPZH
V1
An, Bn
GND
0.1
0.9
VOH
tPHZ
0V
B
tPLZ
An, Bn
VCC
V1
tPZL
0.1
VOL
V1 = 0.5V CC
Figure 2 - Time diagram of tPLZ, tPHZ, tPZL, tPZH. AC parameters control
SLS
System Logic
Semiconductor
SL74LV245
2.3mm
18
17
16
15
14
13
19
12
11
1.99 mm
On-chip marking
74LV245
10
1
9
2
3
4
5
6
7
8
Drawing of the chip
Pads allocation Table
Pad
number
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
coordinates (counted from lower left corner), mm
X
Y
0.140
0.573
0.140
0.315
0.370
0.140
0.790
0.140
1.000
0.140
1.200
0.140
1.417
0.140
1.833
0.140
2.060
0.354
2.060
0.760
2.060
1.340
2.060
1.520
1.833
1.750
1.415
1.750
1.000
1.750
0.790
1.750
0.580
1.750
0.370
1.750
Pad size, mm
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
SLS
System Logic
Semiconductor
SL74LV245
19
20
SLS
0.140
0.140
System Logic
Semiconductor
1.544
1.375
0.108 x 0.108
0.108 x 0.108