SLS SL74LV138D

SL74LV138
3-TO-8 DECODER/DEMULTIPLEXER
By pinning SL74LV138 are compatible with SL74HC138 and
SL74HCT138 series. Input voltage levels are compatible with
standard CMOS ones.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Supply voltage range is from 1.2 to 5.5 V
• Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• Output current 6 mÀ
• Latch current is not less than 150 mÀ at Ò = 125 °Ñ
• ESD acceptable values: than 2000 V as per HBM, and not less
than 200 V as per MM
ORDERING INFORMATION
SL74LV138N Plastic DIP
SL74LV138D SOIC
TA = -40° to 125° C
for all packages
BLOCK DIAGRAM
Y0
PIN ASSIGNMENT
Y1
A0
1
16
VCC
A1
2
15
Q0
A2
3
14
Q1
CS2
4
13
Q2
Cs3
5
12
Q3
CS1
6
11
Q4
Y7
7
10
Q5
GND
8
9
Q6
Q5
H
H
H
Q6
H
H
H
Q7
H
H
H
Y2
Y3
A0
Y4
A1
Y5
A2
Y6
CS3
Y7
CS2
CS1
FUNCTION TABLE
CS1
X
X
L
SLS
System Logic
Semiconductor
INPUTS
CS2 CS3 A2
X
H
X
H
X
X
X
X
X
A1
X
X
X
A0
X
X
X
Q0
H
H
H
Q1
H
H
H
Q2
H
H
H
OUTPUTS
Q3 Q4
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
SL74LV138
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
Parameter
Supply voltage
Rating
Unit
-0.5 to +7.0
V
Conditions
Iik
Input diode current
±20
mA
VI<-0.5 V orV I>Vcc>+0.5 V
Iok
Output diode current
±50
mA
V0<-0.5 V or VI>Vcc>+0.5 V
Output current standard output
±25
mÀ
-0.5 V<Vo<Vcc+0.5 V
Icc
DC Vcc, standard output
±50
mÀ
IGND
GND current
±50
mÀ
Tstg
Starage temperature range
Io
PD
-65 to +150
Power dissipation per package:
DIP
SO
750
500
î
Ñ
mW
Notes:
Power dissipation value decreases for:
DIP - 12 mW°C in the range from 70 to 125°Ñ
SO - 8 mW°C in the range from 70 to 125°Ñ
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Parameter
Supply voltage
Min
Max
Unit
1.2
5.5
V
V
VI
Input voltage
0
Vcc
Vî
Output voltage
0
Vcc
T
tr,tf
Ambient temperature range
Input rise and fall times
-40
+125
500
200
100
50
Conditions
V
o
C
ns/V
Vcc= 1.0
Vcc= 2.0
Vcc= 2.7
Vcc= 3.6
SLS
÷ 2.0 V
÷ 2.7 V
÷ 3.6 V
÷ 5.5 V
System Logic
Semiconductor
SL74LV138
DC CHARACTERISTICS
Sym
bol
Conditions
Parameter
Vcñ
VI
Limits
+85 îÑ
-40 to +25°C
+125 îÑ
Unit
(V)
Min
Max
Min
Max
Min
Max
VIH
HIGH level
input voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
0.9
1.4
2.0
0.7 Vcc
-
0.9
1.4
2.0
0.7 Vcc
-
0.9
1.4
2.0
0.7 Vcc
--
V
VIL
LOW level
output
voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
-
0.3
0.6
0.8
0.3 Vcc
-
0.3
0.6
0.8
0.3 Vcc
-
0.3
0.6
0.8
0.3 Vcc
V
VOH HIGH level
output
voltage
1.2
2.0
2.7
3.6
5.5
VIH IO =-100 µÀ
or
VIL
1.05
1.85
2.55
3.45
5.35
-
1.0
1.8
2.5
3.4
5.3
-
1.0
1.8
2.5
3.4
5.3
-
V
VOH HIGH level
output
voltage;
standard
outputs
3.0
4.5
VIH IO =-6 mA
or IO =-12 mA
VIL
2.48
3.70
-
2.40
3.60
-
2.20
3.50
-
V
VOL LOW level
output
voltage
1.2
2.0
2.7
3.6
5.5
VIH IO =100µÀ
or
VIL
-
0.15
0.15
0.15
0.15
0.15
-
0.2
0.2
0.2
0.2
0.2
-
0.2
0.2
0.2
0.2
0.2
V
VOL LOW level
output
voltage;
standard
outputs
3.0
4.5
VIH IO =6 mA
or IO =12 mA
VIL
-
0.33
0.40
-
0.40
0.55
-
0.50
0.65
V
Input leakage
current
5.5
Vññ
or
GND
-
±1.0
±1.0
-
±1.0
µÀ
Icc
Supply
current
5.5
Vññ Io = 0
or
GND
8.0
80
160
µÀ
Icc
Additional
supply
current per
input
0.2
0.5
0.85
mA
II
SLS
2.7 äî 3.6 VI = Vcc-0.6V
System Logic
Semiconductor
-
-
SL74LV138
AC CHARACTERISICS (CL=50 pF, RL=1 KΩ, tLH = tHL = 2.5 ns
Sym
bol
Conditions
Parameter
Vcc
Limits
-40 to +25°C
+85°C
+125°C
Min
Max
Min
Max
Min
Max
Unit
tPHL, tPLH Propagation
from An to delay
Yn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
150
33
23
19
14
-
150
36
26
21
16
-
150
44
33
26
20
ns
tPHL, tPLH Propagation
from CS to delay
Yn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
170
35
26
21
17
-
170
39
29
23
19
-
170
49
36
29
24
ns
5.0
Ò=+25 îÑ
7.0
-
ns
Ò=+25 îÑ
VI = Vcc or
GND
134
-
ns
CI
Input
capacitance
CPD
Power
dissipation
capacitance
per package
SLS
System Logic
Semiconductor
SL74LV138
Drawing of the chip
1.4 mm
15
13
14
12
11
10
1.33 m m
On-chip marking
16
74LV138
9
8
1
7
2
3
4
5
6
Pads allocation Table
Pad
number
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
SLS
coordinates (counted from lower left corner), mm
X
Y
0.1415
0.6270
0.1415
0.3880
1.1375
0.1515
0.4535
0.1190
0.6245
0.1190
0.7800
0.1190
0.9520
0.1180
1.2685
0.1185
1.2480
0.2960
1.2650
0.5160
1.2650
0.8430
1.2425
1.0820
1.2465
1.3165
0.9520
1.3120
0.7800
1.3110
0.6245
1.3110
System Logic
Semiconductor
Pad size, mm
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100