SL74LV374 OCTAL D-TIME FLIP-FLOP; POSITIVE EDGETRIGGER (3-StatE) SL74LV374 are compatible by pinning with SL74HC374 and SL74HCT374 series. Input voltage levels are compatible with standard CMOS levels. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS. • Supply voltage range from 2.0 to 3.2 V • LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ • Output current 8 mÀ • Latch current value not less than 150 mÀ at Ò = 125 °Ñ • ESD acceptable values: not less than 2000 V as per HBM, and not less than 200 V as per MM ORDERING INFORMATION SL74LV374N Plastic DIP SL74LV374D SOIC TA = -40° to 125° C for all packages BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CP OE 03 02 04 05 07 06 08 09 13 12 14 15 17 16 18 19 Q0 PIN ASSIGNMENT Q1 OE 20 Q0 02 19 Q7 D0 03 18 D7 D1 04 17 D6 Q5 Q1 05 16 Q6 Q6 Q2 06 15 Q5 D2 07 14 D5 D3 08 13 D4 Q3 09 12 Q4 GND 10 11 Q3 Q4 Q7 11 01 Pin 20=VCC Pin 10 = GND 374 OE L L L H System Logic Semiconductor CP FUNCTION TABLE Inputs SLS VCC 01 Q2 CP L, H, X Output Dn H L X X Qn H L no change Z SL74LV374 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter VCC Supply voltage IIK *1 Rating Unit -0.5 to +5.0 V Input diode current ±20 mÀ 2 Output diode current ±50 mÀ 3 IO * Output source or sink current ±35 mÀ ICC Bus driver outputs ±70 mÀ IGND Ground current ±70 mÀ PD Power dissipation per package, Plastic DIP *4 SOIC *4 750 500 IOK * Tstg mW Storage temperature range °C -65 to +150 * In absolute maximum ratings modes functioning is not guaranteed. Upon lifting the absolute maximum ratings functioning is guaranteed at the recommended operating conditions. *1 Provide VI < -0.5 V or VI > VCC + 0.5 V. *2 Provide VO < -0.5 V or VO > VCC + 0.5 V. *3 Provide -0.5 V < VO < VCC + 0.5 V. *4 When operating in the temperature range of 70°C to 125°C power dissipation value decreases - for Plastic DIP by 12 mW/°C - for SOIC by 8 mW/°C RECOMMENDED OPERATING MODES Symbol Parameter Min Max Unit 1.2 3.6 V VCC Supply voltage VIN Input voltage 0 VCC V Output voltage 0 VCC V -40 125 °C 0 1000 700 500 400 ns VOUT TA tLH, tHL Operating ambient temperature range. For all types packages Input rise and fall times VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V SLS System Logic Semiconductor SL74LV374 DC CHARACTERISTICS Symbol Parameter Test VCC, coditions V Limits 25°C -40°C to 85°C 125°C Unit min max min max min max VIH HIGH level input VO = VCC-0.1 V voltage 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - V VIL LOW level input VO =0.1 V voltage 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V VOH HIGH level output voltage VI = VIH or VIL IO = -50 µÀ 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 - 1.0 1.9 2.9 3.5 - 1.0 1.9 2.9 3.5 - V VI = VIH or VIL IO = -8 mÀ 3.0 2.48 - 2.34 - 2.20 - V VI = VIH or VIL IO = 50 µÀ 1.2 2.0 3.0 3.6 - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.1 - 0.1 0.1 0.1 0.1 V VI = VIH or VIL IO = 8 mÀ 3.0 - 0.33 - 0.4 - 0.5 V VOL LOW level output voltage II Input leakage current VI = VCC èëè 0V 3.6 - ±0.1 - ±1.0 - ±1.0 µÀ IOZ Output OFFstate current 3-state outputs VI = VIL or VIH VO =VCC or 0 V 3.6 - ±0.5 - ±5 - ±10 µÀ ICC Suply current VI =VCC or 0 V IO = 0 µÀ 3.6 - 8.0 - 80 - 160 µÀ SLS System Logic Semiconductor SL74LV374 AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns) Symbol Parameter Test VCC, conditions V Limits 25°C -40°C to 85°C 125°C Unit min max min max min max tPHL, tPLH Propagation from CP to Qn delay Figure 1 1.2 2.0 3.0 - 180 45 27 - 230 56 34 - 270 68 41 tPHZ tPLZ Propagation from OE to Qn delay Figure 3 1.2 2.0 3.0 - 160 38 25 - 200 57 36 - 240 68 43 tPZH tPZL Propagation from OE to Qn delay Figure 3 1.2 2.0 3.0 - 160 38 23 - 200 48 29 - 240 58 35 HIGH-to-LOW and LOW-toHIGH transition time Figure 1 1.2 2.0 3.0 - 75 16 10 - 100 20 13 - 120 24 15 tW Clock pulse width HIGH or LOW Figure 1 1.2 2.0 3.0 250 18 11 - 350 23 14 - 540 28 17 - tSU Set-up time Dn to CP Figure 2 1.2 2.0 3.0 45 13 8 - 50 17 10 - 100 20 12 - tH Hold time Dn to CP Figure 2 1.2 2.0 3.0 25 5 5 - 25 5 5 - 25 5 5 - fc CP naximum Figure 1 pulse frequency 2.0 3.0 - 27 46 - 22 37 - 18 31 MHz CI Input capacitance 3.0 - 7 - - - - pF Power VI = 0 V or VCC dissipation capacitance (per flip-flop) 3.0 - 34 - - - - tTHL, tTLH CPD SLS ns System Logic Semiconductor SL74LV374 tLH VCC 0.9 CP V1 V1 V1 tW 0.1 GND 1/fc tPHL tPLH 0.9 0.9 V1 Qn V1 0.1 tTHL tTLH 0.1 0 VB V1 = 0.5V CC Figure 1- Time diagram VCC V1 Dn V1 V1 V1 GND tSU tH tSU tH VCC CP V1 V1 GND V1 = 0.5V CC Figure 2 - Time diagram SLS System Logic Semiconductor SL74LV374 tLH tHL 0.9 OE VCC 0.9 V1 V1 0.1 GND 0.1 tPZH V1 Qn VOH 0.9 tPHZ 0V B VCC tPLZ Qn V1 tPZL 0.1 VOL V1 = 0.5V CC Figure 3 - Time diagram SLS System Logic Semiconductor SL74LV374 Drawing of the chip 1.66 mm 18 17 16 15 14 19 12 20 1.68 mm 13 11 74LV373/374 1 2 3 10 On-chip marking 4 5 6 9 7 8 Pads allocation Table Pad number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 SLS coordinates (counted from lower left corner), mm X Y 0.142 0.628 0.142 0.377 0.142 0.125 0.498 0.125 0.693 0.125 0.871 0.125 1.095 0.125 1.423 0.130 1.423 0.329 1.423 0.587 1.423 0.949 1.423 1.198 1.423 1.447 1.085 1.447 0.868 1.447 0.696 1.447 0.461 1.447 0.142 1.447 0.142 1.245 0.142 0.997 System Logic Semiconductor Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 SL74LV374 SLS System Logic Semiconductor