SONIX SN8P2501A

SN8P2501A
8-Bit Micro-Controller
SN8P2501A
USER’S MANUAL
Preliminary Specification Version 0.2
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
AMENDENT HISTORY
Version
Date
Description
VER 0.1
Jan. 2004
Preliminary Version 0.1 first issue
VER 0.2
Jan. 2004
Preliminary Version 0.2. Add SSOP 16 pin package information.
SONiX TECHNOLOGY CO., LTD
Page 1
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
Table of Content
AMENDENT HISTORY ................................................................................................................. 1
1
1.1
1.2
1.3
1.4
2
PRODUCT OVERVIEW ..................................................................................................... 6
SYSTEM BLOCK DIAGRAM.............................................................................................. 7
PIN ASSIGNMENT............................................................................................................. 8
PIN DESCRIPTIONS ......................................................................................................... 8
PIN CIRCUIT DIAGRAMS.................................................................................................. 9
CENTRAL PROCESSOR UNIT (CPU) ............................................................................ 10
2.1
MEMORY MAP ................................................................................................................ 10
2.1.1
PROGRAM MEMORY (ROM)................................................................................... 10
2.1.2
DATA MEMORY (RAM) ............................................................................................ 17
2.1.3
CODE OPTION TABLE............................................................................................. 18
2.1.4
SYSTEM REGISTER ................................................................................................ 19
2.2
ACCUMULATOR.............................................................................................................. 22
2.3
PROGRAM FLAG ............................................................................................................ 23
2.3.1
RESET FLAG............................................................................................................ 23
2.3.2
CARRY FLAG ........................................................................................................... 23
2.3.3
DECIMAL CARRY FLAG .......................................................................................... 23
2.3.4
ZERO FLAG.............................................................................................................. 23
2.4
PROGRAM COUNTER .................................................................................................... 24
2.4.1
ONE ADDRESS SKIPPING ...................................................................................... 24
2.4.2
MULTI-ADDRESS JUMPING.................................................................................... 25
2.5
ADDRESSING MODE...................................................................................................... 26
2.5.1
IMMEDIATE ADDRESSING MODE.......................................................................... 26
2.5.2 ........................................................................................................................................ 26
2.5.3
DIRECTLY ADDRESSING MODE ............................................................................ 26
2.5.4 ........................................................................................................................................ 26
2.5.5
INDIRECTLY ADDRESSING MODE ........................................................................ 26
2.6
STACK OPERATIONS..................................................................................................... 27
2.6.1
OVERVIEW............................................................................................................... 27
2.6.2
STACK REGISTERS ................................................................................................ 28
2.6.3
STACK OPERATION EXAMPLE .............................................................................. 29
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
3
3.1
3.2
3.3
4
RESET ............................................................................................................................. 30
OVERVIEW...................................................................................................................... 30
EXTERNAL RESET DESCRIPTION ................................................................................ 31
LOW VOLTAGE DETECTOR (LVD) DESCRIPTION....................................................... 32
OSCILLATOR AND SYSTEM CLOCK............................................................................ 33
4.1
OVERVIEW...................................................................................................................... 33
4.2
CLOCK BLOCK DIAGRAM .............................................................................................. 33
4.3
OSCM REGISTER DESCRIPTION.................................................................................. 34
4.4
EXTERNAL SYSTEM OSCILLATOR CIRCUITS ............................................................. 35
4.4.1
OSCILLATOR FREQUENCY MEASUREMENT ....................................................... 36
4.4.2
INTERNAL LOW-SPEED RC OSCILLATOR ............................................................ 37
5
SYSTEM OPERATION MODE ........................................................................................ 38
5.1
OVERVIEW...................................................................................................................... 38
5.2
NORMAL MODE .............................................................................................................. 38
5.3
SLOW MODE ................................................................................................................... 38
5.4
GREEN MODE................................................................................................................. 38
5.5
POWER DOWN MODE.................................................................................................... 38
5.6
SYSTEM MODE CONTROL ............................................................................................ 39
5.6.1
SYSTEM MODE SWITCHING .................................................................................. 40
5.7
WAKEUP.......................................................................................................................... 42
5.7.1
OVERVIEW............................................................................................................... 42
5.7.2
5.7.3
6
6.1
6.2
6.3
6.4
WAKEUP TIME ......................................................................................................... 42
P1W WAKEUP CONTROL REGISTER .................................................................... 42
INTERRUPT..................................................................................................................... 43
OVERVIEW...................................................................................................................... 43
INTEN INTERRUPT ENABLE REGISTER....................................................................... 43
INTRQ INTERRUPT REQUEST REGISTER ................................................................... 44
INTERRUPT OPERATION DESCRIPTION ..................................................................... 44
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
7
7.1
7.2
7.3
7.4
8
GIE GLOBAL INTERRUPT OPERATION ................................................................. 44
INT0 (P0.0) INTERRUPT OPERATION .................................................................... 45
T0 INTERRUPT OPERATION .................................................................................. 46
TC0 INTERRUPT OPERATION................................................................................ 47
MULTI-INTERRUPT OPERATION............................................................................ 48
I/O PORT ......................................................................................................................... 49
I/O PORT MODE.............................................................................................................. 49
I/O PULL UP REGISTER ................................................................................................. 50
I/O OPEN-DRAIN REGISTER.......................................................................................... 50
I/O PORT DATA REGISTER............................................................................................ 51
TIMERS............................................................................................................................ 52
8.1
WATCHDOG TIMER........................................................................................................ 52
8.2
TIMER 0 (T0) ................................................................................................................... 53
8.2.1
OVERVIEW............................................................................................................... 53
8.2.2
T0M MODE REGISTER............................................................................................ 53
8.2.3
T0C COUNTING REGISTER .................................................................................... 54
8.3
TIMER/COUNTER 0 (TC0) .............................................................................................. 55
8.3.1
OVERVIEW............................................................................................................... 55
8.3.2
TC0M MODE REGISTER ......................................................................................... 56
8.3.3
TC0C COUNTING REGISTER ................................................................................. 57
8.4
BUZZER OUTPUT ........................................................................................................... 58
8.4.1
TC0OUT FREQUENCY TABLE ................................................................................ 59
8.5
PWM FUNCTION DESCRIPTION.................................................................................... 61
8.5.1
OVERVIEW............................................................................................................... 61
8.5.2
9
10
PWM PROGRAM DESCRIPTION ............................................................................ 62
INSTRUCTION SET TABLE ............................................................................................ 63
10.1
ELECTRICAL CHARACTERISTIC........................................................................... 64
ABSOLUTE MAXIMUM RATING ..................................................................................... 64
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
10.2
ELECTRICAL CHARACTERISTIC................................................................................... 64
11
11.1
11.2
11.3
PACKAGE INFORMATION ...................................................................................... 65
P-DIP 14 PIN.................................................................................................................... 65
SOP 14 PIN...................................................................................................................... 66
SSOP 16 PIN ................................................................................................................... 67
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
1
PRODUCT OVERVIEW
FEATURES
♦
Memory configuration
OTP ROM size: 1K * 16 bits.
RAM size: 48 * 8 bits.
♦
Four levels stack buffer.
♦
I/O pin configuration
Input only: P1.1.
Bi-directional: P0, P1, P2, P5.
Wakeup: P0, P1.
Pull-up resisters: P0, P1, P2, P5.
External interrupt: P0.
One pin with open-drain: P1.0.
♦
3 interrupt sources
Two internal interrupts: T0, TC0.
One external interrupts: INT0.
♦
Powerful instructions
One clock per machine cycle
Most of instructions are one cycle only.
All ROM area JMP instruction.
All ROM area lookup table function (MOVC)
♦
♦
♦
♦
♦
One channel PWM output. (PWM0)
One channel Buzzer output. (BZ0)
Two 8-bit timer counters. (T0, TC0).
One RTC timer. (T0)
On chip watchdog timer.
♦
Three system clocks
External high clock: RC type up to 10 MHz
External high clock: Crystal type up to 16 MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V)
Internal high clock: 16MHz RC type.
♦
Four operating modes
Normal mode: Both high and low clock active
Slow mode: Low clock only
Sleep mode: Both high and low clock stop
Green mode: Periodical wakeup by T0 Timer
♦
Package (Chip form support)
PDIP 14 pins
SOP 14 pins
SSOP 16 pins
FEATURES TABLE
Timer
CHIP
ROM RAM Stack
RTC I/O
Green PWM Wakeup
Package
Mode Buzzer Pin No.
5
DIP14/SOP14/SSOP16
V
V
T0
TC0
V
V
V
12
-
14
V
-
6
DIP18/SOP18/SSOP20
V
-
15
V
V
7
DIP18/SOP18/SSOP20
SN8P2501A 1K*16
SN8P1602B 1K*16
48
4
48
4
V
-
SN8P2602A 1K*16
48
4
V
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
1.1 SYSTEM BLOCK DIAGRAM
SN8P2501A
PC
R
O
M
IR
FLAGS
H-OSC
Internal
Low
RC
Internal
High
RC
TIMING GENERATOR
ALU
RAM
ACC
POR
Watch
Dog
PWM
PWM & BUZZER
SYSTEM REGISTER
INTERRUPT
CONTROL
TIMER & COUNTER
PORT 0
PORT 1
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PORT 5
PORT 2
Page 7
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
1.2 PIN ASSIGNMENT
SN8P2501AP (P-DIP 14 pins)
SN8P2501AS (SOP 14 pins)
SN8P2501AX (SSOP 16 pins)
P2.2
P2.1
P2.0
VDD
XIN/P1.3
XOUT/P1.2
VPP/RST/P1.1
1
U
14
2
13
3
12
4
11
5
10
6
9
7
8
SN8P2501AP
SN8P2501AS
P2.3
P2.4
P2.5
VSS
P0.0/INT0
P1.0
P5.4/PWM0/BZ0
P2.2
P2.1
P2.0
VDD
VDD
XIN/P1.3
XOUT/P1.2
VPP/RST/P1.1
1
U
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SN8P2501AX
P2.3
P2.4
P2.5
VSS
VSS
P0.0/INT0
P1.0
P5.4/PWM0/BZ0
1.3 PIN DESCRIPTIONS
SN8P2501A
PAD NAME
TYPE
DESCRIPTION
VDD, VSS
P
Power supply input pins. Place the 0.1µF bypass capacitor between the VDD and VSS pin.
P1.1: Input only pin (Schmitt trigger) if disable external reset function.
P1.1 without build-in pull-up resister
P1.1/RST/VPP
I, P
RST: System reset input pin. Schmitt trigger structure, low active, normal stay to “high”.
VPP: OTP programming pin.
P1.3: I/O pin (Schmitt trigger) if high clock select internal high RC oscillator / Built-in pull-up
P1.3/XIN
I/O
resister.
XIN: Oscillator input pin if high clock select external oscillator (crystal or RC type).
P1.2: I/O pin (Schmitt trigger) if high clock select internal high RC oscillator or external RC
P1.2/XOUT
I/O
type oscillator / Built-in pull-up resister.
XOUT: Oscillator output pin if high clock select external crystal type oscillator.
P0.0: I/O pin (Schmitt trigger) and shared with INT0 trigger pin (Schmitt trigger) / Built-in
P0.0/INT0
I/O
pull-up resister.
TC0 event counter clock input pin.
P1.0
I/O Port 1.0 bi-direction pin (Schmitt trigger) / Built-in pull-up resister / Open-Drain pin.
Port 5.4 bi-direction pin (Schmitt trigger) / Built-in pull-up resister.
P5.4/BZ0/PWM0
I/O
TC0 ÷ 2 signal output pin for buzzer and PWM output pin.
P2.0~P2.5
I/O Port 2.0~Port 2.5 bi-direction pins (Schmitt trigger) / Built-in pull-up resisters.
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
1.4 PIN CIRCUIT DIAGRAMS
Port 0, 2, 5 structure:
Pull-Up
PnM
PnM, PnUR
Pin
PnM
Output
Latch
Int. bus
Port 1.0 structure:
Pull-Up
PnM
PnM, PnUR
Pin
PnM
Output
Latch
Int. bus
Open-Drain
P1OC
Port 1.2 and Port 1.3 structure:
Pull-Up
PnM
PnM, PnUR
Pin
PnM
Oscillator
Code Option
Output
Latch
Int. bus
Int. Osc.
Port 1.1 structure:
Int. bus
Pin
Int. Rst
Ext. Rst Code Option
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2
CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
1K words ROM
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
.
.
000FH
0010H
0011H
.
.
.
.
.
03FBH
03FCH
03FDH
03FEH
03FFH
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ROM
Reset vector
General purpose area
User reset vector
Jump to user start address
Jump to user start address
Jump to user start address
Reserved
Interrupt vector
User interrupt vector
User program
General purpose area
End of user program
Reserved
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
USER RESET VECTOR ADDRESS (0000H)
A one-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow
reset, then the chip will restart the program from address 0000h and all system registers will be set as default values.
The following example shows the way to define the reset vector in the program memory.
Programming Tip: Defining Reset Vector
CHIP SN8P2501A
ORG
JMP
.
0
START
ORG
10H
START:
; 0000H
; Jump to user program address.
; 0004H ~ 0007H are reserved
; 0010H, The head of user program.
; User program
.
.
.
.
ENDP
; End of program
INTERRUPT VECTOR ADDRESS (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Programming Tip: Defining Interrupt Vector (Example 1)
CHIP SN8P2501A
.DATA
ACCBUF
PFLAGBUF
.CODE
ORG
JMP
.
0
START
; 0000H
; Jump to user program address.
; 0004H ~ 0007H are reserved
ORG
B0XCH
B0MOV
B0MOV
.
.
B0MOV
B0MOV
B0XCH
RETI
8
A, ACCBUF
A, PFLAG
PFLAGBUF, A
; Interrupt service routine
; B0XCH doesn’t change C, Z flag
A, PFLAGBUF
PFLAG, A
A, ACCBUF
START:
.
.
JMP
; Save PFLAG register in a buffer
; Restore PFLAG register from buffer
; B0XCH doesn’t change C, Z flag
; End of interrupt service routine
; The head of user program.
; User program
START
ENDP
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; End of user program
; End of program
Page 11
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
Programming Tip: Defining Interrupt Vector (Example 2)
CHIP SN8P2501A
.DATA
ACCBUF
PFLAGBUF
.CODE
ORG
JMP
.
0
START
ORG
JMP
08
MY_IRQ
ORG
10H
START:
.
.
.
JMP
; 0008H, Jump to interrupt service routine address
; 0010H, The head of user program.
; User program
START
MY_IRQ:
B0XCH
B0MOV
B0MOV
.
.
B0MOV
B0MOV
B0XCH
RETI
; 0000H
; Jump to user program address.
; 0001H ~ 0007H are reserved
A, ACCBUF
A, PFLAG
PFLAGBUF, A
A, PFLAGBUF
PFLAG, A
A, ACCBUF
ENDP
; End of user program
;The head of interrupt service routine
; B0XCH doesn’t change C, Z flag
; Save PFLAG register in a buffer
; Restore PFLAG register from buffer
; B0XCH doesn’t change C, Z flag
; End of interrupt service routine
; End of program
Remark: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The 0004H~0007H are reserved. Users is NOT allow to use 0004H~0007H addresses. We strongly
suggest users DO NOT take this value into the Check Sum. For detailed information, please check the
following Checksum Calculation section.
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
CHECKSUM CALCULATION
The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses
(0004H~0007H and last address) when calculate the Checksum value.
Example:
The demo program shows
user’s code
MOV
B0MOV
MOV
B0MOV
CLR
CLR
how to avoid 0004H~0007H when calculated Checksum from 00H to the end of
A,#END_USER_CODE$L
END_ADDR1,A
;save low end address to end_addr1
A,#END_USER_CODE$M
END_ADDR2,A
;save middle end address to end_addr2
Y
;set Y to 00H
Z
;set Z to 00H
@@:
CALL
MOVC
B0BSET
ADD
MOV
ADC
JMP
YZ_CHECK
FC
DATA1,A
A,R
DATA2,A
END_CHECK
INCMS
JMP
JMP
Z
@B
Y_ADD_1
MOV
CMPRS
JMP
MOV
CMPRS
JMP
JMP
A,END_ADDR1
A,Z
AAA
A,END_ADDR2
A,Y
AAA
CHECKSUM_END
MOV
CMPRS
RET
MOV
CMPRS
RET
INCMS
INCMS
INCMS
INCMS
RET
A,#04H
A,Z
;call function of check yz value
;
;clear C flag
;add A to Data1
;add R to Data2
;check if the YZ address = the end of code
AAA:
;Z=Z+1
;if Z!= 00H calculate to next address
;if Z=00H increase Y
END_CHECK:
YZ_CHECK:
A,#00H
A,Y
Z
Z
Z
Z
;check if Z = low end address
;if Not jump to checksum calculate
;if Yes, check if Y = middle end address
;if Not jump to checksum calculate
;if Yes checksum calculated is done.
;check if YZ=0004H
;check if Z=04H
;if Not return to checksum calculate
;if Yes, check if Y=00H
;if Not return to checksum calculate
;if Yes, increase 4 to Z
;set YZ=0008H then return
Y_ADD_1:
INCMS
NOP
JMP
Y
;increase Y
@B
;jump to checksum calculate
CHECKSUM_END:
……….
……….
END_USER_CODE:
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;Label of program end
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
GENERAL PURPOSE PROGRAM MEMORY AREA
The ROM location 0009H~03FBH are used as general-purpose memory. The area is to store both instruction’s
op-code and look-up table data. The SN8P2501A includes jump table function by using program counter (PC) and
look-up table function by using ROM code registers (R, Y, Z).
LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to the bit 8~bit 15 and Z register to the bit 0~bit 7 data of ROM
address. After MOVC instruction executed, the low-byte data will be stored in ACC and high-byte data stored in R
register.
Example: To look up the ROM data located “TABLE1”.
@@:
TABLE1:
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INCMS
JMP
INCMS
NOP
Z
@F
Y
MOVC
.
DW
DW
DW
.
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
;
; Increment the index address for next address
; Z+1
; Not overflow
; Z overflow (FFH
00),
Y=Y+1
;
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
;“
;“
CAUSION: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method to process
Y and Z registers automatically.
Example: INC_YZ Macro
INC_YZ
MACRO
INCMS
JMP
INCMS
NOP
Z
@F
; Z+1
; Not overflow
Y
; Y+1
; Not overflow
@@:
ENDM
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
Example: Increase Y and Z register by B0ADD/ADD instruction
B0MOV
B0MOV
Y, #TABLE1$M
Z, #TABLE1$L
; To set lookup table’s middle address.
; To set lookup table’s low address.
B0MOV
B0ADD
A, BUF
Z, A
; Z = Z + BUF.
B0BTS1
JMP
INCMS
NOP
FC
GETDATA
Y
; Check the carry flag.
; FC = 0
; FC = 1. Y+1.
.
0035H
5105H
2012H
;
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
.
.
;
; To define a word (16 bits) data.
;“
;“
GETDATA:
MOVC
TABLE1:
.
DW
DW
DW
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Page 15
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. It is
easy to make a multi-jump program depends on the value of the accumulator (A).
Example :
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
JMP
JMP
JMP
JMP
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
; PCL = PCL + ACC, the PCH can’t be changed.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
@JMP_A
MACRO
IF
JMP
ORG
ENDIF
ADD
ENDM
VAL
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
($ | 0XFF)
($ | 0XFF)
PCL, A
Note: “VAL” is the number of the jump table listing number.
Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; If ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h.
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Page 16
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.1.2 DATA MEMORY (RAM)
48 X 8-bit RAM
BANK 0
Address
000h
“
“
“
“
“
02Fh
080h
“
“
“
“
“
0FFh
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RAM location
General purpose area
80h~FFh of Bank 0 store system
registers (128 bytes).
System register
End of bank 0 area
Page 17
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.1.3 CODE OPTION TABLE
Code Option
Content
RC
32K X’tal
High_Clk
12M X’tal
4M X’tal
IHRC_16M
IHRC_RTC
Always_On
Watch_Dog
Enable
Disable
Fosc/1
Fcpu
16M_IHRC
Reset_Pin
Security
Low Power
Noise_Filter
Fosc/2
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
-2MHz
-1MHz
Normal
+1MHz
+2MHz
Reset
P11
Enable
Disable
Enable
Disable
Enable
Disable
Function Description
Low cost RC for external high clock oscillator and XOUT becomes to
general purpose I/O (P1.2).
Low frequency, power saving crystal (e.g. 32.768KHz) for external high
clock oscillator.
High speed crystal /resonator (e.g. 12MHz) for external high clock
oscillator.
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Internal high RC 16MHz and external oscillator pins as general purpose
I/O (XIN to P1.3, XOUT to P1.2).
Internal high RC 16MHz with RTC function and external oscillator pins
connect with 32.768KHz crystal to generating real time clock.
Watchdog timer always on even in power down and green mode.
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Disable Watchdog function.
Instruction cycle is oscillator clock.
Notice: In Fosc/1, Low Power must be disabled
Instruction cycle is 2 oscillator clocks.
Notice: In Fosc/2 Low Power must be disabled
Instruction cycle is 4 oscillator clocks.
Instruction cycle is 8 oscillator clocks.
Instruction cycle is 16 oscillator clocks.
Instruction cycle is 32 oscillator clocks.
Instruction cycle is 64 oscillator clocks.
Internal high RC 16MHz typical frequency - 2MHz.
Internal high RC 16MHz typical frequency -1MHz.
Internal high RC 16MHz typical frequency.
Internal high RC 16MHz typical frequency + 1MHz.
Internal high RC 16MHz typical frequency + 2MHz.
Enable External reset pin.
Enable P1.1 input only without pull-up resister.
Enable ROM code Security function.
Disable ROM code Security function.
Enable Low Power function to save Operating current.
Normal.
Enable Noise Filter and the Fcpu is Fosc/4~Fosc/64.
Disable Noise Filter and the Fcpu is Fosc/1~Fosc/64.
Notice:
If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog” automatically.
Enable “Low Power” option will reduce operating current except in “High_Clk = 32K X’tal” and
slow mode.
Enable “Low Power” will limit the Fcpu = Fosc/4 ~ Fosc/64.
Enable “Noise_Filter” will limit the Fcpu = Fosc/4 ~ Fosc/64.
Fcpu code option is only available for High Clock.
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Page 18
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.1.4 SYSTEM REGISTER
BYTES of SYSTEM REGISTER
SN8P2501A
0
1
8
9
A
B
C
D
E
F
2
3
4
5
6
7
8
9
A
B
C
D
E
F
-
-
R
Z
Y
-
PFLAG
-
OPTION
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PEDGE
-
-
-
-
-
-
-
-
P0M
-
-
-
-
-
-
P1W
P1M
P2M
-
-
P5M
-
-
INTRQ
INTEN
OSCM
-
WDTR
TC0R
PCL
PCH
P0
P1
P2
-
-
P5
-
-
T0M
T0C
TC0M
TC0C
-
-
-
STKP
P0UR
P1UR
P2UR
-
-
P5UR
-
@YZ
-
P1OC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
STK3L
STK3H STK2L STK2H STK1L STK1H STK0L STK0H
Description
PFLAG =
P1W =
PEDGE =
PnM =
P1OC =
INTRQ =
OSCM =
T0M =
TC0M =
TC0R =
STKP =
@YZ =
ROM page and special flag register.
Port 1 wakeup register.
P0.0 edge direction register.
Port n input/output mode register.
Port 1 open-drain control register.
Interrupt request register.
Oscillator mode register.
T0 mode register.
TC0 mode register.
TC0 auto-reload data buffer.
Stack pointer buffer.
RAM YZ indirect addressing index pointer.
SONiX TECHNOLOGY CO., LTD
R=
Y, Z =
OPTION =
Pn =
PnUR =
INTEN =
PCH, PCL =
T0C =
TC0C =
WDTR =
STK0~STK3 =
Page 19
Working register and ROM look-up data buffer.
Working, @YZ and ROM addressing register.
RTC period selection register.
Port n data buffer.
Port n pull-up resister control register.
Interrupt enable register.
Program counter.
TC0 counting register.
TC0 counting register.
Watchdog timer clear register.
Stack 0 ~ stack 3 buffer.
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
BITS of SYSTEM REGISTER
SN8P2501A system register table
Address
082H
083H
084H
086H
088H
0B8H
0BFH
0C0H
0C1H
0C2H
0C5H
0C8H
0C9H
0CAH
0CCH
0CDH
0CEH
0CFH
0D0H
0D1H
0D2H
0D5H
0D8H
0D9H
0DAH
0DBH
0DFH
0E0H
0E1H
0E2H
0E5H
0E7H
0E9H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
0FFH
Bit7
RBIT7
ZBIT7
YBIT7
NT0
0
WDTR7
TC0R7
PC7
T0ENB
T0C7
TC0ENB
TC0C7
GIE
@YZ7
S3PC7
S2PC7
S1PC7
S0PC7
-
Bit6
RBIT6
ZBIT6
YBIT6
NPD
0
WDTR6
TC0R6
PC6
T0rate2
T0C6
TC0rate2
TC0C6
@YZ6
S3PC6
S2PC6
S1PC6
S0PC6
-
Bit5
RBIT5
ZBIT5
YBIT5
P25M
TC0IRQ
TC0IEN
0
WDTR5
TC0R5
PC5
P25
T0rate1
T0C5
TC0rate1
TC0C5
P25R
@YZ5
S3PC5
S2PC5
S1PC5
S0PC5
-
Bit4
RBIT4
ZBIT4
YBIT4
P00G1
P24M
P54M
T0IRQ
T0IEN
CPUM1
WDTR4
TC0R4
PC4
P24
P54
T0rate0
T0C4
TC0rate0
TC0C4
P24R
P54R
@YZ4
S3PC4
S2PC4
S1PC4
S0PC4
-
Bit3
RBIT3
ZBIT3
YBIT3
RTC1
P00G0
P13W
P13M
P23M
CPUM0
WDTR3
TC0R3
PC3
P13
P23
T0C3
TC0CKS
TC0C3
P13R
P23R
@YZ3
S3PC3
S2PC3
S1PC3
S0PC3
-
Bit2
RBIT2
ZBIT2
YBIT2
C
RTC0
P12W
P12M
P22M
CLKMD
WDTR2
TC0R2
PC2
P12
P22
T0C2
ALOAD0
TC0C2
STKPB2
P12R
P22R
@YZ2
S3PC2
S2PC2
S1PC2
S0PC2
-
Bit1
RBIT1
ZBIT1
YBIT1
DC
P11W
P21M
STPHX
WDTR1
TC0R1
PC1
PC9
P11
P21
T0C1
TC0OUT
TC0C1
STKPB1
P21R
@YZ1
S3PC1
S3PC9
S2PC1
S2PC9
S1PC1
S1PC9
S0PC1
S0PC9
Bit0
RBIT0
ZBIT0
YBIT0
Z
P00M
P10W
P10M
P20M
P00IRQ
P00IEN
0
WDTR0
TC0R0
PC0
PC8
P00
P10
P20
T0TB
T0C0
PWM0OUT
TC0C0
STKPB0
P00R
P10R
P20R
@YZ0
P10OC
S3PC0
S3PC8
S2PC0
S2PC8
S1PC0
S1PC8
S0PC0
S0PC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
R
Z
Y
PFLAG
OPTION
P0M
PEDGE
P1W wakeup register
P1M I/O direction
P2M I/O direction
P5M I/O direction
INTRQ
INTEN
OSCM
WDTR
TC0R
PCL
PCH
P0 data buffer
P1 data buffer
P2 data buffer
P5 data buffer
T0M
T0C
TC0M
TC0C
STKP stack pointer
P0 pull-up register
P1 pull-up register
P2 pull-up register
P5 pull-up register
@YZ index pointer
P1OCopen-drain
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
Note
a): To avoid system error, please be sure to put all the “0” and “1” as it indicates in the above table
b). All of register names had been declared in SN8ASM assembler.
c). One-bit name had been declared in SN8ASM assembler with “F” prefix code.
d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.
e). For detail description, please refer to the “System Register Quick Reference Table”
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Page 20
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
can be used as general working registers
can be used as RAM data pointers with @YZ register
can be used as ROM data pointer with the MOVC instruction for look-up table
084H
Y
Read/Write
After reset
Bit 7
YBIT7
R/W
0
Bit 6
YBIT6
R/W
0
Bit 5
YBIT5
R/W
0
Bit 4
YBIT4
R/W
0
Bit 3
YBIT3
R/W
0
Bit 2
YBIT2
R/W
0
Bit 1
YBIT1
R/W
0
Bit 0
YBIT0
R/W
0
083H
Z
Read/Write
After reset
Bit 7
ZBIT7
R/W
0
Bit 6
ZBIT6
R/W
0
Bit 5
ZBIT5
R/W
0
Bit 4
ZBIT4
R/W
0
Bit 3
ZBIT3
R/W
0
Bit 2
ZBIT2
R/W
0
Bit 1
ZBIT1
R/W
0
Bit 0
ZBIT0
R/W
0
Example: uses YZ register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV
B0MOV
B0MOV
Y, #00H
Z, #25H
A, @YZ
; To set RAM bank 0 for Y register
; To set location 25H for Z register
; To read a data into ACC
Example: uses the YZ register as data pointer to clear the RAM data
B0MOV
B0MOV
Y, #0
Z, #07FH
; Y = 0, bank 0
; Y = 7FH, the last address of the data memory area
CLR
@YZ
; Clear @YZ to be zero
DECMS
JMP
Z
CLR_YZ_BUF
; Z – 1, if Z= 0, finish the routine
; Not zero
CLR
@YZ
CLR_YZ_BUF:
END_CLR:
; End of clear general purpose data memory area of bank 0
.
R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register.
can be used as working register
for store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H
R
Read/Write
After reset
Bit 7
RBIT7
R/W
0
Bit 6
RBIT6
R/W
0
Bit 5
RBIT5
R/W
0
Bit 4
RBIT4
R/W
0
Bit 3
RBIT3
R/W
0
Bit 2
RBIT2
R/W
0
Bit 1
RBIT1
R/W
0
Bit 0
RBIT0
R/W
0
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
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Page 21
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.2 ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
Example: Read and write ACC value.
; Read ACC data and store in BUF data memory
MOV
BUF, A
; Write a immediate data into ACC
MOV
A, #0FH
; Write ACC data from BUF data memory
MOV
A, BUF
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories.
Example: Protect ACC and working registers.
ACCBUF
PFLAGBUF
EQU
EQU
00H
01H
; ACCBUF is ACC data buffer.
; PFLAGBUF is PFLAG data buffer.
B0XCH
B0MOV
B0MOV
.
.
B0MOV
B0MOV
B0XCH
A, ACCBUF
A,PFLAG
PFLAGBUF,A
; Store ACC value.
A,PFLAGBUF
PFLAG,A
A, ACCBUF
; Re-load PFLAG value.
INT_SERVICE:
RETI
; Store PFLAG value.
; Re-load ACC value.
; Exit interrupt service vector
Note: To save and re-load ACC data, users must use “B0XCH” instruction, or else the PFLAG Register
might be modified by ACC operation.
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.3 PROGRAM FLAG
The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is
carry, borrow occurrence, then these flags will be set to PFLAG register.
086H
PFLAG
Read/Write
After reset
Bit 7
NT0
R/W
-
Bit 6
NPD
R/W
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
2.3.1 RESET FLAG
NT0 NPD Reset Status
0
0
Watch-dog time out
0
1
Reserved
1
0
Reset by LVD
1
1
Reset by external Reset Pin
2.3.2 CARRY FLAG
C = 1: When executed arithmetic addition with overflow or executed arithmetic subtraction without borrow or executed
rotation instruction with logic “1” shifting out.
C = 0: When executed arithmetic addition without overflow or executed arithmetic subtraction with borrow or executed
rotation instruction with logic “0”
2.3.3 DECIMAL CARRY FLAG
DC = 1: If executed arithmetic addition with overflow of low nibble or executed arithmetic subtraction without borrow of
low nibble.
DC = 0: If executed arithmetic addition without overflow of low nibble or executed arithmetic subtraction with borrow of
low nibble.
2.3.4 ZERO FLAG
Z = 1: When the content of ACC or target memory is zero after executing instructions involving a zero flag.
Z = 0: When the content of ACC or target memory is not zero after executing instructions involving a zero flag.
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Page 23
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.4 PROGRAM COUNTER
The program counter (PC) is a 10-bit binary counter separated into the high-byte 2 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 9.
PC
After
reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
PC9
-
-
-
-
-
-
0
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
0
0
0
0
0
0
0
0
0
PCH
PCL
2.4.1 ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
FC
C0STEP
; To skip, if Carry_flag = 1
; Else jump to C0STEP.
C0STEP:
B0BTS1
JMP
.
NOP
A, BUF0
FZ
C1STEP
; Move BUF0 value to ACC.
; To skip, if Zero flag = 0.
; Else jump to C1STEP.
C1STEP:
B0MOV
B0BTS0
JMP
.
NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
C0STEP:
CMPRS
JMP
.
NOP
A, #12H
C0STEP
; To skip, if ACC = 12H.
; Else jump to C0STEP.
If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
C0STEP:
INCS
JMP
…
NOP
BUF0
C0STEP
SONiX TECHNOLOGY CO., LTD
; Jump to C0STEP if ACC is not zero.
Page 24
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
INCMS instruction:
C0STEP:
INCMS
JMP
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next
instruction.
DECS instruction:
C0STEP:
DECS
JMP
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
DECMS
JMP
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
DECMS instruction:
C0STEP:
2.4.2 MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, An instruction (M = PCL) to activate
multi-address jumping function. If carry flag occurs after execution of ADD PCL, A, the carry flag will not affect PCH
register.
Example: If PC = 0323H (PCH = 03H、PCL = 23H)
; PC = 0323H
; PC = 0328H
MOV
B0MOV
.
.
.
MOV
B0MOV
A, #28H
PCL, A
.
.
.
A, #00H
PCL, A
; Jump to address 0328H
; Jump to address 0300H
Example: If PC = 0323H (PCH = 03H、PCL = 23H)
; PC = 0323H
B0ADD
JMP
JMP
JMP
JMP
.
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
.
SONiX TECHNOLOGY CO., LTD
; PCL = PCL + ACC, the PCH cannot be changed.
; If ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
;
Page 25
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.5 ADDRESSING MODE
2.5.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location (“ MOV A, # I ”, “ B0MOV
ACC or specific RAM.
M, # I “) in
Example: Immediate addressing mode
MOV
A, #12H
; To set an immediate data 12H into ACC
2.5.2
2.5.3 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.(“ MOV A,12H ”, “ MOV 12H,
A ”).
Example: Directly addressing mode
B0MOV
A, 12H
; To get a content of location 12H of bank 0 and save in ACC
2.5.4
2.5.5 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (Y/Z).
Example: Indirectly addressing mode with @YZ register
CLR
B0MOV
B0MOV
Y
Z, #12H
A, @YZ
SONiX TECHNOLOGY CO., LTD
; To clear Y register to access RAM bank 0.
; To set an immediate data 12H into Z register.
; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
Page 26
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.6 STACK OPERATIONS
2.6.1 OVERVIEW
The stack buffer of SN8P Series MCU has 4-level. These buffers are designed to push and pop up program counter’s
(PC) data when interrupt service routine is executed. The STKP register is a pointer designed to point active level in
order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program counter
(PC) data.
RET /
CALL /
RETI
interrupt
PCH
PCL
STK3H
STK3L
STK2H
STK2L
STKP = 3
STKP + 1
STKP -1
STKP = 2
STKP
STKP
STK1H
STK1L
STK0H
STK0L
STKP = 1
STKP = 0
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Page 27
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.6.2 STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 10-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push
operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to
the top address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0DFH
STKP
Read/Write
After reset
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
STKPBn: Stack pointer (n = 0 ~ 2)
GIE: Global interrupt control bit. 0 = disable, 1 = enable. Please refer to the interrupt chapter.
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the
beginning of the program.
MOV
B0MOV
A, #00000111B
STKP, A
0F0H~0FFH
Bit 7
Bit 6
STKnH
Read/Write
After reset
STKn = <STKnH , STKnL> (n = 3 ~ 0)
Bit 5
-
Bit 4
-
0F0H~0FFH
Bit 7
Bit 6
Bit 5
Bit 4
SnPC7
SnPC6
SnPC5
SnPC4
STKnL
Read/Write
R/W
R/W
R/W
R/W
After reset
0
0
0
0
For SN8P2501A : STKn = <STKnH , STKnL> (n = 3 ~ 0)
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Bit 3
-
Bit 2
-
Bit 1
SnPC9
R/W
0
Bit 0
SnPC8
R/W
0
Bit 3
SnPC3
R/W
0
Bit 2
SnPC2
R/W
0
Bit 1
SnPC1
R/W
0
Bit 0
SnPC0
R/W
0
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
2.6.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
0
1
2
3
4
>4
STKPB2
1
1
1
1
0
0
STKP Register
STKPB1
STKPB0
1
1
0
0
1
1
1
0
1
0
1
0
Stack Buffer
High Byte Low Byte
Free
STK0H
STK1H
STK2H
STK3H
-
Free
STK0L
STK1L
STK2L
STK3L
-
Description
Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
4
3
2
1
0
STKPB2
0
1
1
1
1
STKP Register
STKPB1
STKPB0
1
0
0
1
1
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1
0
1
0
1
Stack Buffer
High Byte Low Byte
STK3H
STK2H
STK1H
STK0H
Free
Page 29
STK3L
STK2L
STK1L
STK0L
Free
Description
-
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
3
RESET
3.1 OVERVIEW
This MCU provides two system resets. One is external reset and the other is internal low voltage detector (LVD). The
external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built-in internal circuit.
When one of the reset is triggered then will reset MCU and system registers become initial value. The timing diagram is
as the following.
VDD
LVD Detect Level
External Reset
External Reset Detect Level
LVD
End of LVD Reset
Internal Reset Signal
End of External Reset
Power on reset timing diagram
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8-Bit Micro-Controller
3.2 EXTERNAL RESET DESCRIPTION
The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the
voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system
operation.
VDD
External Reset
Internal Reset Signal
External Reset Detect Level
System Reset
End of External Reset
Users must make sure the VDD is stable earlier than external reset. Otherwise, the power on reset maybe fail.
The external reset circuit is a simple RC circuit as the following figure.
R
VDD
20K ohm
RST
C
0.1uF
MCU
VSS
VCC
GND
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
Under different environment, by placing a diode in between VCC and reset pin will help the Brownout reset.
R
DIODE
VDD
20K ohm
RST
C
0.1uF
MCU
VSS
VCC
GND
3.3 LOW VOLTAGE DETECTOR (LVD) DESCRIPTION
The LVD is a low voltage detector. It detects VDD level and reset the system as the VDD lower than the detected
voltage. The detect level is 1.8V. If the VDD lower than 1.8V, the system resets.
VDD
LVD Detect Level
LVD
System Reset
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End of LVD Reset
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
4
OSCILLATOR AND SYSTEM CLOCK
4.1 OVERVIEW
The SN8P2501A is a dual clock micro-controller system. There are high-speed clock and low-speed clock. The
high-speed clock is generated from the external oscillator circuit or on-chip 16MHz high-speed RC oscillator circuit
(IHRC 16MHz). The low-speed clock is generated from on-chip low-speed RC oscillator circuit (ILRC 16KHz @3V,
32KHz @5V).
Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock is divided by 4 to be
the instruction cycle (Fcpu).
Normal Mode (High Clock):
Fcpu = Fosc / N, N = 1 ~ 64, Select N by Fcpu code option
Slow Mode (Low Clock):
Fcpu = Fosc/4
4.2 CLOCK BLOCK DIAGRAM
STPHX
HOSC
IHOSC.
CPUM0
STPHX
XIN
XOUT
HOSC
HOSC
Noise Filter Code Option
÷ 1 ~ 64
EHOSC.
CLKMD
CPUM0
Fhosc
Flosc
Fcpu
CPUM0
ILOSC.
÷4
CPUM0
HOSC: High_Clk code option
EHOSC: External high-speed clock
IHRC: Internal high-speed RC clock
ILRC: Internal low-speed RC clock
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8-Bit Micro-Controller
4.3 OSCM REGISTER DESCRIPTION
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
0CAH
OSCM
Read/Write
After reset
Bit 7
0
-
Bit 6
0
-
Bit 5
0
-
Bit 4
CPUM1
R/W
0
Bit 3
CPUM0
R/W
0
Bit 2
CLKMD
R/W
0
Bit 1
STPHX
R/W
0
Bit 0
0
-
STPHX: External high-speed oscillator control bit. 0 = free run, 1 = stop. This bit only controls external high-speed
oscillator. If STPHX=1, the internal low-speed RC oscillator is still running.
CLKMD: System high/Low clock mode: bit 0 = normal (dual) mode, 1 = slow mode.
CPUM1, CPUM0: CPU operating mode control bit:
00 = normal
01 = sleep (power down) mode
10 = green mode
11 = reserved.
Example: Stop high-speed oscillator
B0BSET
FSTPHX
; To stop external high-speed oscillator only.
Example: When entering the Power Down mode, both high-speed oscillator and internal low-speed
oscillator will be stopped.
B0BSET
FCPUM0
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; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Page 34
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
4.4 EXTERNAL SYSTEM OSCILLATOR CIRCUITS
VDD
20PF
XIN
CRYSTAL
20PF
MCU
XOUT
VSS
Crystal/Ceramic Oscillator
VDD
R
XIN
XOUT
C
MCU
VSS
RC Oscillator
VDD
External Clock Input
XIN
XOUT
MCU
VSS
External clock input
Note1: The external oscillator circuit must be directly from Vss pin of micro-controller.
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8-Bit Micro-Controller
4.4.1 OSCILLATOR FREQUENCY MEASUREMENT
Under design period, the users can measure Fosc by software instruction cycle (Fcpu). This way is useful in RC mode.
Example: Fcpu instruction cycle of external oscillator
B0BSET
P1M.0
; Set P1.0 to be output mode for outputting Fcpu toggle signal.
B0BSET
B0BCLR
JMP
P1.0
P1.0
@B
; Output Fcpu toggle signal in low-speed clock mode.
; Measure the Fcpu frequency by oscilloscope.
@@:
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
value.
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8-Bit Micro-Controller
4.4.2 INTERNAL LOW-SPEED RC OSCILLATOR
The internal low-speed oscillator is built in the micro-controller. The low-speed clock source is a RC type oscillator
circuit.
Example: Stop internal low-speed oscillator
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0 bit of OSCM
register.
The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of
the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The
relation between the RC frequency and voltage is as the following figure.
Internal RC vs. VDD
40
38.678
35.343
Fintrc (KHz)
35
32.008
30
28.673
25.338
25
22.003
20
18.668
15.333
15
11.998
10
8.663
7.329
5
0
1.80
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
6.50
VDD (Volts)
Example: Measure the internal RC frequency by instruction cycle (Fcpu). The internal RC frequency is the
Fcpu multiplied by 4. We can get the Fosc frequency of internal RC from the Fcpu frequency.
B0BSET
P1M.0
; Set P1.0 to be output mode for outputting Fcpu toggle signal.
B0BSET
FCLKMD
; Switch the system clock to internal low-speed clock mode.
B0BSET
B0BCLR
JMP
P1.0
P1.0
@B
; Output Fcpu toggle signal in low-speed clock mode.
; Measure the Fcpu frequency by oscilloscope.
@@:
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SN8P2501A
8-Bit Micro-Controller
5
SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip is featured with low power consumption by switching around four different modes as following.
High-speed mode
Low-speed mode
Power-down mode (Sleep mode)
Green mode
5.2 NORMAL MODE
In normal mode, the system clock source is high clock (external or internal 16MHz RC oscillator). After power on reset,
watchdog reset, LVD reset or wakeup from power down mode, the system works under normal mode. From normal
mode, the system can get into power down mode, slow mode and green mode.
5.3 SLOW MODE
In slow mode, the system clock source is internal low-speed RC clock. To set CLKMD =1, the system switches into
slow mode. In slow mode, the system functions similar to the normal mode except using the internal low RC clock. The
system in slow mode can switch back to high-speed normal mode. On the other hand, it can be easily switch to power
down mode and green mode for less power consumption.
5.4 GREEN MODE
The green mode provides a time-variable wakeup function. Users can decide wakeup time by setting T0 timer. There
are two paths into green mode. One is from normal mode and the other is from slow mode. The system can be waked
up to last system mode by T0 timer timeout or P0, P1 level change trigger signal.
5.5 POWER DOWN MODE
The power down mode is also called sleep mode. The MCU stops working as sleeping status. To set CUPM0 = 1, the
system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can
be waked up by P0, P1 level change trigger signal.
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8-Bit Micro-Controller
5.6 SYSTEM MODE CONTROL
Power Down Mode
(Sleep Mode)
P0, P1 wake-up function active.
External reset circuit active.
CPUM1, CPUM0 = 01
CLKMD = 1
Normal Mode
Slow Mode
CLKMD = 0
CPUM1, CPUM0 = 10
P0, P1 wake-up function active.
P0, P1 wake-up function active.
TC0 time out.
TC0 time out.
External reset circuit active.
Green Mode
External reset circuit active.
System Mode Switching Diagram
Operating mode description
MODE
NORMAL
SLOW
GREEN
EHOSC
IHRC
ILRC
EHOSC with RTC
IHRC with RTC
ILRC with RTC
CPU instruction
Running
Running
Running
Running
Running
Running
Executing
By STPHX
By STPHX
Running
By STPHX
By STPHX
Running
Executing
By STPHX
By STPHX
Running
Running
Stop
Stop
Stop
POWER
DOWN
(SLEEP)
Stop
Stop
Stop
Stop
Stop
Stop
Stop
T0 timer
*Active
*Active
*Active
Inactive
TC0 timer
*Active
*Active
Inactive
Inactive
Watchdog timer
Internal interrupt
External interrupt
Wakeup source
REMARK
* Active by
program
* Active by
program
By watchdog By watchdog
By watchdog
By watchdog
code option code option
code option
code option
All active
All active
T0
All inactive
All active
All active
All active
All inactive
P0, P1, T0 Reset P0, P1, Reset
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8-Bit Micro-Controller
5.6.1 SYSTEM MODE SWITCHING
Switch normal/slow mode to power down (sleep) mode.
B0BSET
FCPUM0
; Set CPUM0 = 1.
During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
Switch normal mode to slow mode.
B0BSET
B0BSET
FCLKMD
FSTPHX
;To set CLKMD = 1, Change the system into slow mode
;To stop external high-speed oscillator for power saving.
Switch slow mode to normal mode (The external high-speed oscillator is still running)
B0BCLR
FCLKMD
;To set CLKMD = 0
Switch slow mode to normal mode (The external high-speed oscillator stops)
If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for
external clock stable.
@@:
B0BCLR
FSTPHX
; Turn on the external high-speed oscillator.
B0MOV
DECMS
JMP
Z, #27
Z
@B
; If VDD = 5V, internal RC=32KHz (typical) will delay
; 0.125ms X 81 = 10.125ms for external clock stable
B0BCLR
FCLKMD
;
; Change the system back to the normal mode
Switch normal/slow mode to green mode.
B0BSET
FCPUM1
; Set CPUM1 = 1.
During the green mode without T0 wake-up function, only the wakeup pin wakeup the system back to the
last mode.
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8-Bit Micro-Controller
Switch normal/slow mode to green mode and enable T0 wake-up function.
; Set T0 timer wakeup function.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
B0BCLR
B0BCLR
B0BSET
; Go into green mode
B0BCLR
B0BSET
FT0IEN
FT0ENB
A,#20H
T0M,A
A,#74H
T0C,A
FT0IEN
FT0IRQ
FT0ENB
; To disable T0 interrupt service
; To disable T0 timer
;
; To set T0 clock = Fcpu / 64
FCPUM0
FCPUM1
;To set CPUMx = 10
; To set T0C initial value = 74H (To set T0 interval = 10 ms)
; To disable T0 interrupt service
; To clear T0 interrupt request
; To enable T0 timer
During the green mode with T0 wake-up function, the wakeup pin and T0 wakeup the system back to the
last mode. T0 wake-up period is controlled by program.
Switch normal/slow mode to green mode and enable T0 wake-up function with RTC.
; Set T0 timer wakeup function with 0.5 sec RTC.
B0BCLR
FRTC1
B0BCLR
FRTC0
B0BSET
B0BSET
; Go into green mode
B0BCLR
B0BSET
; Set RTC timer period to 0.5 sec.
FT0ENB
FT0TB
; To enable T0 timer
; To enable RTC function
FCPUM0
FCPUM1
;To set CPUMx = 10
During the green mode with T0 RTC wake-up function, the wakeup pin and T0 wakeup the system back to
the last mode. The T0 wake-up period is controlled by OPTION register.
088H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OPTION
-
-
-
-
RTC1
RTC0
-
-
Read/Write
-
-
-
-
R/W
R/W
-
-
After reset
-
-
-
-
0
0
-
-
RTC1, RTC0: 00 = 0.5 sec. 01 = 1 sec. 10 = 2 sec. 11 = 4 sec.
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8-Bit Micro-Controller
5.7 WAKEUP
5.7.1 OVERVIEW
The high clock (external or internal 16MHz RC oscillator) needs a delay time from stopping to operating. The delay is
necessary for oscillator to be stabilized The delay time for high clock oscillator restart is sometimes called wakeup time.
Following are two conditions require wakeup time, one is switching power down mode to normal mode, and the other is
switching slow mode to normal mode. For the first condition, MCU provides 2048 oscillator clocks as the wakeup time.
The second condition, users need to take the wakeup time into consideration, which involved stabilizing period for start
up the external high-speed oscillator.
Under power down mode (sleep mode) or green mode, P0 and P1 with wakeup function are able to wake the system
up. Port 0 wakeup function always enables, but the Port 1 is controlled by the P1W register. The wakeup signal is level
change trigger.
5.7.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit.
After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as the following.
The Wakeup time = 1/Fosc * 2048 (sec) + X’tal settling time
The X’tal settling time is depended on the X’tal type. Typically, it is about 2~4mS in 4MHz Crystal oscillator
5.7.3 P1W WAKEUP CONTROL REGISTER
Under power down mode (sleep mode) or green mode, P0 and P1 with wakeup function are able to wakeup the system
Port 0 wakeup function is always available, but the Port 1 is controlled by the P1W register. The wakeup signal is level
change trigger.
0C0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1W
-
-
-
-
P13W
P12W
P11W
P10W
Read/Write
-
-
-
-
W
W
W
W
After reset
-
-
-
-
0
0
0
0
P10W~P13W: Port 1 wakeup function control bits. 0 = Disable; 1 = Enable wakeup function.
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8-Bit Micro-Controller
6
INTERRUPT
6.1 OVERVIEW
This MCU provides three interrupt sources, including two internal interrupt (T0/TC0) and one external interrupt (INT0).
The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal
mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt
request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All
of the interrupt request signals are stored in INTRQ register.
INTEN Interrupt enable register
T0IRQ
T0 time out
INTRQ
3-bit
Latchs
TC0 time out
INT0 trigger
Interrupt vector address (0008H)
Interrupt
enable
gating
TC0IRQ
P00IRQ
Global interrupt request signal
Note: The GIE bit must enable during all interrupt operation.
6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTEN
-
-
TC0IEN
T0IEN
-
-
-
P00IEN
Read/Write
-
-
R/W
R/W
-
-
-
R/W
After reset
-
-
0
0
-
-
-
0
P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable.
T0IEN : T0 Timer interrupt control bit 0 = disable, 1 = enable.
TC0IEN : TC0 Timer interrupt control bit 0 = disable, 1 = enable.
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6.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
0C8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTRQ
-
-
TC0IRQ
T0IRQ
-
-
-
P00IRQ
Read/Write
-
-
R/W
R/W
-
-
-
R/W
After reset
-
-
0
0
-
-
-
0
P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request.
T0IRQ : T0 timer interrupt request controls bit 0 = non request, 1 = request.
TC0IRQ : TC0 timer interrupt request controls bit 0 = non request, 1 = request.
6.4 INTERRUPT OPERATION DESCRIPTION
6.4.1 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
0DFH
STKP
Read/Write
After reset
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
GIE: Global interrupt control bit. 0 = disable, 1 = enable.
Example: Set global interrupt control bit (GIE).
B0BSET
FGIE
; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
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6.4.2 INT0 (P0.0) INTERRUPT OPERATION
The interrupt trigger direction is control by PEDGE register.
0BFH
PEDGE
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P00G1
R/W
1
Bit 3
P00G0
R/W
0
Bit 2
-
Bit 1
-
Bit 0
-
P00G[1:0]: P0.0 interrupt trigger edge control bits.
00 = reserved
01 = rising edge
10 = falling edge
11 = rising/falling bi-direction (Level change trigger).
Example: INT0 interrupt request setup.
B0BSET
B0BCLR
B0BSET
FP00IEN
FP00IRQ
FGIE
; Enable INT0 interrupt service
; Clear INT0 interrupt request flag
; Enable GIE
Example: INT0 interrupt service routine.
ACCBUF
PFLAGBUF
EQU
EQU
00H
01H
; ACCBUF is ACC data buffer.
; PFLAGBUF is PFLAG data buffer.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A,PFLAG
PFLAGBUF,A
; Store ACC value.
; Store PFLAG value.
B0BTS1
JMP
FP00IRQ
EXIT_INT
; Check P00IRQ
; P00IRQ = 0, exit interrupt vector
B0BCLR
.
.
FP00IRQ
.
.
; Reset P00IRQ
; INT0 interrupt service routine
B0MOV
B0MOV
B0XCH
A,PFLAGBUF
PFLAG,A
A, ACCBUF
; Re-load PFLAG value.
INT_SERVICE:
EXIT_INT:
RETI
; Re-load ACC value.
; Exit interrupt vector
When the INT0 trigger occurs, the P00IRQ will be set to “1” no matter the P00IEN is enable or disable. If the P00IEN =
1 and the trigger event P00IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG
8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt
vector even when the P00IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt
situation.
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6.4.3 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
Example: T0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FT0IEN
FT0ENB
A, #20H
T0M, A
A, #74H
T0C, A
; Disable T0 interrupt service
; Disable T0 timer
;
; Set T0 clock = Fcpu / 64
; Set T0C initial value = 74H
; Set T0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FT0IEN
FT0IRQ
FT0ENB
; Enable T0 interrupt service
; Clear T0 interrupt request flag
; Enable T0 timer
B0BSET
FGIE
; Enable GIE
Example: T0 interrupt service routine.
ACCBUF
PFLAGBUF
EQU
EQU
00H
01H
; ACCBUF is ACC data buffer.
; PFLAGBUF is PFLAG data buffer.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A,PFLAG
PFLAGBUF,A
; Store ACC value.
; Store PFLAG value.
B0BTS1
JMP
FT0IRQ
EXIT_INT
; Check T0IRQ
; T0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
.
.
FT0IRQ
A, #74H
T0C, A
.
.
; Reset T0IRQ
B0MOV
B0MOV
B0XCH
A,PFLAGBUF
PFLAG,A
A, ACCBUF
INT_SERVICE:
; Reset T0C.
; T0 interrupt service routine
EXIT_INT:
RETI
; Re-load PFLAG value.
; Re-load ACC value.
; Exit interrupt vector
When the T0C counter overflows, the T0IRQ will be set to “1” no matter the T0IEN is enable or disable. If the T0IEN
and the trigger event T0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the T0IEN =
0, the trigger event T0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the
T0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
6.4.4 TC0 INTERRUPT OPERATION
Example: TC0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC0IEN
FTC0ENB
A, #20H
TC0M, A
A, #74H
TC0C, A
; Disable TC0 interrupt service
; Disable TC0 timer
;
; Set TC0 clock = Fcpu / 64
; Set TC0C initial value = 74H
; Set TC0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC0IEN
FTC0IRQ
FTC0ENB
; Enable TC0 interrupt service
; Clear TC0 interrupt request flag
; Enable TC0 timer
B0BSET
FGIE
; Enable GIE
Example: TC0 interrupt service routine.
ACCBUF
PFLAGBUF
EQU
EQU
00H
01H
; ACCBUF is ACC data buffer.
; PFLAGBUF is PFLAG data buffer.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A,PFLAG
PFLAGBUF,A
; Store ACC value.
; Store PFLAG value.
B0BTS1
JMP
FTC0IRQ
EXIT_INT
; Check TC0IRQ
; TC0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
.
.
FTC0IRQ
A, #74H
TC0C, A
.
.
; Reset TC0IRQ
B0MOV
B0MOV
B0XCH
A,PFLAGBUF
PFLAG,A
A, ACCBUF
INT_SERVICE:
; Reset TC0C.
; TC0 interrupt service routine
EXIT_INT:
RETI
; Re-load PFLAG value.
; Re-load ACC value.
; Exit interrupt vector
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
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Preliminary Version 0.2
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8-Bit Micro-Controller
6.4.5 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name
P00IRQ
T0IRQ
TC0IRQ
Trigger Event Description
P0.0 trigger controlled by PEDGE
T0C overflow
TC0C overflow
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
Example: Check the interrupt request under multi-interrupt operation
ACCBUF
PFLAGBUF
EQU
EQU
00H
01H
; ACCBUF is ACC data buffer.
; PFLAGBUF is PFLAG data buffer.
ORG
8
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A,PFLAG
PFLAGBUF,A
; Store ACC value.
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTTC0CHK
FP00IRQ
INTP00
B0BTS1
JMP
B0BTS0
JMP
FT0IEN
INT_EXIT
FT0IRQ
INTT0
B0BTS1
JMP
B0BTS0
JMP
FTC0IEN
INT_EXIT
FTC0IRQ
INTTC0
B0MOV
B0MOV
B0XCH
A,PFLAGBUF
PFLAG,A
A, ACCBUF
INTP00CHK:
INTTC0CHK:
INTTC0CHK:
; Store PFLAG value.
; Check INT0 interrupt request
; Check P00IEN
; Jump check to next interrupt
; Check P00IRQ
; Jump to INT0 interrupt service routine
; Check TC0 interrupt request
; Check T0IEN
; Jump to exit of IRQ
; Check T0IRQ
; Jump to T0 interrupt service routine
; Check TC0 interrupt request
; Check TC0IEN
; Jump to exit of IRQ
; Check TC0IRQ
; Jump to TC0 interrupt service routine
INT_EXIT:
RETI
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; Re-load PFLAG value.
; Re-load ACC value.
; Exit interrupt vector
Page 48
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
7
I/O PORT
7.1 I/O PORT MODE
The port direction is programmed by PnM register. All I/O ports can select input or output direction.
0B8H
P0M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
P00M
R/W
0
0C1H
P1M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P13M
R/W
0
Bit 2
P12M
R/W
0
Bit 1
-
Bit 0
P10M
R/W
0
P1.1 is input only pin, and the P1M.1 keeps “1”.
0C2H
P2M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
P25M
R/W
0
Bit 4
P24M
R/W
0
Bit 3
P23M
R/W
0
Bit 2
P22M
R/W
0
Bit 1
P21M
R/W
0
Bit 0
P20M
R/W
0
0C5H
P5M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P54M
R/W
0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
When PnM=0, the Pn is input mode
PnM=1, the Pn is output mode
Users can program them by bit control instructions (B0BSET, B0BCLR).
Example: I/O mode selecting
CLR
CLR
CLR
CLR
P0M
P1M
P2M
P5M
; Set all ports to be input mode.
MOV
B0MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0M, A
P1M, A
P2M, A
P5M, A
; Set all ports to be output mode.
B0BCLR
P1M.2
; Set P1.2 to be input mode.
B0BSET
P1M.2
; Set P1.2 to be output mode.
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Preliminary Version 0.2
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8-Bit Micro-Controller
7.2 I/O PULL UP REGISTER
0E0H
P0UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
P00R
W
0
0E1H
P1UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P13R
W
0
Bit 2
P12R
W
0
Bit 1
-
Bit 0
P10R
W
0
P1.1 is input only pin and without pull-up resister. The P1UR.1 keeps “1”.
0E2H
P2UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
P25R
W
0
Bit 4
P24R
W
0
Bit 3
P23R
W
0
Bit 2
P22R
W
0
Bit 1
P21R
W
0
Bit 0
P20R
W
0
0E5H
P5UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P54R
W
0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Bit 1
-
Bit 0
P10OC
W
0
Example: I/O Pull up Register
MOV
B0MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0UR, A
P1UR, A
P2UR, A
P5UR, A
; Enable Port0, 1, 2, 5 Pull-up register,
;
7.3 I/O OPEN-DRAIN REGISTER
Port1
0E9H
P1OC
Read/Write
After reset
Bit 0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
P10OC: P10 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
7.4 I/O PORT DATA REGISTER
0D0H
P0
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
P00
R/W
0
0D1H
P1
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P13
R/W
0
Bit 2
P12
R/W
0
Bit 1
P11
R
0
Bit 0
P10
R/W
0
The P11 keeps “1” when external reset enable by code option.
0D2H
P2
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
P25
R/W
0
Bit 4
P24
R/W
0
Bit 3
P23
R/W
0
Bit 2
P22
R/W
0
Bit 1
P21
R/W
0
Bit 0
P20
R/W
0
0D5H
P5
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P54
R/W
0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Example: Read data from input port.
B0MOV
A, P0
B0MOV
A, P1
B0MOV
A, P2
B0MOV
A, P5
Example: Write data to output port.
MOV
A, #0FFH
B0MOV
P0, A
B0MOV
P1, A
B0MOV
P2, A
B0MOV
P5, A
Example: Write one bit data to output port.
B0BSET
P1.3
B0BSET
P2.5
B0BCLR
B0BCLR
P1.3
P2.5
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; Read data from Port 0
; Read data from Port 1
; Read data from Port 2
; Read data from Port 5
; Write data FFH to all Port.
; Set P1.3 and P2.5 to be “1”.
; Set P1.3 and P2.5 to be “0”.
Page 51
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
8
TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (ILRC, 16K @3V, 32K @5V).
Watchdog overflow time is about 0.5 sec @3V, 0.25 sec @5V.
If watchdog is “Always_On” mode, it keeps running event under power down mode or green mode.
For S8KD ICE simulation, clear watchdog timer using “@RST_WDT” macro is necessary. Or the S8KD
watchdog would be error. Please use "@RST_WDT" macro to clear the watchdog timer successfully both
in S8KD ICE emulation and real chip.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH
WDTR
Read/Write
After reset
Bit 7
WDTR7
W
0
Bit 6
WDTR6
W
0
Bit 5
WDTR5
W
0
Bit 4
WDTR4
W
0
Bit 3
WDTR3
W
0
Bit 2
WDTR2
W
0
Bit 1
WDTR1
W
0
Bit 0
WDTR0
W
0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
MOV
B0MOV
.
CALL
CALL
.
.
.
JMP
A,#5AH
WDTR,A
.
SUB1
SUB2
.
.
.
MAIN
; Clear the watchdog timer.
Example: Clear watchdog timer by @RST_WDT macro.
Main:
@RST_WDT
.
CALL
CALL
.
.
.
JMP
; Clear the watchdog timer.
.
SUB1
SUB2
.
.
.
MAIN
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
8.2 TIMER 0 (T0)
8.2.1 OVERVIEW
The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue
counting and issue a time-out signal to trigger T0 interrupt to request interrupt service.
The main purposes of the T0 timer is as following.
8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock
frequency.
RTC timer: Generates interrupts at real time intervals based on the selected clock source. RTC function is
only available in High_Clk code option = "IHRC_RTC".
Green mode wakeup function: T0ENB = 1, T0 time out to make system return to last mode in green mode.
T0rate
Internal data bus
T0enb
T0TB
pre_load
T0C 8-bit binary counter
Fcpu
T0 Time out
T0enb
RTC
RTC1, RTC0 period control
8.2.2 T0M MODE REGISTER
0D8H
T0M
Read/Write
After reset
Bit 7
T0ENB
R/W
0
Bit 6
T0rate2
R/W
0
Bit 5
T0rate1
R/W
0
Bit 4
T0rate0
R/W
0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
T0TB
R/W
0
T0ENB: T0 counter control bit. 0 = disable, 1 = enable.
T0RATE2~T0RATE0: T0 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 = fcpu/2.
T0TB: RTC clock source control bit. 0 = disable (from Fcpu). 1 = enable (from RTC).
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Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
8.2.3 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control.
0D9H
T0C
Read/Write
After reset
Bit 7
T0C7
R/W
0
Bit 6
T0C6
R/W
0
Bit 5
T0C5
R/W
0
Bit 4
T0C4
R/W
0
Bit 3
T0C3
R/W
0
Bit 2
T0C2
R/W
0
Bit 1
T0C1
R/W
0
Bit 0
T0C0
R/W
0
The basic timer table interval time of T0
T0RATE
T0CLOCK
000
001
010
011
100
101
110
111
fcpu/256
fcpu/128
fcpu/64
fcpu/32
fcpu/16
fcpu/8
fcpu/4
fcpu/2
High speed mode (Fcpu = 3.58MHz / 4)
Max overflow interval One step = max/256
73.2 ms
286us
36.6 ms
143us
18.3 ms
71.5us
9.15 ms
35.8us
4.57 ms
17.9us
2.28 ms
8.94us
1.14 ms
4.47us
0.57 ms
2.23us
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval One step = max/256
8000 ms
31.25 ms
4000 ms
15.63 ms
2000 ms
7.8 ms
1000 ms
3.9 ms
500 ms
1.95 ms
250 ms
0.98 ms
125 ms
0.49 ms
62.5 ms
0.24 ms
The equation of T0C initial value is as following.
T0C initial value = 256 - (T0 interrupt interval time * input clock)
Example: To set 10ms interval time for T0 interrupt at 3.58MHz high-speed mode. T0C value (74H) = 256 (10ms * fcpu/64). Let Fcpu = Fosc / 4
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (10ms * 3.58 * 106 / 4 / 64)
= 256 - (10-2 * 3.58 * 106 / 4 / 64)
= 116
= 74H
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Preliminary Version 0.2
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8-Bit Micro-Controller
8.3 TIMER/COUNTER 0 (TC0)
8.3.1 OVERVIEW
The TC0 is an 8-bit binary up timer and event counter, using TC0M register to select TC0C’s clock source from Fcpu or
from external INT0 pin (falling edge trigger) for counting a precision time. If TC0 timer occurs an overflow (from FFH to
00H), it will continue counting and issue a time-out signal to trigger TC0 interrupt to request interrupt service.
The main purposes of the TC0 timer is as following.
8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock
frequency.
External event counter: Counts system “events” based on falling edge detection of external clock signals at
the INT0 input pin.
Buzzer output
PWM output
Aload0
TC0R reload
data buffer
Internal P5.4 I/O circuit
Buzzer
Auto. reload
Compare
S
TC0cks TC0enb
P5.4
÷2
R
TC0rate
TC0out
PWM
PWM0OUT
load
Fcpu
TC0C
8-bit binary counter
INT0
(schmitter trigger)
TC0 Time out
CPUM1,0
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Preliminary Version 0.2
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8-Bit Micro-Controller
8.3.2 TC0M MODE REGISTER
0DAH
TC0M
Read/Write
After reset
Bit 7
TC0ENB
R/W
0
Bit 6
TC0rate2
R/W
0
Bit 5
TC0rate1
R/W
0
Bit 4
TC0rate0
R/W
0
Bit 3
TC0CKS
R/W
0
Bit 2
ALOAD0
R/W
0
Bit 1
TC0OUT
R/W
0
Bit 0
PWM0OUT
R/W
0
TC0ENB: TC0 counter control bit. 0 = disable, 1 = enable.
TC0RATE2~TC0RATE0: TC0 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 =
fcpu/2.
TC0CKS: TC0 clock source select bit. 0 = Fcpu, 1 = External clock comes from INT0/P0.0 pin.
ALOAD0: Auto-reload control bit. 0 = disable. 1 = enable.
TC0OUT: TC0 time out toggle signal output control bit. Only valid when PWM0OUT = 0.
0 = Disable, P5.4 is I/O function.
1 = Enable, P5.4 is output TC0OUT signal.
PWM0OUT: PWM output control bit. 0 = disable. 1 = enable.
PWM duty selection table. (Only valid when PWM0OUT = 1)
Max PWM
ALOAD0 TC0OUT TC0 Overflow boundary PWM duty range
Frequency
Note
(Fcpu = 4M)
0
0
FFh to 00h
0/256 ~ 255/256
7.8125K
Overflow per 256 count
0
1
3Fh to 40h
0/64 ~ 63/64
31.25K
Overflow per 64 count
1
0
1Fh to 20h
0/32 ~ 31/32
62.5K
Overflow per 32 count
1
1
0Fh to 10h
0/16 ~ 15/16
125K
Overflow per 16 count
Note: When TC0CKS=1, TC0 became an external event counter. No more P0.0 interrupt request will be
raised. (P0.0IRQ will be always 0)
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Preliminary Version 0.2
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8-Bit Micro-Controller
8.3.3 TC0C COUNTING REGISTER
TC0C is an 8-bit counter register for TC0 interval time control.
0DBH
TC0C
Read/Write
After reset
Bit 7
TC0C7
R/W
0
Bit 6
TC0C6
R/W
0
Bit 5
TC0C5
R/W
0
Bit 4
TC0C4
R/W
0
Bit 3
TC0C3
R/W
0
Bit 2
TC0C2
R/W
0
Bit 1
TC0C1
R/W
0
Bit 0
TC0C0
R/W
0
The basic timer table interval time of TC0
TC0RATE TC0CLOCK
000
001
010
011
100
101
110
111
fcpu/256
fcpu/128
fcpu/64
fcpu/32
fcpu/16
fcpu/8
fcpu/4
fcpu/2
High speed mode (Fcpu = 3.58MHz / 4)
Max overflow interval One step = max/256
73.2 ms
286us
36.6 ms
143us
18.3 ms
71.5us
9.15 ms
35.8us
4.57 ms
17.9us
2.28 ms
8.94us
1.14 ms
4.47us
0.57 ms
2.23us
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval One step = max/256
8000 ms
31.25 ms
4000 ms
15.63 ms
2000 ms
7.8 ms
1000 ms
3.9 ms
500 ms
1.95 ms
250 ms
0.98 ms
125 ms
0.49 ms
62.5 ms
0.24 ms
The equation of TC0C initial value is as following.
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
Example: To set 10ms interval time for TC0 interrupt at 3.58MHz high-speed mode. TC0C value (74H) =
256 - (10ms * fcpu/64). Let Fcpu = Fosc / 4
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
= 256 - (10ms * 3.58 * 106 / 4 / 64)
= 256 - (10-2 * 3.58 * 106 / 4 / 64)
= 116
= 74H
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Preliminary Version 0.2
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8-Bit Micro-Controller
8.4 BUZZER OUTPUT
Buzzer output (TC0OUT) is from TC0 timer/counter frequency output function. By setting the TC0 clock frequency, the
clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0 output signal divides
by 2. The TC0 clock has many combinations and easily to make difference frequency. The TC0OUT frequency
waveform is as following.
TC0 Clock
TC0OUT Pulse
Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The
TC0OUT frequency is 0.5KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 1KHz. The
TC0 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110.
TC0C = TC0R = 131.
MOV
B0MOV
A,#01100000B
TC0M,A
MOV
B0MOV
B0MOV
A,#131
TC0C,A
TC0R,A
; Set the auto-reload reference value
B0BSET
B0BSET
B0BSET
FTC0OUT
FALOAD0
FTC0ENB
; Enable TC0 output to P5.4 and disable P5.4 I/O function
; Enable TC0 auto-reload function
; Enable TC0 timer
SONiX TECHNOLOGY CO., LTD
; Set the TC0 rate to Fcpu/4
Page 58
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
8.4.1 TC0OUT FREQUENCY TABLE
Fosc = 4MHz, TC0 Rate = Fcpu/8
TC0R
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
TC0OUT
(KHz)
0.2441
0.2451
0.2461
0.2470
0.2480
0.2490
0.2500
0.2510
0.2520
0.2530
0.2541
0.2551
0.2561
0.2572
0.2583
0.2593
0.2604
0.2615
0.2626
0.2637
0.2648
0.2660
0.2671
0.2682
0.2694
0.2706
0.2717
0.2729
0.2741
0.2753
0.2765
0.2778
0.2790
0.2803
0.2815
0.2828
0.2841
0.2854
0.2867
0.2880
0.2894
0.2907
0.2921
0.2934
0.2948
0.2962
0.2976
0.2990
0.3005
0.3019
0.3034
0.3049
0.3064
0.3079
0.3094
0.3109
TC0R
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
TC0OUT
(KHz)
0.3125
0.3141
0.3157
0.3173
0.3189
0.3205
0.3222
0.3238
0.3255
0.3272
0.3289
0.3307
0.3324
0.3342
0.3360
0.3378
0.3397
0.3415
0.3434
0.3453
0.3472
0.3492
0.3511
0.3531
0.3551
0.3571
0.3592
0.3613
0.3634
0.3655
0.3676
0.3698
0.3720
0.3743
0.3765
0.3788
0.3811
0.3834
0.3858
0.3882
0.3906
0.3931
0.3956
0.3981
0.4006
0.4032
0.4058
0.4085
0.4112
0.4139
0.4167
0.4195
0.4223
0.4252
0.4281
0.4310
SONiX TECHNOLOGY CO., LTD
TC0R
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
TC0OUT
(KHz)
0.4340
0.4371
0.4401
0.4433
0.4464
0.4496
0.4529
0.4562
0.4596
0.4630
0.4664
0.4699
0.4735
0.4771
0.4808
0.4845
0.4883
0.4921
0.4960
0.5000
0.5040
0.5081
0.5123
0.5165
0.5208
0.5252
0.5297
0.5342
0.5388
0.5435
0.5482
0.5531
0.5580
0.5631
0.5682
0.5734
0.5787
0.5841
0.5896
0.5952
0.6010
0.6068
0.6127
0.6188
0.6250
0.6313
0.6378
0.6443
0.6510
0.6579
0.6649
0.6720
0.6793
0.6868
0.6944
0.7022
Page 59
TC0R
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
TC0OUT
(KHz)
0.7102
0.7184
0.7267
0.7353
0.7440
0.7530
0.7622
0.7716
0.7813
0.7911
0.8013
0.8117
0.8224
0.8333
0.8446
0.8562
0.8681
0.8803
0.8929
0.9058
0.9191
0.9328
0.9470
0.9615
0.9766
0.9921
1.0081
1.0246
1.0417
1.0593
1.0776
1.0965
1.1161
1.1364
1.1574
1.1792
1.2019
1.2255
1.2500
1.2755
1.3021
1.3298
1.3587
1.3889
1.4205
1.4535
1.4881
1.5244
1.5625
1.6026
1.6447
1.6892
1.7361
1.7857
1.8382
1.8939
TC0R
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
TC0OUT
(KHz)
1.9531
2.0161
2.0833
2.1552
2.2321
2.3148
2.4038
2.5000
2.6042
2.7174
2.8409
2.9762
3.1250
3.2895
3.4722
3.6765
3.9063
4.1667
4.4643
4.8077
5.2083
5.6818
6.2500
6.9444
7.8125
8.9286
10.4167
12.5000
15.6250
20.8333
31.2500
62.5000
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
Fosc = 16MHz, TC0 Rate = Fcpu/8
TC0R
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
TC0OUT
(KHz)
0.9766
0.9804
0.9843
0.9881
0.9921
0.9960
1.0000
1.0040
1.0081
1.0121
1.0163
1.0204
1.0246
1.0288
1.0331
1.0373
1.0417
1.0460
1.0504
1.0549
1.0593
1.0638
1.0684
1.0730
1.0776
1.0823
1.0870
1.0917
1.0965
1.1013
1.1062
1.1111
1.1161
1.1211
1.1261
1.1312
1.1364
1.1416
1.1468
1.1521
1.1574
1.1628
1.1682
1.1737
1.1792
1.1848
1.1905
1.1962
1.2019
1.2077
1.2136
1.2195
1.2255
1.2315
1.2376
1.2438
TC0R
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
TC0OUT
(KHz)
1.2500
1.2563
1.2626
1.2690
1.2755
1.2821
1.2887
1.2953
1.3021
1.3089
1.3158
1.3228
1.3298
1.3369
1.3441
1.3514
1.3587
1.3661
1.3736
1.3812
1.3889
1.3966
1.4045
1.4124
1.4205
1.4286
1.4368
1.4451
1.4535
1.4620
1.4706
1.4793
1.4881
1.4970
1.5060
1.5152
1.5244
1.5337
1.5432
1.5528
1.5625
1.5723
1.5823
1.5924
1.6026
1.6129
1.6234
1.6340
1.6447
1.6556
1.6667
1.6779
1.6892
1.7007
1.7123
1.7241
SONiX TECHNOLOGY CO., LTD
TC0R
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
TC0OUT
(KHz)
1.7361
1.7483
1.7606
1.7730
1.7857
1.7986
1.8116
1.8248
1.8382
1.8519
1.8657
1.8797
1.8939
1.9084
1.9231
1.9380
1.9531
1.9685
1.9841
2.0000
2.0161
2.0325
2.0492
2.0661
2.0833
2.1008
2.1186
2.1368
2.1552
2.1739
2.1930
2.2124
2.2321
2.2523
2.2727
2.2936
2.3148
2.3364
2.3585
2.3810
2.4038
2.4272
2.4510
2.4752
2.5000
2.5253
2.5510
2.5773
2.6042
2.6316
2.6596
2.6882
2.7174
2.7473
2.7778
2.8090
Page 60
TC0R
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
TC0OUT
(KHz)
2.8409
2.8736
2.9070
2.9412
2.9762
3.0120
3.0488
3.0864
3.1250
3.1646
3.2051
3.2468
3.2895
3.3333
3.3784
3.4247
3.4722
3.5211
3.5714
3.6232
3.6765
3.7313
3.7879
3.8462
3.9063
3.9683
4.0323
4.0984
4.1667
4.2373
4.3103
4.3860
4.4643
4.5455
4.6296
4.7170
4.8077
4.9020
5.0000
5.1020
5.2083
5.3191
5.4348
5.5556
5.6818
5.8140
5.9524
6.0976
6.2500
6.4103
6.5789
6.7568
6.9444
7.1429
7.3529
7.5758
TC0R
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
TC0OUT
(KHz)
7.8125
8.0645
8.3333
8.6207
8.9286
9.2593
9.6154
10.0000
10.4167
10.8696
11.3636
11.9048
12.5000
13.1579
13.8889
14.7059
15.6250
16.6667
17.8571
19.2308
20.8333
22.7273
25.0000
27.7778
31.2500
35.7143
41.6667
50.0000
62.5000
83.3333
125.0000
250.0000
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
8.5 PWM FUNCTION DESCRIPTION
8.5.1 OVERVIEW
PWM function is generated by TC0 timer counter and output the PWM signal to PWM0OUT pin (P5.4). The 8-bit
counter counts modulus 256, 64, 32, 16 controlled by ALOAD0, TC0OUT bits. The value of the 8-bit counter is
compared to the contents of the reference register (TC0R). When the reference register value (TC0R) is equal to the
counter value (TC0C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The
low-to-high ratio (duty) of the PWM0 output is TC0R/256, 64, 32, 16.
PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to
change the PWM’s duty cycle is to modify the TC0R.
ALOAD0 TC0OUT PWM duty range
0
0
1
1
0
1
0
1
TC0C valid value TC0R valid bits value
0/256~255/256
0/64~63/64
0/32~31/32
0/16~15/16
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
MAX. PWM
Frequency
(Fcpu = 4MHz)
7.8125K
31.25K
62.5K
125K
Remark
Overflow per 256 count
Overflow per 64 count
Overflow per 32 count
Overflow per 16 count
The Output duty of PWM with different TC0R. Duty range is from 0/256~255/256.
0
1
..... 128
..... 254 255
0
1
..... 128
..... 254 255
TC0/TC1 Clock
TC0R/TC1R = 00H
Low
High
TC0R/TC1R = 01H
Low
High
TC0R/TC1R = 80H
Low
High
TC0R/TC1R = FFH
Low
SONiX TECHNOLOGY CO., LTD
Page 61
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
8.5.2 PWM PROGRAM DESCRIPTION
Example: Setup PWM0 output from TC0 to PWM0OUT (P5.4). The external high-speed oscillator clock is
4MHz. Fcpu = Fosc/4. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock
source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C =
TC0R = 30.
MOV
B0MOV
A,#01100000B
TC0M,A
MOV
B0MOV
B0MOV
A,#30
TC0C,A
TC0R,A
; Set the PWM duty to 30/256
B0BCLR
B0BCLR
B0BSET
B0BSET
FTC0OUT
FALOAD0
FPWM0OUT
FTC0ENB
; Set duty range as 0/256~255/256.
; Set the TC0 rate to Fcpu/4
; Enable PWM0 output to P5.4 and disable P5.4 I/O function
; Enable TC0 timer
Note: The TC0R is write-only registers. Don’t process them using INCMS, DECMS instructions.
Example: Modify TC0R registers’ value.
MOV
B0MOV
A, #30H
TC0R, A
; Input a number using B0MOV instruction.
INCMS
B0MOV
B0MOV
BUF0
A, BUF0
TC0R, BUF0
; Get the new TC0R value from the BUF0 buffer defined by
; programming.
Note: That is better to set the TC0C and TC0R value together when PWM0 duty modified. It protects the
PWM0 signal no glitch as PWM0 duty changing.
Note: The PWM can work with interrupt request.
SONiX TECHNOLOGY CO., LTD
Page 62
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
9
Field
M
O
V
E
A
R
I
T
H
M
E
T
I
C
L
O
G
I
C
P
R
O
C
E
S
S
B
R
A
N
C
H
INSTRUCTION SET TABLE
Mnemonic
MOV
A,M
MOV
M,A
B0MOV
A,M
B0MOV
M,A
MOV
A,I
B0MOV
M,I
XCH
A,M
B0XCH
A,M
MOVC
Description
A←M
M←A
A ← M (bank 0)
M (bank 0) ← A
A←I
M ← I, (M = only for Working registers R, Y, Z , RBANK & PFLAG)
A ←→M
A ←→M (bank 0)
R, A ← ROM [Y,Z]
C
-
DC
-
Z
√
√
-
Cycle
1
1
1
1
1
1
1+N
1+N
2
ADC
ADC
ADD
ADD
B0ADD
ADD
SBC
SBC
SUB
SUB
SUB
DAA
A,M
M,A
A,M
M,A
M,A
A,I
A,M
M,A
A,M
M,A
A,I
A ← A + M + C, if occur carry, then C=1, else C=0
M ← A + M + C, if occur carry, then C=1, else C=0
A ← A + M, if occur carry, then C=1, else C=0
M ← A + M, if occur carry, then C=1, else C=0
M (bank 0) ← M (bank 0) + A, if occur carry, then C=1, else C=0
A ← A + I, if occur carry, then C=1, else C=0
A ← A - M - /C, if occur borrow, then C=0, else C=1
M ← A - M - /C, if occur borrow, then C=0, else C=1
A ← A - M, if occur borrow, then C=0, else C=1
M ← A - M, if occur borrow, then C=0, else C=1
A ← A - I, if occur borrow, then C=0, else C=1
To adjust ACC’s data format from HEX to DEC.
√
√
√
√
√
√
√
√
√
√
√
-
√
√
√
√
√
√
√
√
√
√
√
-
1
1+N
1
1+N
1+N
1
1
1+N
1
1+N
1
1
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
A,M
M,A
A,I
A,M
M,A
A,I
A,M
M,A
A,I
A ← A and M
M ← A and M
A ← A and I
A ← A or M
M ← A or M
A ← A or I
A ← A xor M
M ← A xor M
A ← A xor I
√
√
√
√
√
√
√
√
√
√
√
√
-
-
1
1+N
1
1
1+N
1
1
1+N
1
SWAP
SWAPM
RRC
RRCM
RLC
RLCM
CLR
BCLR
BSET
B0BCLR
B0BSET
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
A (b3~b0, b7~b4) ←M(b7~b4, b3~b0)
M(b3~b0, b7~b4) ← M(b7~b4, b3~b0)
A ← RRC M
M ← RRC M
A ← RLC M
M ← RLC M
M←0
M.b ← 0
M.b ← 1
M(bank 0).b ← 0
M(bank 0).b ← 1
√
√
√
√
-
-
√
√
√
√
√
√
√
√
√
-
CMPRS
CMPRS
INCS
INCMS
DECS
DECMS
BTS0
BTS1
B0BTS0
B0BTS1
JMP
CALL
A,I
A,M
M
M
M
M
M.b
M.b
M.b
M.b
d
d
ZF,C ← A - I, If A = I, then skip next instruction
ZF,C ← A – M, If A = M, then skip next instruction
A ← M + 1, If A = 0, then skip next instruction
M ← M + 1, If M = 0, then skip next instruction
A ← M - 1, If A = 0, then skip next instruction
M ← M - 1, If M = 0, then skip next instruction
If M.b = 0, then skip next instruction
If M.b = 1, then skip next instruction
If M(bank 0).b = 0, then skip next instruction
If M(bank 0).b = 1, then skip next instruction
PC15/14 ← RomPages1/0, PC13~PC0 ← d
Stack ← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d
√
√
-
-
√
√
-
1+S
1+S
1+ S
1+N+S
1+ S
1+N+S
1+S
1+S
1+S
1+S
2
2
-
-
2
2
2
1
M
RET
PC ← Stack
I
RETI
PC ← Stack, and to enable global interrupt
S
RETLW
PC ← Stack, and to load a value by PC+A
C
NOP
No operation
Note: “M” is register and memory. “S” is instruction cycle of next instruction. If “M” is system registers then “N” = 0, otherwise “N” = 1.
SONiX TECHNOLOGY CO., LTD
Page 63
1
1+N
1
1+N
1
1+N
1
1
1
1
1
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
10 ELECTRICAL CHARACTERISTIC
10.1 ABSOLUTE MAXIMUM RATING
Supply voltage (Vdd)………………………………………………………………………………………………… - 0.3V ~ 6.0V
Input in voltage (Vin)…………………………………………………………………………………… Vss – 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr)………………………………………………………………………… -20°C ~ + 70°C
Storage ambient temperature (Tstor) ………………………………………………………………………… –30°C ~ + 125°C
Power consumption(Pc)…………………………………………………………………………………………………… 500mW
10.2 ELECTRICAL CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 5.0V, fosc = 3.579545 MHz, ambient temperature is 25°C unless otherwise note.)
PARAMETER
SYM. DESCRIPTION
Operating voltage
Vdd
OTP programming voltage
RAM Data Retention voltage
Internal POR
Vpp
Vdr
Vpor
ViL1
ViL2
ViL3
ViL4
ViH1
ViH2
Input Low Voltage
Input High Voltage
Reset pin leakage current
I/O port pull-up resistor
I/O port input leakage current
All Port source current
sink current
INTn trigger pulse width
ViH3
ViH4
Ilekg
Rup
Ilekg
IoH
IoL
Tint0
Idd1
Idd2
Supply Current
Idd3
Idd4
LVD detect level
VLVD
MIN.
TYP.
MAX.
2.4
Vss
Vss
Vss
Vss
0.7Vdd
0.8Vdd
5.0
6.0
12.5
1.5
0.05
-
5.5
0.3Vdd
0.2Vdd
0.2Vdd
0.3Vdd
Vdd
Vdd
Reset pin ; Xin ( in RC mode )
0.9Vdd
Xin ( in X’tal mode )
0.7Vdd
Vin = Vdd
Vin = Vss , Vdd = 5V
Pull-up resistor disable, Vin = Vdd
Vop = Vdd – 0.5V
Vop = Vss + 0.5V
INT0 interrupt request pulse width
2/fcpu
Vdd= 5V 4Mhz
Run Mode, no loading
Vdd= 3V 4Mhz
(Low Power Disable)
Vdd= 3V
32768Hz
Vdd= 5V
Internal RC mode (16KHz)
Vdd= 3V
Vdd= 5V
Sleep Mode
Vdd= 3V
Vdd= 5V
Green Mode High Clock
Vdd= 3V
Vdd= 5V
Green Mode Low Clock
Vdd= 3V
Low voltage detect level
-
100
15
15
2.5
1
Vdd
Vdd
1
1
-
cycle
mA
mA
25
-
uA
25
5
0.50
0.30
0.50
0.15
15
3
1.8
-
uA
uA
uA
uA
mA
mA
uA
uA
V
Normal mode, Vpp = Vdd
Programming mode, Vpp = 12.5V
OTP programming voltage
Vdd rise rate to ensure internal power-on reset
All input pins except those specified below
Input with Schmitt trigger buffer
Reset pin ; Xin ( in RC mode )
Xin ( in X’tal mode )
All input pins except those specified below
Input with Schmitt trigger buffer
SONiX TECHNOLOGY CO., LTD
Page 64
-
UNIT
V
V
V
V/ms
V
V
V
V
V
V
V
V
uA
KΩ
uA
mA
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
11 PACKAGE INFORMATION
11.1 P-DIP 14 PIN
SYMBOLS
MIN
NOR
MAX
MIN
(inch)
A
A1
A2
D
E
E1
L
0.015
0.125
0.735
MAX
(mm)
0.210
0.135
0.775
0.381
3.175
18.669
0.245
0.115
0.130
0.075
0.300
0.250
0.130
0.255
0.150
ｅB
0.335
0.355
θ°
0°
7°
SONiX TECHNOLOGY CO., LTD
NOR
5.334
3.429
19.685
6.223
2.921
3.302
1.905
7.62
6.35
3.302
0.375
8.509
9.017
9.525
15°
0°
7°
15°
Page 65
6.477
3.810
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
11.2 SOP 14 PIN
SYMBOLS
A
A1
B
C
D
E
e
H
L
θ°
MIN
NOR
MAX
MIN
(inch)
0.058
0.004
0.013
0.0075
0.336
0.150
0.228
0.015
0°
SONiX TECHNOLOGY CO., LTD
0.064
0.016
0.008
0.341
0.154
0.050
0.236
0.025
-
NOR
MAX
(mm)
0.068
0.010
0.020
0.0098
0.344
0.157
0.244
0.050
8°
Page 66
1.4732
0.1016
0.3302
0.1905
8.5344
3.81
5.7912
0.381
0°
1.6256
0.4064
0.2032
8.6614
3.9116
1.27
5.9944
0.635
-
1.7272
0.254
0.508
0.2490
8.7376
3.9878
6.1976
1.27
8°
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
11.3 SSOP 16 PIN
SYMBOLS
A
A1
A2
b
b1
c
c1
D
E1
E
L
e
θ°
MIN
NOR
MAX
MIN
(inch)
0.053
0.004
0.008
0.008
0.007
0.007
0.189
0.150
0.228
0.016
0°
0.025 BASIC
-
SONiX TECHNOLOGY CO., LTD
NOR
MAX
(mm)
0.069
0.010
0.059
0.012
0.011
0.010
0.009
0.197
0.157
0.244
0.050
1.3462
0.1016
0.2032
0.2032
0.1778
0.1778
4.8006
3.81
5.7912
0.4064
8°
0°
Page 67
0.635 BASIC
-
1.7526
0.254
1.4986
0.3048
0.2794
0.254
0.2286
5.0038
3.9878
6.1976
1.27
8°
Preliminary Version 0.2
SN8P2501A
8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or
design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed,
intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a
situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such
unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries,
affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use
even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C.
Tel: 886-3-551 0520
Fax: 886-3-551 0523
Taipei Office:
Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C.
Tel: 886-2-2759 1980
Fax: 886-2-2759 8180
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Address: Flat 3 9/F Energy Plaza 92 Granville Road, Tsimshatsui East Kowloon.
Tel: 852-2723 8086
Fax: 852-2723 9179
Technical Support by Email:
[email protected]
SONiX TECHNOLOGY CO., LTD
Page 68
Preliminary Version 0.2