SONIX SN8A2617

SN8A2617
8-bit micro-controller MASK type with SIO function
SN8A2617
SIO INTERFACE
MASK TYPE MCU
USER’S MANUAL
Version 1.1
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
Page 1
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
AMENDENT HISTORY
Version
VER 1.0
VER 1.1
Date
May. 2006
Sep. 2006
Description
First issue
Modify LVD to two steps. LVD 2.0 and LVD 2.4V and controlled by code option.
LVD_L: LVD 2.0V, LVD_H: LVD 2.4V.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1.1
1.2
1.3
1.4
1.5
2
PRODUCT OVERVIEW................................................................................................................. 7
FEATURES ........................................................................................................................................ 7
SYSTEM BLOCK DIAGRAM .......................................................................................................... 8
PIN ASSIGNMENT ........................................................................................................................... 9
PIN DESCRIPTIONS....................................................................................................................... 10
PIN CIRCUIT DIAGRAMS ............................................................................................................ 11
CENTRAL PROCESSOR UNIT (CPU) ...................................................................................... 12
2.1
MEMORY MAP............................................................................................................................... 12
2.1.1
PROGRAM MEMORY (ROM) ................................................................................................. 12
2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 13
2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 14
2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 16
2.1.1.4 JUMP TABLE DESCRIPTION ........................................................................................... 18
2.1.1.5 CHECKSUM CALCULATION........................................................................................... 20
2.1.2
CODE OPTION TABLE ........................................................................................................... 21
2.1.3
DATA MEMORY (RAM)........................................................................................................... 22
2.1.4
SYSTEM REGISTER................................................................................................................. 22
2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 22
2.1.4.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 22
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER....................................................................... 23
2.1.4.4 ACCUMULATOR ............................................................................................................... 24
2.1.4.5 PROGRAM FLAG ............................................................................................................... 25
2.1.4.6 PROGRAM COUNTER....................................................................................................... 26
2.1.4.7 H, L REGISTERS................................................................................................................. 29
2.1.4.8 Y, Z REGISTERS................................................................................................................. 30
2.1.4.9 R REGISTERS ..................................................................................................................... 31
2.2
ADDRESSING MODE .................................................................................................................... 32
2.2.1
IMMEDIATE ADDRESSING MODE....................................................................................... 32
2.2.2
DIRECTLY ADDRESSING MODE .......................................................................................... 32
2.2.3
INDIRECTLY ADDRESSING MODE ...................................................................................... 32
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.3
STACK OPERATION ..................................................................................................................... 33
2.3.1
OVERVIEW .............................................................................................................................. 33
2.3.2
STACK REGISTERS ................................................................................................................. 34
2.3.3
STACK OPERATION EXAMPLE............................................................................................. 35
3
RESET ............................................................................................................................................. 36
3.1
OVERVIEW..................................................................................................................................... 36
3.2
POWER ON RESET ........................................................................................................................ 37
3.3
WATCHDOG RESET...................................................................................................................... 37
3.4
BROWN OUT RESET..................................................................................................................... 38
3.4.1
BROWN OUT DESCRIPTION ................................................................................................. 38
3.4.2
THE SYSTEM OPERATING VOLTAGE DECSRIPTION........................................................ 39
3.4.3
BROWN OUT RESET IMPROVEMENT.................................................................................. 39
3.5
EXTERNAL RESET........................................................................................................................ 41
3.6
EXTERNAL RESET CIRCUIT....................................................................................................... 41
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
4
Simply RC Reset Circuit ........................................................................................................... 41
Diode & RC Reset Circuit ........................................................................................................ 42
Zener Diode Reset Circuit ........................................................................................................ 42
Voltage Bias Reset Circuit........................................................................................................ 43
External Reset IC...................................................................................................................... 44
SYSTEM OPERATION MODE ................................................................................................... 45
4.1
OVERVIEW..................................................................................................................................... 45
4.2
SYSTEM MODE SWITCHING ...................................................................................................... 45
4.3
WAKEUP ......................................................................................................................................... 46
4.3.1
OVERVIEW .............................................................................................................................. 46
4.3.2
WAKEUP TIME........................................................................................................................ 46
4.3.3
P1W WAKEUP CONTROL REGISTER ................................................................................... 47
5
5.1
5.2
5.3
5.4
INTERRUPT................................................................................................................................... 48
OVERVIEW..................................................................................................................................... 48
INTEN INTERRUPT ENABLE REGISTER .................................................................................. 49
INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 50
GIE GLOBAL INTERRUPT OPERATION.................................................................................... 51
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
6
6.1
6.2
6.3
6.4
7
PUSH, POP ROUTINE .................................................................................................................... 52
INT0 (P0.0) INTERRUPT OPERATION ........................................................................................ 53
INT1 (P0.1) INTERRUPT OPERATION ........................................................................................ 54
INT2 (P0.2) INTERRUPT OPERATION ........................................................................................ 55
T0 INTERRUPT OPERATION ....................................................................................................... 56
TC0 INTERRUPT OPERATION .................................................................................................... 57
SIO INTERRUPT OPERATION ..................................................................................................... 58
MULTI-INTERRUPT OPERATION............................................................................................... 59
I/O PORT ........................................................................................................................................ 61
I/O PORT MODE............................................................................................................................. 61
I/O PULL UP REGISTER................................................................................................................ 62
I/O PORT DATA REGISTER ......................................................................................................... 63
I/O OPEN-DRAIN REGISTER........................................................................................................ 64
TIMERS .......................................................................................................................................... 65
7.1
WATCHDOG TIMER ..................................................................................................................... 65
7.2
TIMER 0 (T0)................................................................................................................................... 67
7.2.1
OVERVIEW .............................................................................................................................. 67
7.2.2
T0M MODE REGISTER........................................................................................................... 67
7.2.3
T0C COUNTING REGISTER................................................................................................... 68
7.2.4
T0 TIMER OPERATION SEQUENCE ..................................................................................... 69
7.3
TIMER/COUNTER 0 (TC0) ............................................................................................................ 70
7.3.1
OVERVIEW .............................................................................................................................. 70
7.3.2
TC0M MODE REGISTER ........................................................................................................ 71
7.3.3
TC0C COUNTING REGISTER ................................................................................................ 72
7.3.4
TC0 TIMER OPERATION SEQUENCE .................................................................................. 73
8
8.1
8.2
8.3
8.4
SERIAL INPUT/OUTPUT TRANSCEIVER (SIO) ................................................................... 74
OVERVIEW..................................................................................................................................... 74
SIOM MODE REGISTER ............................................................................................................... 76
SIOB DATA BUFFER..................................................................................................................... 77
SIOR REGISTER DESCRIPTION .................................................................................................. 77
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
9
10
INSTRUCTION TABLE ............................................................................................................... 80
10.1
10.2
ABSOLUTE MAXIMUM RATING................................................................................................ 81
STANDARD ELECTRICAL CHARACTERISTIC........................................................................ 81
11
12
12.1
ELECTRICAL CHARACTERISTIC .................................................................................. 81
DEVELOPMENT TOOL ...................................................................................................... 82
PACKAGE INFORMATION ............................................................................................... 83
QFP 44 PIN ...................................................................................................................................... 83
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
1
PRODUCT OVERVIEW
1.1 FEATURES
♦
Memory configuration
ROM size: 4K * 16 bits. (MAKS ROM)
RAM size: 256 * 8 bits.
♦
6 interrupt sources
Three internal interrupts: T0, TC0, SIO
Three external interrupts: INT0, INT1, INT2
♦
8 levels stack buffer.
♦
♦
♦
Fcpu: Fhosc/1, Fhosc/2, Fhosc/4 controlled by
code option.
Two 8-bit timer counters. (T0, TC0).
On chip watchdog timer and clock source is
Internal low clock RC type (16KHz @3V, 32KHz
@5V).
♦
I/O pin configuration
Bi-directional: P0, P1, P2, P4, P5
Programmable open-drain: P5.2
Wakeup: P0, P1 level change
Pull-up resisters: P0, P1, P2, P4, P5
External interrupt: P0.0, P0.1, P0.2
♦
SIO function.
♦
One system clocks
External high clock: RC type up to 10 MHz
External high clock: Crystal type up to 16 MHz
♦
Two operating modes
Normal mode: Both high and low clock active
Sleep mode: Both high and low clock stop
♦
Package (Chip form support)
QFP 44 pin
♦
Powerful instructions
One clocks per instruction cycle (1T)
Instruction’s length is one word.
Most of instructions are one cycle only.
All ROM area JMP instruction.
All ROM area lookup table function (MOVC)
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
1.2 SYSTEM BLOCK DIAGRAM
PC
MASK
IR
ROM
EXTERNAL
HIGH OSC.
INTERNAL
LOW RC
LVD
(Low Voltage Detector)
FLAGS
WATCHDOG TIMER
TIMING GENERATOR
ALU
RAM
ACC
SYSTEM REGISTERS
INTERRUPT
CONTROL
TIMER & COUNTER
P0
P1
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P2
Page 8
SIO TX/RX
P4
P5
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
1.3 PIN ASSIGNMENT
SONiX TECHNOLOGY CO., LTD
P5.3
P5.2/SO
P5.1/SI
P5.0/SCK
P2.4
P2.5
P2.6
P2.7
VSS
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33
32
31
30
29
28
27
26
25
24
23
P5.4
P5.5
P5.6
P5.7
P1.7
VDD
P0.4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P0.3
VSS
P2.3
P2.2
P2.1
P2.0
44 43 42 41 40 39 38 37 36 35 34
1 O
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
P1.0
P1.6
P0.0/INT0
P0.1/INT1
P0.2/INT2
RST
P1.5
P1.4
P1.3
VDD
P1.2
P1.1
XOUT/Fcpu
XIN
SN8P2707AQ (QFP44)
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
1.4 PIN DESCRIPTIONS
PIN NAME
VDD, VSS
TYPE
P
RST
I, P
XIN
I
XOUT/Fcpu
O
P0.0/INT0
I/O
P0[2:1]/INT[2:1]
I/O
P0[4:3]
I/O
P1[7:0]
I/O
P2[7:0]
I/O
P4[7:0]
I/O
P5.0/SCK
I/O
P5.1/SI
I/O
P5.2/SO
I/O
P5[7:3]
I/O
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DESCRIPTION
Power supply input pins for digital circuit.
RST is system external reset input pin.
Schmitt trigger structure, active “low”, normal stay to “high”.
XIN: Oscillator input pin.
XOUT: Oscillator output pin.
Fpcu: System clock output pin as RC mode.
P0.0: Port 0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
INT0: External interrupt input pin.
TC0 event counter input pin.
P0[2:1]: Port 0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
INT[2:1]: External interrupt input pin.
P0.3, P0.4: Port 0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
P1: Port 1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function controlled by P1W register.
P2: Port 2 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P4: Port 4 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P5.0: Port 5.0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
SIO: SIO clock pin.
P5.1: Port 5.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
SI: SIO data input pin.
P5.2: Port 5.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
SO: SIO data output pin. Programmable open-drain type controlled by P1OC register.
P5: Port 5 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
1.5 PIN CIRCUIT DIAGRAMS
Port P5.2 structure:
Pull-Up
PnM
PnM, PnUR
Input Bus
Pin
Output
Latch
Output Bus
Open-Drain
P1OC
Port 0, 1, 2, 4, 5 structure:
Pull-Up
PnM
PnM, PnUR
Input Bus
Pin
Output
Latch
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Output Bus
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2
CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
4K words ROM
ROM
0000H
0001H
.
.
0007H
0008H
0009H
.
.
000FH
0010H
0011H
.
.
.
.
.
FFBH
FFCH
FFDH
FFEH
FFFH
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Reset vector
User reset vector
Jump to user start address
General purpose area
Interrupt vector
User interrupt vector
User program
General purpose area
End of user program
Reserved
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.1.1
RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
Power On Reset (NT0=1, NPD=0).
Watchdog Reset (NT0=0, NPD=0).
External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
Example: Defining Reset Vector
ORG
JMP
…
0
START
ORG
10H
START:
…
…
ENDP
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; 0000H
; Jump to user program address.
; 0010H, The head of user program.
; User program
; End of program
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.1.2
INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG
JMP
…
0
START
; 0000H
; Jump to user program address.
ORG
PUSH
…
…
POP
RETI
…
8
; Interrupt vector.
; Save ACC and PFLAG register to buffers.
; Load ACC and PFLAG register from buffers.
; End of interrupt service routine
START:
…
…
JMP
…
; The head of user program.
; User program
START
ENDP
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; End of user program
; End of program
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG
JMP
…
ORG
JMP
0
START
; 0000H
; Jump to user program address.
8
MY_IRQ
; Interrupt vector.
; 0008H, Jump to interrupt service routine address.
ORG
10H
START:
…
…
…
JMP
…
; 0010H, The head of user program.
; User program.
START
MY_IRQ:
PUSH
…
…
POP
RETI
…
ENDP
; End of user program.
;The head of interrupt service routine.
; Save ACC and PFLAG register to buffers.
; Load ACC and PFLAG register from buffers.
; End of interrupt service routine.
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.1.3
LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
Example: To look up the ROM data located “TABLE1”.
@@:
TABLE1:
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INCMS
JMP
INCMS
NOP
Z
@F
Y
MOVC
…
DW
DW
DW
…
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
; Z+1
; Z is not overflow.
; Z overflow (FFH
00),
Y=Y+1
;
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
Example: INC_YZ macro.
INC_YZ
MACRO
INCMS
JMP
INCMS
NOP
Z
@F
; Z+1
; Not overflow
Y
; Y+1
; Not overflow
@@:
ENDM
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
Example: Modify above example by “INC_YZ” macro.
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INC_YZ
@@:
TABLE1:
MOVC
…
DW
DW
DW
…
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV
B0MOV
Y, #TABLE1$M
Z, #TABLE1$L
; To set lookup table’s middle address.
; To set lookup table’s low address.
B0MOV
B0ADD
A, BUF
Z, A
; Z = Z + BUF.
B0BTS1
JMP
INCMS
NOP
FC
GETDATA
Y
; Check the carry flag.
; FC = 0
; FC = 1. Y+1.
GETDATA:
;
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
MOVC
…
TABLE1:
DW
DW
DW
…
0035H
5105H
2012H
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; To define a word (16 bits) data.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.1.4
JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: Jump table.
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
JMP
JMP
JMP
JMP
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A
MACRO
IF
JMP
ORG
ENDIF
ADD
ENDM
VAL
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
($ | 0XFF)
($ | 0XFF)
PCL, A
Note: “VAL” is the number of the jump table listing number.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
Example: “@JMP_A” operation.
; Before compiling program.
ROM address
0X00FD
0X00FE
0X00FF
0X0100
0X0101
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
0X0100
0X0101
0X0102
0X0103
0X0104
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
SONiX TECHNOLOGY CO., LTD
Page 19
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.1.5
CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV
B0MOV
MOV
B0MOV
CLR
CLR
A,#END_USER_CODE$L
END_ADDR1, A
; Save low end address to end_addr1
A,#END_USER_CODE$M
END_ADDR2, A
; Save middle end address to end_addr2
Y
; Set Y to 00H
Z
; Set Z to 00H
MOVC
B0BSET
ADD
MOV
ADC
JMP
FC
DATA1, A
A, R
DATA2, A
END_CHECK
; Clear C flag
; Add A to Data1
INCMS
JMP
JMP
Z
@B
Y_ADD_1
; Z=Z+1
; If Z != 00H calculate to next address
; If Z = 00H increase Y
MOV
CMPRS
JMP
MOV
CMPRS
JMP
JMP
A, END_ADDR1
A, Z
AAA
A, END_ADDR2
A, Y
AAA
CHECKSUM_END
; If Yes, check if Y = middle end address
; If Not jump to checksum calculate
; If Yes checksum calculated is done.
INCMS
NOP
JMP
Y
; Increase Y
@B
; Jump to checksum calculate
@@:
; Add R to Data2
; Check if the YZ address =
the end of code
AAA:
END_CHECK:
; Check if Z = low end address
; If Not jump to checksum calculate
Y_ADD_1:
CHECKSUM_END:
…
…
END_USER_CODE:
SONiX TECHNOLOGY CO., LTD
; Label of program end
Page 20
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.2
CODE OPTION TABLE
Code Option
Content
RC
High_Clk
12M X’tal
Watch_Dog
Fcpu
LVD
4M X’tal
Always_On
Enable
Disable
Fhosc/1
Fhosc/2
Fhosc/4
LVD_L
LVD_H
SONiX TECHNOLOGY CO., LTD
Function Description
Low cost RC for external high clock oscillator and XOUT becomes to
Fcpu frequency output pin.
High speed crystal /resonator (e.g. 12MHz) for external high clock
oscillator.
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Watchdog timer is always on enable even in power down mode.
Enable watchdog timer. Watchdog timer stops in power down mode.
Disable Watchdog function.
Instruction cycle is oscillator clock.
Instruction cycle is 2 oscillator clocks.
Instruction cycle is 4 oscillator clocks.
LVD will reset chip if VDD id below 2.0V.
LVD will reset chip if VDD id below 2.4V.
Page 21
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.3 DATA MEMORY (RAM)
256 X 8-bit RAM
BANK 0
BANK 1
RAM location
Address
000h
“
“
“
“
“
07Fh
080h
“
“
“
“
“
0FFh
100h
“
“
“
“
“
17Fh
000h~07Fh of Bank 0 = To store
general purpose data (128 bytes).
General purpose area
080h~0FFh of Bank 0 store system
registers (128 bytes).
System register
End of bank 0 area
100h~17Fh of Bank 1 = To store
general purpose data (128 bytes).
General purpose area
End of bank 1 area
2.1.4 SYSTEM REGISTER
2.1.4.1
SYSTEM REGISTER TABLE
0
1
L
H
8
9
A
B
P1M
C P1W
P1
D P0
P0UR
P1UR
E
F STK7L STK7H
2.1.4.2
L, H =
PFLAG =
SIOM =
SIOB =
P1OC =
PnM =
INTRQ =
OSCM =
T0M =
T0C =
STKP =
@HL =
2
3
4
5
6
7
8
9
A
B
C
D
E
F
R
Z
Y
-
PFLAG
RBANK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIOM
SIOR
SIOB
-
P0M
-
-
-
-
-
-
PEDGE
P2M
-
P4M
P5M
-
-
P2
-
P4
P5
-
-
P2UR
-
P4UR
P5UR
@HL
STK6L STK6H STK5L STK5H STK4L
INTRQ INTEN
OSCM
-
WDTR
-
PCL
PCH
T0M
T0C
TC0M
TC0C
-
-
-
STKP
-
P1OC
-
-
-
-
-
-
@YZ
STK4H
STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
SYSTEM REGISTER DESCRIPTION
Working & @HL addressing register.
ROM page and special flag register.
SIO mode control register.
SIO’s data buffer.
P5.2 open-drain control register.
Port n input/output mode register.
Interrupts’ request register.
Oscillator mode register.
Timer 0 mode register.
Timer 0 counting register.
Stack pointer buffer.
RAM HL indirect addressing index pointer.
SONiX TECHNOLOGY CO., LTD
R=
Y, Z =
RBANK =
SIOR =
P1W =
Pn =
INTEN =
PCH, PCL =
TC0M =
TC0C =
STK0~STK7 =
@YZ =
Page 22
Working register and ROM lookup data buffer.
Working, @YZ and ROM addressing register.
RAM Bank Select register.
SIO’s clock reload buffer.
Port 1 wakeup register.
Port n data buffer.
Interrupts’ enable register.
Program counter.
Timer/Counter 0 mode register.
Timer/Counter 0 counting register.
Stack 0 ~ stack 7 buffer.
RAM YZ indirect addressing index pointer.
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.4.3
Address
080H
081H
082H
083H
084H
086H
087H
0B4H
0B5H
0B6H
0B8H
0BFH
0C0H
0C1H
0C2H
0C4H
0C5H
0C8H
0C9H
0CAH
0CCH
0CEH
0CFH
0D0H
0D1H
0D2H
0D4H
0D5H
0D8H
0D9H
0DAH
0DBH
0DFH
0E0H
0E1H
0E2H
0E4H
0E5H
0E6H
0E7H
0E9H
0F0H
0F1H
0F2H
0F3H
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
0FFH
BIT DEFINITION of SYSTEM REGISTER
Bit7
LBIT7
HBIT7
RBIT7
ZBIT7
YBIT7
NT0
SENB
SIOR7
SIOB7
P17W
P17M
P27M
P47M
P57M
WDTR7
PC7
P17
P27
P47
P57
T0ENB
T0C7
TC0ENB
TC0C7
GIE
P17R
P27R
P47R
P57R
@HL7
@YZ7
S7PC7
S6PC7
S5PC7
S4PC7
S3PC7
S2PC7
S1PC7
S0PC7
-
Bit6
LBIT6
HBIT6
RBIT6
ZBIT6
YBIT6
NPD
START
SIOR6
SIOB6
P16W
P16M
P26M
P46M
P56M
WDTR6
PC6
P16
P26
P46
P56
T0rate2
T0C6
TC0rate2
TC0C6
P16R
P26R
P46R
P56R
@HL6
@YZ6
S7PC6
S6PC6
S5PC6
S4PC6
S3PC6
S2PC6
S1PC6
S0PC6
-
Bit5
LBIT5
HBIT5
RBIT5
ZBIT5
YBIT5
SRATE1
SIOR5
SIOB5
P15W
P15M
P25M
P45M
P55M
TC0IRQ
TC0IEN
WDTR5
PC5
P15
P25
P45
P55
T0rate1
T0C5
TC0rate1
TC0C5
P15R
P25R
P45R
P54R
@HL5
@YZ5
S7PC5
S6PC5
S5PC5
S4PC5
S3PC5
S2PC5
S1PC5
S0PC5
-
Bit4
LBIT4
HBIT4
RBIT4
ZBIT4
YBIT4
SRATE0
SIOR4
SIOB4
P04M
P00G1
Bit3
LBIT3
HBIT3
RBIT3
ZBIT3
YBIT3
0
SIOR3
SIOB3
P03M
P00G0
Bit2
LBIT2
HBIT2
RBIT2
ZBIT2
YBIT2
C
SCKMD
SIOR2
SIOB2
P02M
-
Bit1
LBIT1
HBIT1
RBIT1
ZBIT1
YBIT1
DC
SEDGE
SIOR1
SIOB1
P01M
-
Bit0
LBIT0
HBIT0
RBIT0
ZBIT0
YBIT0
Z
RBNKS0
TXRX
SIOR0
SIOB0
P00M
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
Remarks
L
H
R
Z
Y
PFLAG
RBANK
SIOM mode register
SIOR reload buffer
SIOB data buffer
P0M
PEDGE
P14W
P14M
P24M
P44M
P54M
T0IRQ
T0IEN
CPUM1
WDTR4
PC4
P04
P14
P24
P44
P54
T0rate0
T0C4
TC0rate0
TC0C4
P04R
P14R
P24R
P44R
P54R
@HL4
@YZ4
S7PC4
S6PC4
S5PC4
S4PC4
S3PC4
S2PC4
S1PC4
S0PC4
-
P13W
P13M
P23M
P43M
P53M
SIOIRQ
SIOIEN
CPUM0
WDTR3
PC3
PC11
P03
P13
P23
P43
P53
T0C3
TC0CKS
TC0C3
P03R
P13R
P23R
P43R
P53R
@HL3
@YZ3
S7PC3
S7PC11
S6PC3
S6PC11
S5PC3
S5PC11
S4PC3
S4PC11
S3PC3
S3PC11
S2PC3
S2PC11
S1PC3
S1PC11
S0PC3
S0PC11
P12W
P12M
P22M
P42M
P52M
P02IRQ
P02IEN
WDTR2
PC2
PC10
P02
P12
P22
P42
P52
T0C2
TC0C2
STKPB2
P02R
P12R
P22R
P42R
P52R
@HL2
@YZ2
P52OC
S7PC2
S7PC10
S6PC2
S6PC10
S5PC2
S5PC10
S4PC2
S4PC10
S3PC2
S3PC10
S2PC2
S2PC10
S1PC2
S1PC10
S0PC2
S0PC10
P11W
P11M
P21M
P41M
P51M
P01IRQ
P01IEN
STPHX
WDTR1
PC1
PC9
P01
P11
P21
P41
P51
T0C1
TC0C1
STKPB1
P01R
P11R
P21R
P41R
P51R
@HL1
@YZ1
S7PC1
S7PC9
S6PC1
S6PC9
S5PC1
S5PC9
S4PC1
S4PC9
S3PC1
S3PC9
S2PC1
S2PC9
S1PC1
S1PC9
S0PC1
S0PC9
P10W
P10M
P20M
P40M
P50M
P00IRQ
P00IEN
WDTR0
PC0
PC8
P00
P10
P20
P40
P50
T0C0
TC0C0
STKPB0
P00R
P10R
P20R
P40R
P50R
@HL0
@YZ0
S7PC0
S7PC8
S6PC0
S6PC8
S5PC0
S5PC8
S4PC0
S4PC8
S3PC0
S3PC8
S2PC0
S2PC8
S1PC0
S1PC8
S0PC0
S0PC8
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1W wakeup register
P1M I/O direction
P2M I/O direction
P4M I/O direction
P5M I/O direction
INTRQ
INTEN
OSCM
WDTR
PCL
PCH
P0 data buffer
P1 data buffer
P2 data buffer
P4 data buffer
P5 data buffer
T0M
T0C
TC0M
TC0C
STKP stack pointer
P0UR
P1UR
P2UR
P4UR
P5UR
@HL index pointer
@YZ index pointer
P1OC
STK7L
STK7H
STK6L
STK6H
STK5L
STK5H
STK4L
STK4H
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
Note:
1. To avoid system error, make sure to put all the “0” and “1” as it indicates in the above table.
2. All of register names had been declared in SN8ASM assembler.
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code.
4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.
SONiX TECHNOLOGY CO., LTD
Page 23
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.4.4
ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
Example: Read and write ACC value.
; Read ACC data and store in BUF data memory.
MOV
BUF, A
; Write a immediate data into ACC.
MOV
A, #0FH
; Write ACC data from BUF data memory.
MOV
A, BUF
B0MOV
A, BUF
; or
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories. “PUSH”, “POP” save and load ACC, PFLAG data into buffers.
Example: Protect ACC and working registers.
INT_SERVICE:
PUSH
…
…
POP
; Save ACC and PFLAG to buffers.
.
RETI
SONiX TECHNOLOGY CO., LTD
; Load ACC and PFLAG from buffers.
; Exit interrupt service vector
Page 24
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.4.5
PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and
watchdog reset. C, DC, Z bits indicate the result status of ALU operation.
086H
PFLAG
Read/Write
After reset
Bit [7:6]
Bit 7
NT0
R/W
-
Bit 6
NPD
R/W
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
NT0, NPD: Reset status flag.
NT0
0
0
1
1
NPD
0
1
0
1
Reset Status
Watch-dog time out
Reserved
Reset by LVD
Reset by external Reset Pin
Bit 2
C: Carry flag
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result
≥ 0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison
result < 0.
Bit 1
DC: Decimal carry flag
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.
Bit 0
Z: Zero flag
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
SONiX TECHNOLOGY CO., LTD
Page 25
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.4.6
PROGRAM COUNTER
The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 11.
PC
After
reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
PC11 PC10 PC9
-
-
-
-
0
0
0
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
0
0
0
0
0
0
0
0
0
PCH
PCL
ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
FC
C0STEP
; To skip, if Carry_flag = 1
; Else jump to C0STEP.
C0STEP:
B0BTS1
JMP
…
…
NOP
A, BUF0
FZ
C1STEP
; Move BUF0 value to ACC.
; To skip, if Zero flag = 0.
; Else jump to C1STEP.
C1STEP:
B0MOV
B0BTS0
JMP
…
…
NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
C0STEP:
CMPRS
JMP
…
…
NOP
A, #12H
C0STEP
SONiX TECHNOLOGY CO., LTD
; To skip, if ACC = 12H.
; Else jump to C0STEP.
Page 26
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
C0STEP:
INCS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
INCMS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
INCMS instruction:
C0STEP:
If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next
instruction.
DECS instruction:
C0STEP:
DECS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
DECMS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
DECMS instruction:
C0STEP:
SONiX TECHNOLOGY CO., LTD
Page 27
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and don’t care PCL overflow problem.
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: If PC = 0323H
(PCH = 03H, PCL = 23H)
; PC = 0323H
MOV
B0MOV
…
A, #28H
PCL, A
; Jump to address 0328H
MOV
B0MOV
…
A, #00H
PCL, A
; Jump to address 0300H
; PC = 0328H
Example: If PC = 0323H
(PCH = 03H, PCL = 23H)
; PC = 0323H
B0ADD
JMP
JMP
JMP
JMP
…
…
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
SONiX TECHNOLOGY CO., LTD
; PCL = PCL + ACC, the PCH cannot be changed.
; If ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
Page 28
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.4.7
H, L REGISTERS
The H and L registers are the 8-bit buffers. There are two major functions of these registers.
can be used as general working registers
can be used as RAM data pointers with @HL register
081H
H
Read/Write
After reset
Bit 7
HBIT7
R/W
X
Bit 6
HBIT6
R/W
X
Bit 5
HBIT5
R/W
X
Bit 4
HBIT4
R/W
X
Bit 3
HBIT3
R/W
X
Bit 2
HBIT2
R/W
X
Bit 1
HBIT1
R/W
X
Bit 0
HBIT0
R/W
X
080H
L
Read/Write
After reset
Bit 7
LBIT7
R/W
X
Bit 6
LBIT6
R/W
X
Bit 5
LBIT5
R/W
X
Bit 4
LBIT4
R/W
X
Bit 3
LBIT3
R/W
X
Bit 2
LBIT2
R/W
X
Bit 1
LBIT1
R/W
X
Bit 0
LBIT0
R/W
X
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode
to access data as following.
B0MOV
B0MOV
B0MOV
H, #00H
L, #20H
A, @HL
; To set RAM bank 0 for H register
; To set location 20H for L register
; To read a data into ACC
Example: Clear general-purpose data memory area of bank 0 using @HL register.
CLR
B0MOV
H
L, #07FH
; H = 0, bank 0
; L = 7FH, the last address of the data memory area
CLR
DECMS
JMP
@HL
L
CLR_HL_BUF
; Clear @HL to be zero
; L – 1, if L = 0, finish the routine
; Not zero
CLR
@HL
CLR_HL_BUF:
END_CLR:
; End of clear general purpose data memory area of bank 0
…
…
SONiX TECHNOLOGY CO., LTD
Page 29
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.4.8
Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
can be used as general working registers
can be used as RAM data pointers with @YZ register
can be used as ROM data pointer with the MOVC instruction for look-up table
084H
Y
Read/Write
After reset
Bit 7
YBIT7
R/W
-
Bit 6
YBIT6
R/W
-
Bit 5
YBIT5
R/W
-
Bit 4
YBIT4
R/W
-
Bit 3
YBIT3
R/W
-
Bit 2
YBIT2
R/W
-
Bit 1
YBIT1
R/W
-
Bit 0
YBIT0
R/W
-
083H
Z
Read/Write
After reset
Bit 7
ZBIT7
R/W
-
Bit 6
ZBIT6
R/W
-
Bit 5
ZBIT5
R/W
-
Bit 4
ZBIT4
R/W
-
Bit 3
ZBIT3
R/W
-
Bit 2
ZBIT2
R/W
-
Bit 1
ZBIT1
R/W
-
Bit 0
ZBIT0
R/W
-
Example:
Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV
B0MOV
B0MOV
Example:
Y, #00H
Z, #25H
A, @YZ
; To set RAM bank 0 for Y register
; To set location 25H for Z register
; To read a data into ACC
Uses the Y, Z register as data pointer to clear the RAM data.
B0MOV
B0MOV
Y, #0
Z, #07FH
; Y = 0, bank 0
; Z = 7FH, the last address of the data memory area
CLR
@YZ
; Clear @YZ to be zero
DECMS
JMP
Z
CLR_YZ_BUF
; Z – 1, if Z= 0, finish the routine
; Not zero
CLR
@YZ
CLR_YZ_BUF:
END_CLR:
; End of clear general purpose data memory area of bank 0
…
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
2.1.4.9
R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register.
Can be used as working register
For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H
R
Read/Write
After reset
Bit 7
RBIT7
R/W
-
Bit 6
RBIT6
R/W
-
Bit 5
RBIT5
R/W
-
Bit 4
RBIT4
R/W
-
Bit 3
RBIT3
R/W
-
Bit 2
RBIT2
R/W
-
Bit 1
RBIT1
R/W
-
Bit 0
RBIT0
R/W
-
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
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8-bit micro-controller MASK type with SIO function
2.2 ADDRESSING MODE
2.2.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
Example: Move the immediate data 12H to ACC.
MOV
A, #12H
; To set an immediate data 12H into ACC.
Example: Move the immediate data 12H to R register.
B0MOV
R, #12H
; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
2.2.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
Example: Move 0x12 RAM location data into ACC.
B0MOV
A, 12H
; To get a content of RAM location 0x12 of bank 0 and save in
ACC.
Example: Move ACC data into 0x12 RAM location.
B0MOV
12H, A
; To get a content of ACC and save in RAM location 12H of
bank 0.
2.2.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (H/L, Y/Z).
Example: Indirectly addressing mode with @HL register
B0MOV
B0MOV
B0MOV
H, #0
L, #12H
A, @HL
; To clear H register to access RAM bank 0.
; To set an immediate data 12H into L register.
; Use data pointer @HL reads a data from RAM location
; 012H into ACC.
Example: Indirectly addressing mode with @YZ register
B0MOV
B0MOV
B0MOV
Y, #0
Z, #12H
A, @YZ
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; To clear Y register to access RAM bank 0.
; To set an immediate data 12H into Z register.
; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
Page 32
Version 1.1
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8-bit micro-controller MASK type with SIO function
2.3 STACK OPERATION
2.3.1 OVERVIEW
The stack buffer has 8-level. These buffers are designed to push and pop up program counter’s (PC) data when
interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active
level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program
counter (PC) data.
RET /
RETI
STKP + 1
CALL /
INTERRUPT
STKP - 1
PCH
PCL
STACK Level
STACK Buffer
High Byte
STACK Buffer
Low Byte
STKP = 7
STK7H
STK7L
STKP = 6
STK6H
STK6L
STKP = 5
STK5H
STKP
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STK5L
STKP
STKP = 4
STK4H
STK4L
STKP = 3
STK3H
STK3L
STKP = 2
STK2H
STK2L
STKP = 1
STK1H
STK1L
STKP = 0
STK0H
STK0L
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Version 1.1
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8-bit micro-controller MASK type with SIO function
2.3.2 STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 12-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push
operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to
the top address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0DFH
STKP
Read/Write
After reset
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit[2:0]
STKPBn: Stack pointer (n = 0 ~ 2)
Bit 7
GIE: Global interrupt control bit.
0 = Disable.
1 = Enable. Please refer to the interrupt chapter.
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointer in the
beginning of the program.
MOV
B0MOV
A, #00000111B
STKP, A
0F0H~0FFH
STKnH
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
SnPC11
R/W
0
Bit 2
SnPC10
R/W
0
Bit 1
SnPC9
R/W
0
Bit 0
SnPC8
R/W
0
0F0H~0FFH
STKnL
Read/Write
After reset
Bit 7
SnPC7
R/W
0
Bit 6
SnPC6
R/W
0
Bit 5
SnPC5
R/W
0
Bit 4
SnPC4
R/W
0
Bit 3
SnPC3
R/W
0
Bit 2
SnPC2
R/W
0
Bit 1
SnPC1
R/W
0
Bit 0
SnPC0
R/W
0
STKn = STKnH , STKnL (n = 7 ~ 0)
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8-bit micro-controller MASK type with SIO function
2.3.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
0
1
2
3
4
5
6
7
8
>8
STKPB2
STKP Register
STKPB1
STKPB0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
Stack Buffer
High Byte Low Byte
Free
STK0H
STK1H
STK2H
STK3H
STK4H
STK5H
STK6H
STK7H
-
Free
STK0L
STK1L
STK2L
STK3L
STK4L
STK5L
STK6L
STK7L
-
Description
Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
8
7
6
5
4
3
2
1
0
STKPB2
STKP Register
STKPB1
STKPB0
1
0
0
0
0
1
1
1
1
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1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Stack Buffer
High Byte Low Byte
STK7H
STK6H
STK5H
STK4H
STK3H
STK2H
STK1H
STK0H
Free
Page 35
STK7L
STK6L
STK5L
STK4L
STK3L
STK2L
STK1L
STK0L
Free
Description
-
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
3
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
Power on reset
Watchdog reset
Brown out reset
External reset
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H
PFLAG
Read/Write
After reset
Bit [7:6]
Bit 7
NT0
R/W
-
Bit 6
NPD
R/W
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
NT0, NPD: Reset status flag.
NT0
0
0
1
1
NPD
0
1
0
1
Condition
Watchdog reset
Reserved
Power on reset and LVD reset.
External reset
Description
Watchdog timer overflow.
Power voltage is lower than LVD detecting level.
External reset pin detect low level status.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
VDD
Power
LVD Detect Level
VSS
VDD
External Reset
VSS
External Reset
Low Detect
External Reset
High Detect
Watchdog
Overflow
Watchdog Normal Run
Watchdog Reset
Watchdog Stop
System Normal Run
System Status
System Stop
Power On
Delay Time
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External
Reset Delay
Time
Page 36
Watchdog
Reset Delay
Time
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising
curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.
Power-up: System detects the power voltage up and waits for power stable.
External reset: System checks external reset pin status. If external reset pin is not high level, the system keeps
reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.
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8-bit micro-controller MASK type with SIO function
3.4 BROWN OUT RESET
3.4.1 BROWN OUT DESCRIPTION
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external
factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well
or executing program error.
VDD
System Work
Well Area
V1
V2
V3
System Work
Error Area
VSS
Brown Out Reset Diagram
The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power
range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset
diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate
the system working area. The above area is the system work well area. The below area is the system work error area
called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the
below area and may induce the system error occurrence. Let system under dead-band includes some conditions.
DC application:
The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,
the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system
reset voltage. That makes the system under dead-band.
AC application:
In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC
noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating
induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power
situation.
The power on duration and power down duration are longer in AC application. The system power on sequence protects
the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power,
the VDD drops slowly and through the dead-band for a while.
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8-bit micro-controller MASK type with SIO function
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system
executing rate and power level. Different system executing rates have different system minimum operating voltage.
The electrical characteristic section shows the system voltage to executing rate relationship.
System Mini.
Operating Voltage.
Vdd (V)
Normal Operating
Area
Dead-Band Area
Reset Area
System Reset
Voltage.
System Rate (Fcpu)
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
3.4.3 BROWN OUT RESET IMPROVEMENT
How to improve the brown reset condition? There are some methods to improve brown out reset as following.
LVD reset
Watchdog reset
Reduce the system executing rate
External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)
Note:
1. The “ Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can
completely improve the brown out reset, DC low battery and AC slow power down conditions.
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips)
and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset
IC”). The structure can improve noise effective and get good EFT characteristic.
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8-bit micro-controller MASK type with SIO function
LVD reset:
VDD
Power
LVD Detect Voltage
VSS
Power is below LVD Detect
Voltage and System Reset.
System Normal Run
System Status
System Stop
Power On
Delay Time
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the
watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method
also can improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful
and the system stays in reset status until the power return to normal range.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External
reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
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8-bit micro-controller MASK type with SIO function
3.5 EXTERNAL RESET
External reset pin is Schmitt Trigger structure and low level active. The system is running when reset pin is high level
voltage input. The reset pin receives the low voltage and the system is reset. The external reset operation actives in
power on and normal running mode. During system power-up, the external reset pin must be high level input, or the
system keeps in reset status. External reset sequence is as following.
External reset: System checks external reset pin status. If external reset pin is not high level, the system keeps
reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
The external reset can reset the system during power on duration, and good external reset circuit can protect the
system to avoid working at unusual power condition, e.g. brown out reset in AC power application…
3.6 EXTERNAL RESET CIRCUIT
3.6.1 Simply RC Reset Circuit
VDD
R1
47K ohm
R2
RST
100 ohm
MCU
C1
0.1uF
VSS
VCC
GND
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into
reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from
the timing difference.
Note: The reset circuit is no any protection against unusual power or brown out reset.
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SN8A2617
8-bit micro-controller MASK type with SIO function
3.6.2 Diode & RC Reset Circuit
VDD
R1
47K ohm
DIODE
R2
RST
MCU
100 ohm
C1
0.1uF
VSS
VCC
GND
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal.
The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct
higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can
improve slight brown out reset condition.
Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to
limit any current flowing into reset pin from external capacitor C in the event of reset pin
breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
3.6.3 Zener Diode Reset Circuit
VDD
R1
33K ohm
E
R2
B
10K ohm
Vz
Q1
C
RST
MCU
R3
40K ohm
VSS
VCC
GND
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition
completely. Use zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of
the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of
the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener
specification. Select the right zener voltage to conform the application.
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SN8A2617
8-bit micro-controller MASK type with SIO function
3.6.4 Voltage Bias Reset Circuit
VDD
R1
47K ohm
E
B
Q1
C
R2
10K ohm
RST
MCU
R3
2K ohm
VSS
VCC
GND
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely.
The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When
VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high
voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor
outputs low voltage and MCU is in reset mode.
Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the
circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is
0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the
reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias
reset circuit” can protects system no any error occurrence as power dropping. When power drops
below the reset detect voltage, the system reset would be triggered, and then system executes
reset sequence. That makes sure the system work well under unstable power situation.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
3.6.5 External Reset IC
VDD
VDD
Bypass
Capacitor
0.1uF
Reset
IC
RST
RST
MCU
VSS
VSS
VCC
GND
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
4
SYSTEM OPERATION MODE
4.1 OVERVIEW
The chip is featured with low power consumption by switching around two different modes as following.
Normal mode (High-speed mode)
Power-down mode (Sleep mode)
Normal Mode
P0, P1 Wake-up Function Active.
External Reset Circuit Active.
CPUM0 = 1
Power Down Mode
(Sleep Mode)
System Mode Switching Diagram
Operating mode description
MODE
POWER
DOWN
(SLEEP)
Running
Stop
Executing
Stop
*Active
Inactive
*Active
Inactive
By Watch_Dog By Watch_Dog
Code option
Code option
P0, P1, Reset
REMARK
NORMAL
EHOSC
CPU instruction
T0 timer
TC0 timer
Watchdog timer
Wakeup source
* Active if T0ENB=1
* Active if TC0ENB=1
Refer to code option
description
EHOSC: External high clock
4.2 SYSTEM MODE SWITCHING
Example: Switch normal/slow mode to power down (sleep) mode.
BSET
FCPUM0
; Set CPUM0 = 1.
Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
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4.3 WAKEUP
4.3.1 OVERVIEW
Under power down mode (sleep mode) , program doesn’t execute. The wakeup trigger can wake the system up to
normal mode. The wakeup trigger sources are external trigger (P0, P1 level change)
Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change)
4.3.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit.
After the wakeup time, the system goes into the normal mode.
The value of the wakeup time is as the following.
The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system
goes into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz)
The total wakeup time = 0.512 ms + oscillator start-up time
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4.3.3 P1W WAKEUP CONTROL REGISTER
Under power down mode (sleep mode) and green mode, the I/O ports with wakeup function are able to wake the
system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but
the Port 1 is controlled by the P1W register.
0C0H
P1W
Read/Write
After reset
Bit[7:0]
Bit 7
P17W
W
0
Bit 6
P16W
W
0
Bit 5
P15W
W
0
Bit 4
P14W
W
0
Bit 3
P13W
W
0
Bit 2
P12W
W
0
Bit 1
P11W
W
0
Bit 0
P10W
W
0
P10W~P17W: Port 1 wakeup function control bits.
0 = Disable P1n wakeup function.
1 = Enable P1n wakeup function.
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5
INTERRUPT
5.1 OVERVIEW
This MCU provides six interrupt sources, including three internal interrupt (T0/TC0 /SIO) and three external interrupt
(INT0/INT1/INT2). The external interrupt can wakeup the chip while the system is switched from power down mode to
high-speed normal mode, and interrupt request is latched until return to normal mode. Once interrupt service is
executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt request. On the contrast, when
interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All of the interrupt request signals
are stored in INTRQ register.
INTEN Interrupt Enable Register
P00IRQ
INT0 Trigger
INT1 Trigger
INT2 Trigger
T0 Time Out
TC0 Time Out
Interrupt Vector Address (0008H)
P01IRQ
INTRQ
P02IRQ
Interrupt
2-Bit
T0IRQ
Enable
Latchs
TC0IRQ
Gating
SIO Process End
Global Interrupt Request Signal
SIOIRQ
Note: The GIE bit must enable during all interrupt operation.
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5.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including three internal interrupts, three external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C9H
INTEN
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
TC0IEN
R/W
0
Bit 4
T0IEN
R/W
0
Bit 0
P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
Bit 1
P01IEN: External P0.1 interrupt (INT1) control bit.
0 = Disable INT1 interrupt function.
1 = Enable INT1 interrupt function.
Bit 2
P02IEN: External P0.2 interrupt (INT2) control bit.
0 = Disable INT1 interrupt function.
1 = Enable INT1 interrupt function.
Bit 3
SIOIEN: SIO interrupt control bit.
0 = Disable SIO interrupt function.
1 = Enable SIO interrupt function.
Bit 4
T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
Bit 5
TC0IEN: TC0 timer interrupt control bit.
0 = Disable TC0 interrupt function.
1 = Enable TC0 interrupt function.
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Bit 3
SIOIEN
R/W
0
Bit 2
P02IEN
R/W
0
Bit 1
P01IEN
R/W
0
Bit 0
P00IEN
R/W
0
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5.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
0C8H
INTRQ
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
TC0IRQ
R/W
0
Bit 4
T0IRQ
R/W
0
Bit 0
P00IRQ: External P0.0 interrupt (INT0) request flag.
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
Bit 1
P01IRQ: External P0.1 interrupt (INT1) request flag.
0 = None INT1 interrupt request.
1 = INT1 interrupt request.
Bit 2
P02IRQ: External P0.2 interrupt (INT2) request flag.
0 = None INT1 interrupt request.
1 = INT1 interrupt request.
Bit 3
SIOIRQ: SIO interrupt request flag.
0 = None SIO interrupt request.
1 = SIO interrupt request.
Bit 4
T0IRQ: T0 timer interrupt request flag.
0 = None T0 interrupt request.
1 = T0 interrupt request.
Bit 5
TC0IRQ: TC0 timer interrupt request flag.
0 = None TC0 interrupt request.
1 = TC0 interrupt request.
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Bit 3
SIOIRQ
R/W
0
Bit 2
P02IRQ
R/W
0
Bit 1
P01IRQ
R/W
0
Bit 0
P00IRQ
R/W
0
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5.4 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
0DFH
STKP
Read/Write
After reset
Bit 7
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
GIE: Global interrupt control bit.
0 = Disable global interrupt.
1 = Enable global interrupt.
Example: Set global interrupt control bit (GIE).
B0BSET
FGIE
; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
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5.5 PUSH, POP ROUTINE
When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save
ACC, PFLAG data. The chip includes “PUSH”, “POP” for in/out interrupt service routine. The two instruction save and
load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is
an unique buffer and only one level.
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine
executed.
ORG
JMP
0
START
ORG
JMP
8
INT_SERVICE
ORG
10H
START:
…
INT_SERVICE:
PUSH
…
…
POP
; Save ACC and PFLAG to buffers.
RETI
…
ENDP
; Exit interrupt service vector
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; Load ACC and PFLAG from buffers.
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5.6 INT0 (P0.0) INTERRUPT OPERATION
When the INT0 trigger occurs, the P00IRQ will be set to “1” no matter the P00IEN is enable or disable. If the P00IEN =
1 and the trigger event P00IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG
8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt
vector even when the P00IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt
situation.
Note: The interrupt trigger direction of P0.0 is control by PEDGE register.
0BFH
PEDGE
Read/Write
After reset
Bit[4:3]
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P00G1
R/W
1
Bit 3
P00G0
R/W
0
Bit 2
-
Bit 1
-
Bit 0
-
P00G[1:0]: P0.0 interrupt trigger edge control bits.
00 = reserved.
01 = rising edge.
10 = falling edge.
11 = rising/falling bi-direction (Level change trigger).
Example: Setup INT0 interrupt request and bi-direction edge trigger.
MOV
B0MOV
A, #18H
PEDGE, A
; Set INT0 interrupt trigger as bi-direction edge.
B0BSET
B0BCLR
B0BSET
FP00IEN
FP00IRQ
FGIE
; Enable INT0 interrupt service
; Clear INT0 interrupt request flag
; Enable GIE
Example: INT0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FP00IRQ
EXIT_INT
; Check P00IRQ
; P00IRQ = 0, exit interrupt vector
B0BCLR
…
…
FP00IRQ
; Reset P00IRQ
; INT0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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5.7 INT1 (P0.1) INTERRUPT OPERATION
When the INT1 trigger occurs, the P01IRQ will be set to “1” no matter the P01IEN is enable or disable. If the P01IEN =
1 and the trigger event P01IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG
8). If the P01IEN = 0 and the trigger event P01IRQ is still set to be “1”. Moreover, the system won’t execute interrupt
vector even when the P01IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt
situation.
Note: The interrupt trigger direction of P0.1 is falling edge.
Example: INT1 interrupt request setup.
B0BSET
B0BCLR
B0BSET
FP01IEN
FP01IRQ
FGIE
; Enable INT1 interrupt service
; Clear INT1 interrupt request flag
; Enable GIE
Example: INT1 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FP01IRQ
EXIT_INT
; Check P01IRQ
; P01IRQ = 0, exit interrupt vector
B0BCLR
…
…
FP01IRQ
; Reset P01IRQ
; INT1 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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5.8 INT2 (P0.2) INTERRUPT OPERATION
When the INT2 trigger occurs, the P02IRQ will be set to “1” no matter the P02IEN is enable or disable. If the P02IEN =
1 and the trigger event P02IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG
8). If the P02IEN = 0 and the trigger event P02IRQ is still set to be “1”. Moreover, the system won’t execute interrupt
vector even when the P02IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt
situation.
Note: The interrupt trigger direction of P0.2 is falling edge.
Example: INT2 interrupt request setup.
B0BSET
B0BCLR
B0BSET
FP02IEN
FP02IRQ
FGIE
; Enable INT2 interrupt service
; Clear INT2 interrupt request flag
; Enable GIE
Example: INT2 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FP02IRQ
EXIT_INT
; Check P02IRQ
; P02IRQ = 0, exit interrupt vector
B0BCLR
…
…
FP02IRQ
; Reset P02IRQ
; INT2 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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5.9 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
Example: T0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FT0IEN
FT0ENB
A, #20H
T0M, A
A, #74H
T0C, A
; Disable T0 interrupt service
; Disable T0 timer
;
; Set T0 clock = Fcpu / 64
; Set T0C initial value = 74H
; Set T0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FT0IEN
FT0IRQ
FT0ENB
; Enable T0 interrupt service
; Clear T0 interrupt request flag
; Enable T0 timer
B0BSET
FGIE
; Enable GIE
Example: T0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FT0IRQ
EXIT_INT
; Check T0IRQ
; T0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FT0IRQ
A, #74H
T0C, A
; Reset T0IRQ
; Reset T0C.
; T0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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5.10 TC0 INTERRUPT OPERATION
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: TC0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC0IEN
FTC0ENB
A, #20H
TC0M, A
A, #74H
TC0C, A
; Disable TC0 interrupt service
; Disable TC0 timer
;
; Set TC0 clock = Fcpu / 64
; Set TC0C initial value = 74H
; Set TC0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC0IEN
FTC0IRQ
FTC0ENB
; Enable TC0 interrupt service
; Clear TC0 interrupt request flag
; Enable TC0 timer
B0BSET
FGIE
; Enable GIE
Example: TC0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC0IRQ
EXIT_INT
; Check TC0IRQ
; TC0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FTC0IRQ
A, #74H
TC0C, A
; Reset TC0IRQ
; Reset TC0C.
; TC0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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5.11 SIO INTERRUPT OPERATION
When the SIO converting successfully, the SIOIRQ will be set to “1” no matter the SIOIEN is enable or disable. If the
SIOIEN and the trigger event SIOIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
SIOIEN = 0, the trigger event SIOIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the SIOIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: SIO interrupt request setup.
B0BSET
B0BCLR
B0BSET
FSIOIEN
FSIOIRQ
FGIE
; Enable SIO interrupt service
; Clear SIO interrupt request flag
; Enable GIE
Example: SIO interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FSIOIRQ
EXIT_INT
; Check SIOIRQ
; SIOIRQ = 0, exit interrupt vector
B0BCLR
…
…
FSIOIRQ
; Reset SIOIRQ
; SIO interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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5.12 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name
P00IRQ
P01IRQ
P02IRQ
T0IRQ
TC0IRQ
SIOIRQ
Trigger Event Description
P0.0 trigger controlled by PEDGE
P0.1 falling edge trigger
P0.2 falling edge trigger
T0C overflow
TC0C overflow
SIO transmitting end.
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
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Example: Check the interrupt request under multi-interrupt operation
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
INTP00CHK:
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTP01CHK
FP00IRQ
INTP00
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTP02CHK
FP01IRQ
INTP01
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTT0CHK
FP02IRQ
INTP02
B0BTS1
JMP
B0BTS0
JMP
FT0IEN
INTTC0CHK
FT0IRQ
INTT0
B0BTS1
JMP
B0BTS0
JMP
FTC0IEN
INTSIOCHK
FTC0IRQ
INTTC0
B0BTS1
JMP
B0BTS0
JMP
FSIOIEN
INT_EXIT
FSIOIRQ
INTSIO
INTP01CHK:
INTP02CHK:
INTT0CHK:
INTTC0CHK:
INTSIOCHK:
; Check INT0 interrupt request
; Check P00IEN
; Jump check to next interrupt
; Check P00IRQ
; Check INT1 interrupt request
; Check P01IEN
; Jump check to next interrupt
; Check P01IRQ
; Check INT2 interrupt request
; Check P02IEN
; Jump check to next interrupt
; Check P02IRQ
; Check T0 interrupt request
; Check T0IEN
; Jump check to next interrupt
; Check T0IRQ
; Jump to T0 interrupt service routine
; Check TC0 interrupt request
; Check TC0IEN
; Jump check to next interrupt
; Check TC0IRQ
; Jump to TC0 interrupt service routine
; Check SIO interrupt request
; Check SIOIEN
; Exit interrupt vector
; Check SIOIRQ
; Jump to SIO interrupt service routine
INT_EXIT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6
I/O PORT
6.1 I/O PORT MODE
The port direction is programmed by PnM register. All I/O ports can select input or output direction.
0B8H
P0M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P04M
R/W
0
Bit 3
P03M
R/W
0
Bit 2
P02M
R/W
0
Bit 1
P01M
R/W
0
Bit 0
P00M
R/W
0
0C1H
P1M
Read/Write
After reset
Bit 7
P17M
R/W
0
Bit 6
P16M
R/W
0
Bit 5
P15M
R/W
0
Bit 4
P14M
R/W
0
Bit 3
P13M
R/W
0
Bit 2
P12M
R/W
0
Bit 1
P11M
R/W
0
Bit 0
P10M
R/W
0
0C2H
P2M
Read/Write
After reset
Bit 7
P27M
R/W
0
Bit 6
P26M
R/W
0
Bit 5
P25M
R/W
0
Bit 4
P24M
R/W
0
Bit 3
P23M
R/W
0
Bit 2
P22M
R/W
0
Bit 1
P21M
R/W
0
Bit 0
P20M
R/W
0
0C4H
P4M
Read/Write
After reset
Bit 7
P47M
R/W
0
Bit 6
P46M
R/W
0
Bit 5
P45M
R/W
0
Bit 4
P44M
R/W
0
Bit 3
P43M
R/W
0
Bit 2
P42M
R/W
0
Bit 1
P41M
R/W
0
Bit 0
P40M
R/W
0
0C5H
P5M
Read/Write
After reset
Bit 7
P57M
R/W
0
Bit 6
P56M
R/W
0
Bit 5
P55M
R/W
0
Bit 4
P54M
R/W
0
Bit 3
P53M
R/W
0
Bit 2
P52M
R/W
0
Bit 1
P51M
R/W
0
Bit 0
P50M
R/W
0
Bit[7:0]
PnM[7:0]: Pn mode control bits. (n = 0~5).
0 = Pn is input mode.
1 = Pn is output mode.
Note: Users can program them by bit control instructions (B0BSET, B0BCLR).
Example: I/O mode selecting
CLR
CLR
CLR
P0M
P4M
P5M
; Set all ports to be input mode.
MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0M, A
P4M,A
P5M, A
; Set all ports to be output mode.
B0BCLR
P4M.0
; Set P4.0 to be input mode.
B0BSET
P4M.0
; Set P4.0 to be output mode.
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6.2 I/O PULL UP REGISTER
0E0H
P0UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P04R
W
0
Bit 3
P03R
W
0
Bit 2
P02R
W
0
Bit 1
P01R
W
0
Bit 0
P00R
W
0
0E1H
P1UR
Read/Write
After reset
Bit 7
P17R
W
0
Bit 6
P16R
W
0
Bit 5
P15R
W
0
Bit 4
P14R
W
0
Bit 3
P13R
W
0
Bit 2
P12R
W
0
Bit 1
P11R
W
0
Bit 0
P10R
W
0
0E2H
P2UR
Read/Write
After reset
Bit 7
P27R
W
0
Bit 6
P26R
W
0
Bit 5
P25R
W
0
Bit 4
P24R
W
0
Bit 3
P23R
W
0
Bit 2
P22R
W
0
Bit 1
P21R
W
0
Bit 0
P20R
W
0
0E4H
P4UR
Read/Write
After reset
Bit 7
P47R
W
0
Bit 6
P46R
W
0
Bit 5
P45R
W
0
Bit 4
P44R
W
0
Bit 3
P43R
W
0
Bit 2
P42R
W
0
Bit 1
P41R
W
0
Bit 0
P40R
W
0
0E5H
P5UR
Read/Write
After reset
Bit 7
P57R
W
0
Bit 6
P56R
W
0
Bit 5
P55R
W
0
Bit 4
P54R
W
0
Bit 3
P53R
W
0
Bit 2
P52R
W
0
Bit 1
P51R
W
0
Bit 0
P50R
W
0
Example: I/O Pull up Register
MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0UR, A
P4UR,A
P5UR, A
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; Enable Port0, 4, 5 Pull-up register,
;
Page 62
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
6.3 I/O PORT DATA REGISTER
0D0H
P0
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P04
R/W
0
Bit 3
P03
R/W
0
Bit 2
P02
R/W
0
Bit 1
P01
R/W
0
Bit 0
P00
R/W
0
0D1H
P1
Read/Write
After reset
Bit 7
P17
R/W
0
Bit 6
P16
R/W
0
Bit 5
P15
R/W
0
Bit 4
P14
R/W
0
Bit 3
P13
R/W
0
Bit 2
P12
R/W
0
Bit 1
P11
R/W
0
Bit 0
P10
R/W
0
0D2H
P2
Read/Write
After reset
Bit 7
P27
R/W
0
Bit 6
P26
R/W
0
Bit 5
P25
R/W
0
Bit 4
P24
R/W
0
Bit 3
P23
R/W
0
Bit 2
P22
R/W
0
Bit 1
P21
R/W
0
Bit 0
P20
R/W
0
0D4H
P4
Read/Write
After reset
Bit 7
P47
R/W
0
Bit 6
P46
R/W
0
Bit 5
P45
R/W
0
Bit 4
P44
R/W
0
Bit 3
P43
R/W
0
Bit 2
P42
R/W
0
Bit 1
P41
R/W
0
Bit 0
P40
R/W
0
0D5H
P5
Read/Write
After reset
Bit 7
P57
R/W
0
Bit 6
P56
R/W
0
Bit 5
P55
R/W
0
Bit 4
P54
R/W
0
Bit 3
P53
R/W
0
Bit 2
P52
R/W
0
Bit 1
P51
R/W
0
Bit 0
P50
R/W
0
Example: Read data from input port.
B0MOV
A, P0
B0MOV
A, P4
B0MOV
A, P5
Example: Write data to output port.
MOV
A, #0FFH
B0MOV
P0, A
B0MOV
P4, A
B0MOV
P5, A
Example: Write one bit data to output port.
B0BSET
P4.0
B0BSET
P5.3
B0BCLR
B0BCLR
P4.0
P5.3
SONiX TECHNOLOGY CO., LTD
; Read data from Port 0
; Read data from Port 4
; Read data from Port 5
; Write data FFH to all Port.
; Set P4.0 and P5.3 to be “1”.
; Set P4.0 and P5.3 to be “0”.
Page 63
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
6.4 I/O OPEN-DRAIN REGISTER
P5.2 is built-in open-drain function. P5.2 must be set as output mode when enable open-drain function. Open-drain
external circuit is as following.
MCU2
MCU1
U
U
VCC
Pull-up Resistor
Open-drain pin
Open-drain pin
The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCU’s
pin.
0E9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1OC
P52OC
Read/Write
W
After reset
0
Bit 2
P52OC: P5.2 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Example: Enable P5.2 to open-drain mode and output high.
B0BSET
P5.2
; Set P5.2 buffer high.
B0BSET
MOV
B0MOV
P52M
A, #04H
P1OC, A
; Enable P5.2 output mode.
; Enable P5.2 open-drain function.
Note: P1OC is write only register. Setting P10OC must be used “MOV” instructions.
Example: Disable P5.2 to open-drain mode and output low.
MOV
B0MOV
A, #0
P1OC, A
; Disable P5.2 open-drain function.
Note: After disable open-drain function, I/O mode returns to last I/O mode.
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7
TIMERS
7.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (16KHz @3V, 32KHz @5V).
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
VDD
3V
5V
Internal Low RC Freq.
16KHz
32KHz
Watchdog Overflow Time
512ms
256ms
Note:
1. If watchdog is “Always_On” mode, it keeps running event under power down mode or green
mode.
2. For S8KD ICE simulation, clear watchdog timer using “@RST_WDT” macro is necessary. Or
the S8KD watchdog would be error.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH
WDTR
Read/Write
After reset
Bit 7
WDTR7
W
0
Bit 6
WDTR6
W
0
Bit 5
WDTR5
W
0
Bit 4
WDTR4
W
0
Bit 3
WDTR3
W
0
Bit 2
WDTR2
W
0
Bit 1
WDTR1
W
0
Bit 0
WDTR0
W
0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
MOV
B0MOV
…
…
CALL
CALL
…
…
JMP
A, #5AH
WDTR, A
; Clear the watchdog timer.
SUB1
SUB2
MAIN
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
Example: Clear watchdog timer by @RST_WDT macro.
Main:
@RST_WDT
…
…
CALL
CALL
…
…
JMP
; Clear the watchdog timer.
SUB1
SUB2
MAIN
Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
Err:
…
…
JMP $
; Check I/O.
; Check RAM
; I/O or RAM error. Program jump here and don’t
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct:
B0BSET
…
CALL
CALL
…
…
…
JMP
FWDRST
; I/O and RAM are correct. Clear watchdog timer and
; execute program.
; Only one clearing watchdog timer of whole program.
SUB1
SUB2
MAIN
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7.2 TIMER 0 (T0)
7.2.1 OVERVIEW
The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue
counting and issue a time-out signal to trigger T0 interrupt to request interrupt service.
The main purposes of the T0 timer is as following.
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
T0 Rate
(Fcpu/2~Fcpu/256)
T0ENB
Internal Data Bus
Load
Fcpu
T0C 8-Bit Binary Up Counting Counter
T0 Time Out
CPUM0,1
7.2.2 T0M MODE REGISTER
0D8H
T0M
Read/Write
After reset
Bit 7
T0ENB
R/W
0
Bit 6
T0rate2
R/W
0
Bit 5
T0rate1
R/W
0
Bit [6:4]
T0RATE[2:0]: T0 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7
T0ENB: T0 counter control bit.
0 = Disable T0 timer.
1 = Enable T0 timer.
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Bit 4
T0rate0
R/W
0
Page 67
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7.2.3 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control.
0D9H
T0C
Read/Write
After reset
Bit 7
T0C7
R/W
0
Bit 6
T0C6
R/W
0
Bit 5
T0C5
R/W
0
Bit 4
T0C4
R/W
0
Bit 3
T0C3
R/W
0
Bit 2
T0C2
R/W
0
Bit 1
T0C1
R/W
0
Bit 0
T0C0
R/W
0
The equation of T0C initial value is as following.
T0C initial value = 256 - (T0 interrupt interval time * input clock)
Example: To set 10ms interval time for T0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
T0RATE=010 (Fcpu/64).
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
The basic timer table interval time of T0.
High speed mode (Fcpu = 4MHz / 4)
T0RATE
T0CLOCK
Max overflow interval One step = max/256
000
Fcpu/256
65.536 ms
256 us
001
Fcpu/128
32.768 ms
128 us
010
Fcpu/64
16.384 ms
64 us
011
Fcpu/32
8.192 ms
32 us
100
Fcpu/16
4.096 ms
16 us
101
Fcpu/8
2.048 ms
8 us
110
Fcpu/4
1.024 ms
4 us
111
Fcpu/2
0.512 ms
2 us
SONiX TECHNOLOGY CO., LTD
Page 68
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval One step = max/256
8000 ms
31250 us
4000 ms
15625 us
2000 ms
7812.5 us
1000 ms
3906.25 us
500 ms
1953.125 us
250 ms
976.563 us
125 ms
488.281 us
62.5 ms
244.141 us
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7.2.4 T0 TIMER OPERATION SEQUENCE
T0 timer operation sequence of setup T0 timer is as following.
Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
FT0ENB
FT0IEN
FT0IRQ
; T0 timer.
; T0 interrupt function is disabled.
; T0 interrupt request flag is cleared.
MOV
A, #0xxx0000b
B0MOV
T0M,A
;The T0 rate control bits exist in bit4~bit6 of T0M. The
; value is from x000xxxxb~x111xxxxb.
; T0 timer is disabled.
Set T0 timer rate.
Set T0 interrupt interval time.
MOV
B0MOV
A,#7FH
T0C,A
; Set T0C value.
FT0IEN
; Enable T0 interrupt function.
FT0ENB
; Enable T0 timer.
Set T0 timer function mode.
B0BSET
Enable T0 timer.
B0BSET
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7.3 TIMER/COUNTER 0 (TC0)
7.3.1 OVERVIEW
The TC0 is an 8-bit binary up counting. TC0 has two clock sources including internal clock and external clock for
counting a precision time. The internal clock source is from Fcpu. The external clock is INT0 from P0.0 pin (Falling
edge trigger). Using TC0M register selects TC0C’s clock source from internal or external. If TC0 timer occurs an
overflow, it will continue counting and issue a time-out signal to trigger TC0 interrupt to request interrupt service. TC0
overflow time is 0xFF to 0X00 normally. The main purposes of the TC0 timer is as following.
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
External event counter: Counts system “events” based on falling edge detection of external clock signals at the
INT0 input pin.
TC0OUT
Internal P5.4 I/O Circuit
Up Counting
Reload Value
ALOAD0
Buzzer
Auto. Reload
TC0 Time Out
TC0R Reload
Data Buffer
R
TC0CKS
Compare
TC0ENB
P5.4
ALOAD0, TC0OUT
TC0 Rate
(Fcpu/2~Fcpu/256)
Fcpu
TC0 / 2
PWM0OUT
PWM
S
Load
TC0C
8-Bit Binary Up
Counting Counter
TC0 Time Out
INT0
(Schmitter Trigger)
CPUM0,1
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7.3.2 TC0M MODE REGISTER
0DAH
TC0M
Read/Write
After reset
Bit 7
TC0ENB
R/W
0
Bit 6
TC0rate2
R/W
0
Bit 5
TC0rate1
R/W
0
Bit 4
TC0rate0
R/W
0
Bit 3
TC0CKS: TC0 clock source select bit.
0 = Internal clock (Fcpu or Fosc).
1 = External clock from P0.0/INT0 pin.
Bit [6:4]
TC0RATE[2:0]: TC0 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7
TC0ENB: TC0 counter control bit.
0 = Disable TC0 timer.
1 = Enable TC0 timer.
Bit 3
TC0CKS
R/W
0
Bit 2
-
Bit 1
-
Bit 0
-
Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0
interrupt request will be raised. (P0.0IRQ will be always 0).
SONiX TECHNOLOGY CO., LTD
Page 71
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7.3.3 TC0C COUNTING REGISTER
TC0C is an 8-bit counter register for TC0 interval time control.
0DBH
TC0C
Read/Write
After reset
Bit 7
TC0C7
R/W
0
Bit 6
TC0C6
R/W
0
Bit 5
TC0C5
R/W
0
Bit 4
TC0C4
R/W
0
Bit 3
TC0C3
R/W
0
Bit 2
TC0C2
R/W
0
Bit 1
TC0C1
R/W
0
Bit 0
TC0C0
R/W
0
The equation of TC0C initial value is as following.
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
Example: To set 10ms interval time for TC0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
TC0RATE=010 (Fcpu/64).
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
The basic timer table interval time of TC0.
High speed mode (Fcpu = 4MHz / 4)
TC0RATE TC0CLOCK
Max overflow interval One step = max/256
000
Fcpu/256
65.536 ms
256 us
001
Fcpu/128
32.768 ms
128 us
010
Fcpu/64
16.384 ms
64 us
011
Fcpu/32
8.192 ms
32 us
100
Fcpu/16
4.096 ms
16 us
101
Fcpu/8
2.048 ms
8 us
110
Fcpu/4
1.024 ms
4 us
111
Fcpu/2
0.512 ms
2 us
SONiX TECHNOLOGY CO., LTD
Page 72
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval One step = max/256
8000 ms
31250 us
4000 ms
15625 us
2000 ms
7812.5 us
1000 ms
3906.25 us
500 ms
1953.125 us
250 ms
976.563 us
125 ms
488.281 us
62.5 ms
244.141 us
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
7.3.4 TC0 TIMER OPERATION SEQUENCE
TC0 timer operation includes timer interrupt, event counter. The sequence of setup TC0 timer is as following.
Stop TC0 timer counting, disable TC0 interrupt function and clear TC0 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
FTC0ENB
FTC0IEN
FTC0IRQ
; TC0 timer stop.
; TC0 interrupt function is disabled.
; TC0 interrupt request flag is cleared.
Set TC0 timer rate. (Besides event counter mode.)
MOV
A, #0xxx0000b
B0MOV
TC0M,A
;The TC0 rate control bits exist in bit4~bit6 of TC0M. The
; value is from x000xxxxb~x111xxxxb.
; TC0 interrupt function is disabled.
Set TC0 timer clock source.
; Select TC0 internal / external clock source.
B0BCLR
FTC0CKS
or
B0BSET
FTC0CKS
; Select TC0 internal clock source.
; Select TC0 external clock source.
Set TC0 interrupt interval time.
; Set TC0 interrupt interval time.
MOV
B0MOV
A,#7FH
TC0C,A
; TC0C value is decided by TC0 mode.
; Set TC0C value.
Set TC0 timer function mode.
B0BSET
FTC0IEN
; Enable TC0 interrupt function.
FTC0ENB
; Enable TC0 timer.
Enable TC0 timer.
B0BSET
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
8
SERIAL INPUT/OUTPUT TRANSCEIVER
(SIO)
8.1 OVERVIEW
The SIO (serial input/output) transceiver allows high-speed synchronous data transfer between the SN8A2617 series
MCU and peripheral devices or between several SN8A2617 devices. These peripheral devices may be Serial
EEPROMs, shift registers, display drivers, etc. The SN8A2617 SIO features include the following:
Full-duplex, 3-wire synchronous data transfer
TX/RX or TX Only mode
Master (SCK is clock output) or Slave (SCK is clock input) operation
LSB first data transfer
SO (P5.2) is programmable open-drain output pin for multiple salve devices application
Two programmable bit rates (Only in master mode)
End-of-Transfer interrupt
The SIOM register can control SIO operating function, such as: transmit/receive, clock rate, transfer edge and starting
this circuit. This SIO circuit will transmit or receive 8-bit data automatically by setting SENB and START bits in SIOM
register. The SIOB is an 8-bit buffer, which is designed to store transfer data. SIOC and SIOR are designed to
generate SIO’s clock source with auto-reload function. The 3-bit I/O counter can monitor the operation of SIO and
announce an interrupt request after transmitting/receiving 8-bit data. After transferring 8-bit data, this circuit will be
disabled automatically and re-transfer data by programming SIOM register.
Senb
Data bus
SIOM register
Senb, TxRx
SI/P5.1 pin
Sckmd
Senb
SO/P5.2 pin
SIOB 8-bit buffer
CPUM1,0
SCK/P5.0 pin
CPUM1,0
SCK sources
CPUM1,0
3-bit I/O
counter
SIOC
8-bit binary counter
Sckmd
Sedge
SIO Time out
reset
Senb
Senb
Srate
Auto_reload
SIOR register
SIO Interface Circuit Diagram
SONiX TECHNOLOGY CO., LTD
Page 74
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
The system is single-buffered in the transmit direction and double-buffered in the receive direction. This means that
bytes to be transmitted cannot be written to the SIOB Data Register before the entire shift cycle is completed. When
receiving data, however, a received byte must be read from the SIOB Data Register before the next byte has been
completely shifted in. Otherwise, the first byte is lost. Following figure shows a typical SIO transfer between two
S8P2700A micro-controllers. Master MCU sends SCK for initial the data transfer. Both mater and slave MCU must
work in the same clock edge direction, and then both controllers would send and receive data at the same time.
SIO Master
SIO Slave
(SCKMD = 0)
(SCKMD = 1)
Read SIOB
SCK
SCK
SI
SO
2nd Receive Buffer
(Address = SIOB)
Shift Register
(SIOB)
Shift Register
(SIOB)
Write SIOB
Read SIOB
Write SIOB
SO
SI
Internal Bus
Internal Bus
2nd Receive Buffer
(Address = SIOB)
SIO Data Transfer Diagram
The SIO data transfer timing as following figure:
SCK (P5.0)
(SEDGE = 0)
SCK (P5.0)
(SEDGE = 1)
Shift Data Out
SO (P5.2)
(TX/RX = 1)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Shift Data In
SI (P5.1)
SO (P5.2)
(TX/RX = 0)
General Purpose I/O Pin
SIO Data Transfer Timing
Note: In any mode, SIO always transmit data in first SCK edge and receive data in second SCK edge.
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
8.2 SIOM MODE REGISTER
SIOM initial value = 0000 x000
0B4H
Bit 7
Bit 6
SIOM
SENB
START
Read/Write
R/W
R/W
After reset
0
0
Bit 5
SRATE1
R/W
0
Bit 4
SRATE0
R/W
0
Bit 3
-
Bit 2
SCKMD
R/W
0
Bit 1
SEDGE
R/W
0
Bit 7
SENB: SIO function control bit.
0 = disable (P5.0~P5.2 is general purpose port).
1 = enable (P5.0~P5.2 is SIO pins).
Bit 6
START: SIO progress control bit.
0 = End of transfer.
1 = progressing.
Bit [5:4]
SRATE1,0: SIO’s transfer rate select bit. These 2-bits are workless when SCKMD=1.
00 = fcpu.
01 = fcpu/32
10 = fcpu/16
11 = fcpu/8.
Bit 2
SCKMD: SIO’s clock mode select bit.
0 = Internal.
1 = External.
Bit 1
SEDGE: SIO’s transfer clock edge select bit.
0 = Falling edge.
1 = Rising edge.
Bit 0
TXRX: SIO’s transfer direction select bit.
0 = Receiver only.
1 = Transmitter/receiver full duplex.
Bit 0
TXRX
R/W
0
Note: 1. If SCKMD=1 for external clock, the SIO is in SLAVE mode. If SCKMD=0 for internal clock,
the SIO is in MASTER mode.
2. Don’t set SENB and START bits in the same time. That makes the SIO function error.
Because SIO function is shared with Port5 for P5.0 as SCK, P5.1 as SI and P5.2 as SO.
The following table shown the Port5[2:0] I/O mode behavior and setting when SIO function enable and disable.
SENB=1 (SIO Function Enable)
(SCKMD=1)
P5.0 will change to Input mode automatically, no matter what P5M
SIO source = External clock
setting
P5.0/SCK
(SCKMD=0)
P5.0 will change to Output mode automatically, no matter what
SIO source = Internal clock
P5M setting
P5.1/SI
P5.1 must be set as Input mode in P5M ,or the SIO function will be abnormal
(TXRX=1)
P5.2 will change to Output mode automatically, no matter what
SIO = Transmitter/Receiver
P5M setting
P5.2/SO
(TXRX=0)
P5.2 will change to Input mode automatically, no matter what P5M
SIO = Receiver only
setting
SENB=0 (SIO Function Disable)
P5.0/P5.1/P5.2 Port5[2:0] I/O mode are fully controlled by P5M when SIO function Disable
SONiX TECHNOLOGY CO., LTD
Page 76
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
8.3 SIOB DATA BUFFER
SIOB initial value = 0000 0000
0B6H
Bit 7
Bit 6
SIOB
SIOB7
SIOB6
Read/Write
R/W
R/W
After reset
0
0
Bit 5
SIOB5
R/W
0
Bit 4
SIOB4
R/W
0
Bit 3
SIOB3
R/W
0
Bit 2
SIOB2
R/W
0
Bit 1
SIOB1
R/W
0
Bit 0
SIOB0
R/W
0
Bit 2
SIOR2
W
0
Bit 1
SIOR1
W
0
Bit 0
SIOR0
W
0
SIOB is the SIO data buffer register. It stores serial I/O transmit and receive data.
8.4 SIOR REGISTER DESCRIPTION
SIOR initial value = 0000 0000
0B5H
Bit 7
Bit 6
SIOR
SIOR7
SIOR6
Read/Write
W
W
After reset
0
0
Bit 5
SIOR5
W
0
Bit 4
SIOR4
W
0
Bit 3
SIOR3
W
0
The SIOR is designed for the SIO counter to reload the counted value when end of counting. It is like a post-scaler of
SIO clock source and let SIO has more flexible to setting SCK range. Users can set the SIOR value to setup SIO
transfer time. To setup SIOR value equation to desire transfer time is as following.
SCK frequency = SIO rate / (256 - SIOR)
SIOR = 256 - ( 1 / ( SCK frequency ) * SIO rate )
Example: Setup the SIO clock to be 5KHz. Fosc = 3.58MHz. SIO’s rate = Fcpu = Fosc/4.
SIOR = 256 – (1/(5KHz) * 3.58MHz/4)
= 256 – (0.0002*895000)
= 256 – 179
= 77
SONiX TECHNOLOGY CO., LTD
Page 77
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
Example: Master, duplex transfer and transmit data on rising edge
MOV
B0MOV
MOV
B0MOV
MOV
B0MOV
B0BSET
A,TXDATA
SIOB,A
A,#0FFH
SIOR,A
A,#10000001B
SIOM,A
FSTART
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Load transmitted data into SIOB register.
; Set SIO clock
; Setup SIOM and enable SIO function.
; Start transfer and receiving SIO data.
CHK_END:
; Wait the end of SIO operation.
; Save SIOB data into RXDATA buffer.
Example: Master, duplex transfer and transmit data on falling edge
MOV
B0MOV
MOV
B0MOV
MOV
B0MOV
B0BSET
A,TXDATA
SIOB,A
A,#0FFH
SIOR,A
A,#10000011B
SIOM,A
FSTART
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Load transmitted data into SIOB register.
; Set SIO clock.
; Setup SIOM and enable SIO function.
; Start transfer and receiving SIO data.
CHK_END:
; Wait the end of SIO operation.
; Save SIOB data into RXDATA buffer.
Example: Master, receive only and transmit data on rising edge
MOV
B0MOV
MOV
B0MOV
B0BSET
A,#0FFH
SIOR,A
A,#10000000B
SIOM,A
FSTART
; Set SIO clock with auto-reload function.
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Wait the end of SIO operation.
; Setup SIOM and enable SIO function.
; Start receiving SIO data.
CHK_END:
; Save SIOB data into RXDATA buffer.
Example: Master, receive only and transmit data on falling edge
MOV
B0MOV
MOV
B0MOV
B0BSET
A,#0FFH
SIOR,A
A,#10000010B
SIOM,A
FSTART
; Set SIO clock.
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Wait the end of SIO operation.
; Setup SIOM and enable SIO function.
; Start receiving SIO data.
CHK_END:
SONiX TECHNOLOGY CO., LTD
; Save SIOB data into RXDATA buffer.
Page 78
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
Example: Slave, duplex transfer and transmit data on rising edge
MOV
B0MOV
MOV
B0MOV
B0BSET
A,TXDATA
SIOB,A
A,# 10000101B
SIOM,A
FSTART
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Load transfer data into SIOB register.
; Setup SIOM and enable SIO function.
; Start transfer and receiving SIO data.
CHK_END:
; Wait the end of SIO operation.
; Save SIOB data into RXDATA buffer.
Example: Slave, duplex transfer and transmit data on falling edge
MOV
B0MOV
MOV
B0MOV
B0BSET
A,TXDATA
SIOB,A
A,# 10000111B
SIOM,A
FSTART
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Load transfer data into SIOB register.
; Setup SIOM and enable SIO function.
; Start transfer and receiving SIO data.
CHK_END:
; Wait the end of SIO operation.
; Save SIOB data into RXDATA buffer.
Example: Slave, receive only and transmit data on rising edge
MOV
B0MOV
B0BSET
A,# 10000100B
SIOM,A
FSTART
; Setup SIOM and enable SIO function.
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Wait the end of SIO operation.
; Start receiving SIO data.
CHK_END:
; Save SIOB data into RXDATA buffer.
Example: Slave, receive only and transmit data on falling edge
MOV
B0MOV
B0BSET
A,# 10000110B
SIOM,A
FSTART
; Setup SIOM and enable SIO function.
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
RXDATA,A
; Wait the end of SIO operation.
; Start receiving SIO data.
CHK_END:
SONiX TECHNOLOGY CO., LTD
; Save SIOB data into RXDATA buffer.
Page 79
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
9
Field
M
O
V
E
A
R
I
T
H
M
E
T
I
C
L
O
G
I
C
P
R
O
C
E
S
S
B
R
A
N
C
H
INSTRUCTION TABLE
Mnemonic
MOV
A,M
MOV
M,A
B0MOV
A,M
B0MOV
M,A
MOV
A,I
B0MOV
M,I
XCH
A,M
B0XCH
A,M
MOVC
Description
A←M
M←A
A ← M (bank 0)
M (bank 0) ← A
A←I
M ← I, “M” only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z…)
A ←→M
A ←→M (bank 0)
R, A ← ROM [Y,Z]
C
-
DC
-
Z
√
√
-
Cycle
1
1
1
1
1
1
1+N
1+N
2
ADC
ADC
ADD
ADD
B0ADD
ADD
SBC
SBC
SUB
SUB
SUB
A,M
M,A
A,M
M,A
M,A
A,I
A,M
M,A
A,M
M,A
A,I
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
1
1+N
1
1+N
1+N
1
1
1+N
1
1+N
1
MUL
A,M
A ← A + M + C, if occur carry, then C=1, else C=0
M ← A + M + C, if occur carry, then C=1, else C=0
A ← A + M, if occur carry, then C=1, else C=0
M ← A + M, if occur carry, then C=1, else C=0
M (bank 0) ← M (bank 0) + A, if occur carry, then C=1, else C=0
A ← A + I, if occur carry, then C=1, else C=0
A ← A - M - /C, if occur borrow, then C=0, else C=1
M ← A - M - /C, if occur borrow, then C=0, else C=1
A ← A - M, if occur borrow, then C=0, else C=1
M ← A - M, if occur borrow, then C=0, else C=1
A ← A - I, if occur borrow, then C=0, else C=1
R, A ← A * M, The LB of product stored in Acc and HB stored in R register. ZF affected by
Acc.
-
-
√
2
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
A,M
M,A
A,I
A,M
M,A
A,I
A,M
M,A
A,I
A ← A and M
M ← A and M
A ← A and I
A ← A or M
M ← A or M
A ← A or I
A ← A xor M
M ← A xor M
A ← A xor I
-
-
1
1+N
1
1
1+N
1
1
1+N
1
SWAP
SWAPM
RRC
RRCM
RLC
RLCM
CLR
BCLR
BSET
B0BCLR
B0BSET
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
A (b3~b0, b7~b4) ←M(b7~b4, b3~b0)
M(b3~b0, b7~b4) ← M(b7~b4, b3~b0)
A ← RRC M
M ← RRC M
A ← RLC M
M ← RLC M
M←0
M.b ← 0
M.b ← 1
M(bank 0).b ← 0
M(bank 0).b ← 1
√
√
√
√
-
-
√
√
√
√
√
√
√
√
√
-
1
1+N
1
1+N
1
1+N
1
1+N
1+N
1+N
1+N
CMPRS
CMPRS
INCS
INCMS
DECS
DECMS
BTS0
BTS1
B0BTS0
B0BTS1
JMP
CALL
A,I
A,M
M
M
M
M
M.b
M.b
M.b
M.b
d
d
ZF,C ← A - I, If A = I, then skip next instruction
ZF,C ← A – M, If A = M, then skip next instruction
A ← M + 1, If A = 0, then skip next instruction
M ← M + 1, If M = 0, then skip next instruction
A ← M - 1, If A = 0, then skip next instruction
M ← M - 1, If M = 0, then skip next instruction
If M.b = 0, then skip next instruction
If M.b = 1, then skip next instruction
If M(bank 0).b = 0, then skip next instruction
If M(bank 0).b = 1, then skip next instruction
PC15/14 ← RomPages1/0, PC13~PC0 ← d
Stack ← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d
√
√
-
-
√
√
-
1+S
1+S
1+ S
1+N+S
1+ S
1+N+S
1+S
1+S
1+S
1+S
2
2
√
-
√
-
√
-
2
2
1
1
1
RET
PC ← Stack
RETI
PC ← Stack, and to enable global interrupt
PUSH
To push ACC and PFLAG (except NT0, NPD bit) into buffers.
POP
To pop ACC and PFLAG (except NT0, NPD bit) from buffers.
NOP
No operation
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1.
2. If branch condition is true then “S = 1”, otherwise “S = 0”.
M
I
S
C
SONiX TECHNOLOGY CO., LTD
Page 80
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
10 ELECTRICAL CHARACTERISTIC
10.1 ABSOLUTE MAXIMUM RATING
(All of the voltages referenced to Vss)
Supply voltage (Vdd)………………………………………………………………………………………………… - 0.3V ~ 6.0V
Input in voltage (Vin)……………………………………………………………………………………..Vss - 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr).…………………………………………………………………………
0°C ~ + 70°C
Storage ambient temperature (Tstor) ………………………………………………………………….……… –40°C ~ + 125°C
10.2 STANDARD ELECTRICAL CHARACTERISTIC
(All of voltages referenced to Vss, Vdd = 3.0V, fosc = 4 MHz, ambient temperature is 25°C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
MAX.
UNIT
Operating voltage
Vdd
Normal mode, 1mips~16mips
RAM Data Retention voltage
Vdd rise rate
Vdr
Vpor
ViL1
ViL2
ViH1
ViH2
Ilekg
Rup
Ilekg
IoH
IoL
Tint0
Vdd rise rate to ensure internal power-on reset
0.05
All input ports
Vss
Reset pin
Vss
All input ports
0.8Vdd
Reset pin
0.8Vdd
Vin = Vdd
Vin = Vss , Vdd = 3V
100
Pull-up resistor disable, Vin = Vdd
Vop = Vdd - 0.5V
Vop = Vss + 0.5V
INT0 ~ INT2 interrupt request pulse width
2/fcpu
Vdd=3V, Fcpu=16MHz/2
normal Mode
(No loading)
Vdd=3V, Fcpu=4MHz/4
-
Input Low Voltage
Input High Voltage
Reset pin leakage current
I/O port pull-up resistor
I/O port input leakage current
I/O output source current
sink current
INTn trigger pulse width
Supply Current
Idd1
Idd2
Sleep Mode
Vdd= 3V
Vdet1 LVD_L Low voltage detect level.
LVD Detect Voltage
Vdet2 LVD_H Low voltage detect level.
*These parameters are for design reference, not tested.
SONiX TECHNOLOGY CO., LTD
Page 81
LVD
1.5
2.0
-
5.5
V
1.5*
200
12*
15*
3
0.2Vdd
0.2Vdd
Vdd
Vdd
2
300
2
6
V
V/ms
V
V
V
V
uA
KΩ
uA
mA
mA
Cycle
mA
1.5
3
mA
0.5
1.8
2.4
2
2.0
3.0
uA
V
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
11 DEVELOPMENT TOOL
SN8A2617 development tools are as following.
ICE version: SN8ICE2K.
IDE version: M2IDE_V110 later.
SN8A2617 is MASK type MCU and no OTP type. The SIO's mode control methods is like SN8P2708A and the
waveform is like SN8P1707. Use ICE to develop and emulate the SN8A2617 function. If user wants to verify function
by OTP MCU, the SN8P1707 and SN8P2708A can emulate partial functions of SN8A2617.
Migration SN8P1707 and SN8P2708A to SN8A2617.
Item
I/O
SN8A2617
SN8P2708A
SN8P1707
37 pins. (Add P0.3, P0.4, 36 pins. (Add P0.3, P1.6, 33 pins
P1.6, P1.7)
P1.7)
PUSH, POP
Save ACC and PFLAG.
Save ACC and working
Save working registers
registers 80h~FFh.
80h~FFh.
DAC
No
Yes
Yes
ADC
No
Yes
Yes
SIO
Double buffer design
Single buffer design
Double buffer design
SIO control is like SN8P2708A
SIO
operation
is
like
SN8P1707
T0
Yes
Yes
Yes
TC0
Timer/Event Counter
Timer/Event
Timer/Event
Counter/PWM/Buzzer
Counter/PWM/Buzzer
TC1
No
Yes
Yes
Operating mode Normal mode
Normal mode
Normal mode
Sleep mode
Sleep mode
Sleep mode
Slow mode
Slow mode
Green mode
Green mode
System clock
External RC
External RC
External RC
External crystal
External crystal
External crystal
Operating voltage LVD~5.5V
2.4V~5.5V
2.2V~5.5V
SONiX TECHNOLOGY CO., LTD
Page 82
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
12 PACKAGE INFORMATION
12.1 QFP 44 PIN
SYMBOLS
A
A1
A2
b
C
D
D1
E
E1
L
[e]
θ°
MIN
NOR
MAX
MIN
(inch)
0.010
0.075
0.004
0.512
0.390
0.512
0.390
0.029
0°
SONiX TECHNOLOGY CO., LTD
0.012
0.079
0.012
0.006
0.520
0.394
0.520
0.394
0.035
0.031
-
NOR
MAX
(mm)
0.106
0.014
0.087
0.250
1.900
0.008
0.528
0.398
0.528
0.398
0.037
0.100
13.000
9.900
13.000
9.900
0.730
7°
0°
Page 83
0.300
2.000
0.300
0.150
13.200
10.000
13.200
10.000
0.880
0.800
-
2.700
0.350
2.200
0.200
13.400
10.100
13.400
10.100
0.930
7°
Version 1.1
SN8A2617
8-bit micro-controller MASK type with SIO function
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or
design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed,
intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a
situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such
unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries,
affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use
even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C.
Tel: 886-3-551 0520
Fax: 886-3-551 0523
Taipei Office:
Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C.
Tel: 886-2-2759 1980
Fax: 886-2-2759 8180
Hong Kong Office:
Address: Unit No.705,Level 7 Tower 1,Grand Central Plaza 138 Shatin Rural
Committee Road,Shatin,New Territories,Hong Kong.
Tel: 852-2723-8086
Fax: 852-2723-9179
Technical Support by Email:
[email protected]
SONiX TECHNOLOGY CO., LTD
Page 84
Version 1.1