SONIX SN8A1602A

SN8P1600
8-Bit Micro-Controller
SN8P1600 Series
USER’S MANUAL
SN8P1602
SN8P1603
SN8P1604
No Recommend in New Design
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
Revision 1.94
SN8P1600
8-bit micro-controller
AMENDENT HISTORY
Version
Date
Description
VER 1.90
Sep. 2002
V1.9 first issue
VER 1.91
Sep. 2002
Correct some V1.9 typing errors
VER 1.92
Oct. 2002
1. Correct some template code errors
2. Modify description of code option
3. Modify approval form section
4. Modify description of TC1 timer and add more explanation about PWM function
VER 1.93
Feb. 2003
1. Extend chip operating temperature from “0°C ~ +70°C” to “-20°C ~ +70°C”.
2. Change the description of ADD M,A instruction from “M
M+A” to “M
A+M”
3. Change “ACC can’t be access by “B0MOV” instruction” to “ACC can’t be access by
“B0MOV” instruction during the instant addressing mode”.
4. Correct the description of STKn.
5. Correct the bit definition of INTEN register.
6. Correct the description of “TC1 CLOCK FREQUENCY OUTPUT” section.
7. Correct an error of template code: “b0bclr FWDRST”
“b0bset FWDRST”.
8. Add a notice about OSCM register access cycle.
9. Correct the table of “STANDARD ELECTRICAL CHARACTERISTICS”.
VER 1.94
Sep. 2003
1. Add new section about checksum calculate must avoid 04H~07H
2. Reserved Last 16 word ROM addresses
3. Remove register bit description
4. Modify TC0M description.
5. Modify TC1M description.
6. Modify PWM description
7. Modify slow mode current.
8. Change code option to chapter2
9. Adjust Electrical characteristic page
10. Remove approval sheet.
11. Remove PCB layout notice section.
12. Modify the description of INTRQ register.
SONiX TECHNOLOGY CO., LTD
Revision 1.94
SN8P1600
8-bit micro-controller
Table of Content
AMENDENT HISTORY ............................................................................................................................... 2
1
PRODUCT OVERVIEW................................................................................................................. 8
GENERAL DESCRIPTION........................................................................................................................... 8
SELECTION TABLE..................................................................................................................................... 8
FEATURES .................................................................................................................................................... 9
SYSTEM BLOCK DIAGRAM.................................................................................................................... 10
PIN ASSIGNMENT ..................................................................................................................................... 11
PIN DESCRIPTIONS................................................................................................................................... 13
PIN CIRCUIT DIAGRAMS ........................................................................................................................ 14
2
3
CODE OPTION TABLE ............................................................................................................... 15
ADDRESS SPACES ....................................................................................................................... 16
PROGRAM MEMORY (ROM)................................................................................................................... 16
OVERVIEW .............................................................................................................................................. 16
USER RESET VECTOR ADDRESS (0000H) ........................................................................................... 17
INTERRUPT VECTOR ADDRESS (0008H) ............................................................................................ 17
CHECKSUM CALCULATION ................................................................................................................. 19
GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................................. 20
LOOK-UP TABLE DESCRIPTION.......................................................................................................... 20
JUMP TABLE DESCRIPTION................................................................................................................. 22
DATA MEMORY (RAM) ........................................................................................................................... 24
OVERVIEW .............................................................................................................................................. 24
WORKING REGISTERS............................................................................................................................. 25
Y, Z REGISTERS....................................................................................................................................... 25
R REGISTERS........................................................................................................................................... 26
PROGRAM FLAG ....................................................................................................................................... 27
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Revision 1.94
SN8P1600
8-bit micro-controller
CARRY FLAG ........................................................................................................................................... 27
DECIMAL CARRY FLAG......................................................................................................................... 27
ZERO FLAG ............................................................................................................................................. 27
ACCUMULATOR ....................................................................................................................................... 28
STACK OPERATIONS ............................................................................................................................... 29
OVERVIEW .............................................................................................................................................. 29
STACK REGISTERS ................................................................................................................................. 30
STACK OPERATION EXAMPLE............................................................................................................. 31
PROGRAM COUNTER............................................................................................................................... 32
ONE ADDRESS SKIPPING ..................................................................................................................... 33
MULTI-ADDRESS JUMPING ................................................................................................................. 34
4
ADDRESSING MODE................................................................................................................... 35
OVERVIEW................................................................................................................................................. 35
IMMEDIATE ADDRESSING MODE....................................................................................................... 35
DIRECTLY ADDRESSING MODE .......................................................................................................... 35
INDIRECTLY ADDRESSING MODE ...................................................................................................... 35
5
SYSTEM REGISTER .................................................................................................................... 36
OVERVIEW................................................................................................................................................. 36
SYSTEM REGISTER ARRANGEMENT (BANK 0)................................................................................. 36
BYTES of SYSTEM REGISTER ................................................................................................................ 36
BITS of SYSTEM REGISTER.................................................................................................................... 37
6
POWER ON RESET ...................................................................................................................... 38
OVERVIEW................................................................................................................................................. 38
EXTERNAL RESET DESCRIPTION ......................................................................................................... 39
LOW VOLTAGE DETECTOR (LVD) DESCRIPTION............................................................................. 40
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Page 4
Revision 1.94
SN8P1600
8-bit micro-controller
7
OSCILLATORS ............................................................................................................................. 41
OVERVIEW................................................................................................................................................. 41
CLOCK BLOCK DIAGRAM .................................................................................................................... 41
OSCM REGISTER DESCRIPTION.......................................................................................................... 42
EXTERNAL HIGH-SPEED OSCILLATOR .............................................................................................. 43
OSCILLATOR MODE CODE OPTION ................................................................................................... 43
OSCILLATOR DEVIDE BY 2 CODE OPTION........................................................................................ 43
OSCILLATOR SAFE GUARD CODE OPTION....................................................................................... 43
SYSTEM OSCILLATOR CIRCUITS ......................................................................................................... 44
External RC Oscillator Frequency Measurement .................................................................................... 45
INTERNAL LOW-SPEED OSCILLATOR................................................................................................. 46
SYSTEM MODE DESCRIPTION............................................................................................................... 47
OVERVIEW .............................................................................................................................................. 47
NORMAL MODE...................................................................................................................................... 47
SLOW MODE ........................................................................................................................................... 47
POWER DOWN MODE ........................................................................................................................... 47
SYSTEM MODE CONTROL...................................................................................................................... 48
SYSTEM MODE SWITCHING ................................................................................................................. 49
WAKEUP TIME .......................................................................................................................................... 50
OVERVIEW .............................................................................................................................................. 50
HARDWARE WAKEUP............................................................................................................................ 50
8
TIMERS .......................................................................................................................................... 51
WATCHDOG TIMER (WDT)..................................................................................................................... 51
TIMER0 (TC0) (SN8P1602/1603 ONLY) .................................................................................................... 52
OVERVIEW .............................................................................................................................................. 52
TC0M MODE REGISTER ........................................................................................................................ 53
TC0C COUNTING REGISTER ................................................................................................................ 54
TC0 TIMER OPERATION SEQUENCE .................................................................................................. 55
TIMER1 (TC1) (SN8P1604 ONLY).............................................................................................................. 56
OVERVIEW .............................................................................................................................................. 56
TC1M MODE REGISTER ........................................................................................................................ 57
TC1C COUNTING REGISTER ................................................................................................................ 58
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Revision 1.94
SN8P1600
8-bit micro-controller
TC1R AUTO-LOAD REGISTER .............................................................................................................. 59
TC1 TIMER COUNTER OPERATION SEQUENCE ............................................................................... 60
TC1 CLOCK FREQUENCY OUTPUT (BUZZER) .................................................................................. 62
PWM FUNCTION DESCRIPTION (SN8P1604 ONLY) ............................................................................. 63
OVERVIEW .............................................................................................................................................. 63
PWM PROGRAM DESCRIPTION........................................................................................................... 64
9
INTERRUPT................................................................................................................................... 65
OVERVIEW................................................................................................................................................. 65
INTEN INTERRUPT ENABLE REGISTER .............................................................................................. 66
INTRQ INTERRUPT REQUEST REGISTER ............................................................................................ 66
INTERRUPT OPERATION DESCRIPTION.............................................................................................. 67
GIE GLOBAL INTERRUPT OPERATION............................................................................................... 67
INT0 (P0.0) INTERRUPT OPERATION .................................................................................................. 68
TC0/TC1 INTERRUPT OPERATION ...................................................................................................... 69
MULTI-INTERRUPT OPERATION ......................................................................................................... 70
10
I/O PORT ............................................................................................................................ 71
OVERVIEW................................................................................................................................................. 71
I/O PORT FUNCTION TABLE................................................................................................................... 72
I/O PORT MODE......................................................................................................................................... 73
I/O PORT DATA REGISTER ..................................................................................................................... 74
11
EXTERNAL RESET CIRCUIT........................................................................................ 76
SN8P1602 EXTERNAL RESET CIRCUIT EXAMPLE ......................................................................................... 76
SN8P1603 EXTERNAL RESET CIRCUIT EXAMPLE ......................................................................................... 77
12
CODING ISSUE ................................................................................................................. 79
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Revision 1.94
SN8P1600
8-bit micro-controller
TEMPLATE CODE ..................................................................................................................................... 79
CHIP DECLARATION IN ASSEMBLER .................................................................................................. 83
PROGRAM CHECK LIST .......................................................................................................................... 83
13
14
INSTRUCTION SET TABLE ........................................................................................... 84
ELECTRICAL CHARACTERISTICS ............................................................................ 85
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 85
STANDARD ELECTRICAL CHARACTERISTICS.................................................................................. 85
SN8P1602 ................................................................................................................................................. 85
SN8P1603 ................................................................................................................................................. 86
SN8P1604 ................................................................................................................................................. 87
15
PACKAGE INFORMATION ........................................................................................... 89
P-DIP 18 PIN................................................................................................................................................ 89
SOP 18 PIN .................................................................................................................................................. 90
SSOP 20 PIN ................................................................................................................................................ 91
SOP28PIN .................................................................................................................................................... 92
SK-DIP28PIN............................................................................................................................................... 93
SONiX TECHNOLOGY CO., LTD
Page 7
Revision 1.94
SN8P1600
8-bit micro-controller
1 PRODUCT OVERVIEW
GENERAL DESCRIPTION
The SN8P1600 series is an 8-bit micro-controller utilized CMOS technology and featured with low power consumption
and high performance by its unique electronic structure.
SN8P1602/ SN8P1603 is designed with the excellent IC structure including the program memory up to 1K-word OTP
ROM, data memory of 48-bytes RAM, one 8-bit timer (TC0), a watchdog timer, two interrupt sources (TC0, INT0), and
4-level stack buffers.
More expansion functions come with SN8P1604, such like 4K-word OTP ROM, more data memory of 128-byte RAM,
8-bit timer named TC1, and buzzer function for different application. More details listed below.
Besides, user can choose desired oscillator configuration for the controller. There are four external oscillator
configurations to select for generating system clock, including High/Low speed crystal, ceramic resonator or
cost-saving RC oscillator. SN8P1600 also includes an internal RC oscillator for slow mode controlled by program.
SELECTION TABLE
CHIP
SN8P1602
ROM RAM
1K*16
48
I/O
14
SN8P1603
SN8P1604 4K*16
128
22
Timer
Stack
4
LVD
TC0
TC1
V
-
PWM Wakeup
Package
Buzzer Pin no.
On/Off
-
6
DIP18/SOP18/SSOP20
1
10
SKDIP28/SOP28
On
-
V
On/off
Notice: The SN8P1603 always turn the LVD (low voltage detect) on.
SONiX TECHNOLOGY CO., LTD
Page 8
Revision 1.94
SN8P1600
8-bit micro-controller
FEATURES
♦
Memory configuration
OTP ROM size: 1K * 16-bit. (SN8P1602/1603)
RAM size: 48 * 8-bit. (SN8P1602/1603)
OTP ROM size: 4K * 16-bit. (SN8P1604)
RAM size: 128 * 8-bit. (SN8P1604)
♦
Two interrupt sources
One internal interrupt: TC0. (SN8P1602/ 1603)
One internal interrupt: TC1. (SN8P1604)
One external interrupt: INT0.
♦
I/O pin configuration
(SN8P1602/1603 14 pins, SN8P1604 22 pins)
Input only: P0
Bi-directional: P1, P2, P5
Wakeup: P0, P1
Pull-up resisters: P0, P1, P2, P5 (SN8P1604 only)
External interrupt: P0
♦
One channel 8-bits PWM or Buzzer output.
(SN8P1604 only)
♦
Dual clock system offers three operating modes
External high clock: RC type up to 10 MHz
External high clock: Crystal type up to 16 MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V)
Normal mode: Both high and low clock active
Slow mode: Low clock only
Sleep mode: Both high and low clock stop
♦
Package (Chip form support)
P-DIP18 (SN8P1602/ 1603)
SOP18 (SN8P1602/1603)
SSOP20 (SN8P1602/1603)
♦
♦
♦
♦
One 8-bit timer counters.
(TC1 for SN8P1604, TC0 for others)
On chip watchdog timer.
Four levels stack buffer.
56 powerful instructions
Four clocks per instruction cycle
All of instructions are one word length.
Most of instructions are one cycle only.
All ROM area lookup table function (MOVC)
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SKDIP28 (SN8P1604)
SOP28 (SN8P1604)
Page 9
Revision 1.94
SN8P1600
8-bit micro-controller
SYSTEM BLOCK DIAGRAM
SN8P1602/1603
SN8P1602/SN8P1603
H-OSC
PC
IR
Internal
RC
POR
ROM
FLAGS
TIMING GENERATOR
ALU
Watch
Dog
RAM
SYSTEM REGISTER
ACC
INTERRUPT
CONTROL
TIMER & COUNTER
PORT 0
PORT 1
PORT 2
SN8P1604
SN8P1604
H-OSC
PC
IR
Internal
RC
LDV
ROM
TIMING GENERATOR
FLAGS
ALU
Watch
Dog
RAM
SYSTEM REGISTER
ACC
INTERRUPT
CONTROL
TIMER & COUNTER
PORT 0
PORT 1
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PORT 2
PORT 5
Page 10
Revision 1.94
SN8P1600
8-bit micro-controller
PIN ASSIGNMENT
Part Number Description：
OTP Type: SN8P16XXY, MASK Type: SN8A16XXAY
Y = Q: QFP，P: PDIP，K: SKDIP，S: SOP，X: SSOP
OTP Type:
SN8P1602P / SN8P1603P (DIP 18 pins)
SN8P1602S / SN8P1603S (SOP 18 pins)
P1.2
P1.3
INT0/P0.0
RST
VSS
P2.0
P2.1
P2.2
P2.3
1
U
18 P1.1
2
17 P1.0
3
16 XIN
4
15 XOUT/P1.4
5
14 VDD
6
13 P2.7
7
12 P2.6
8
11 P2.5
9
10 P2.4
SN8P1602P OTP
SN8P1602S
SN8P1602X / SN8P1603X (SSOP 20 pins)
P1.2
P1.3
INT0/P0.0
RST
VSS
VSS
P2.0
P2.1
P2.2
P2.3
1
U
20 P1.1
2
19 P1.0
3
18 XIN
4
17 XOUT/P1.4
5
16 VDD
6
15 VDD
7
14 P2.7
8
13 P2.6
9
12 P2.5
10
11 P2.4
SN8P1602X OTP
MASK Type:
TEST
P_RESETB
PORT1[0]
PORT1[1]
XIN
XOUT
PORT0[0]
PORT1[2]
PORT1[3]
PORT2[0]
PORT2[1]
PORT2[2]
GND
SN8A1602A: Support dice form only
VDD
PORT2[3]
PORT2[4]
(0.00,0.00)
PORT2[5]
PORT2[6]
PORT2[7]
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Revision 1.94
SN8P1600
8-bit micro-controller
OTP Type:
SN8P1604K (SKDIP 28 pins)
SN8P1604S (SOP 28 pins)
P0.1
VDD
VPP/VDD
VSS
P0.0/INT0
P5.0
P5.1
P5.2
P5.3/BZ1/PWM1
P1.0
P1.1
P1.2
P1.3
P1.4
1
U 28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
SN8P1604K
SN8P1604S
RST
XIN
XOUT/Fcpu
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.7
P1.6
P1.5
P0.1
VDD
P0.2
VSS
P0.0/INT0
P5.0
P5.1
P5.2
P5.3/BZ1/PWM1
P1.0
P1.1
P1.2
P1.3
P1.4
1
U 28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
SN8A1604AK
SN8A1604AS
RST
XIN
XOUT/Fcpu
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.7
P1.6
P1.5
MASK Type:
SN8A1604AK (SKDIP 28 pins)
SN8A1604AS (SOP 28 pins)
Notice: Different pins between MASK and OTP:
Pin 3 of SN8A1604A is P0.2 but it is VPP in SN8P1604. Pull up P0.2 to VDD if no use to avoid extra power
consumption.
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Page 12
Revision 1.94
SN8P1600
8-bit micro-controller
PIN DESCRIPTIONS
SN8P1602/1603
PIN NAME
VDD, VSS
VPP/RST
XIN
XOUT/P1.4
P0.0 / INT0
P1.0 ~ P1.4
P2.0 ~ P2.7
TYPE
P
I
I
I/O
I
I/O
I/O
DESCRIPTION
Power supply input pins. Place the 0.1µF bypass capacitor between the VDD and VSS pin.
System reset pin. Schmitt trigger structure, low active, normal stay to “high”.
External oscillator input pin. RC mode input pin.
External oscillator output pin. In RC mode is P1.4 I/O.
Input / Interrupt (Schmitt trigger) / Wakeup function.
Bi-direction pins with sleep mode wakeup function.
Bi-direction pins.
Notice : The SN8P1602/3 do not have the pull-up resistor in the input port. The user must use the external pull-up
resistor.
SN8P1604
PIN NAME
VDD, VSS
VPP/VDD
RST
XIN
XOUT/Fcpu
P0.0/INT0
P0.1
P1.0 ~ P1.7
P2.0 ~ P2.7
P5.0 ~ P5.3
TYPE
P
P
I
I
I/O
I
I
I/O
I/O
I/O
DESCRIPTION
Power supply input pins. Place the 0.1µF bypass capacitor between the VDD and VSS pin.
OTP programming pin. Keep connect to VDD during normal mode.
System reset pin. Schmitt trigger structure, low active, normal stay to “high”.
External oscillator input pin. RC mode input pin.
External oscillator output pin. RC Mode as the Fcpu output
Input / Interrupt (Schmitt trigger) / Wakeup function / Built-in pull-up resisters.
Input / Wakeup function. / Built-in pull-up resister.
Bi-direction pins with sleep mode Wakeup function. Built-in pull-up resisters.
Bi-direction pins / Built-in pull-up resisters.
Bi-direction pin, P5.3 as TC1 output for PWM and Buzzer function/Built-in pull-up resisters.
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Page 13
Revision 1.94
SN8P1600
8-bit micro-controller
PIN CIRCUIT DIAGRAMS
SN8P1602/1603
Port1, 2 structure
PnM
Port0 structure
Pin
Latch
Int. bus
Pin
Int. bus
PnM
PnM
Note: All of the latch output circuits are push-pull structures.
SN8P1604
Port0 structure
Port1,2, 5 structure
PUR
PUR
PnM, Code Option
Code Option
Pin
PnM
Pin
Int. bus
Latch
Int. bus
PnM
PnM
Note: The internal pull-up resistor of the SN8P1604 can be enabled by the code option.
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Page 14
Revision 1.94
SN8P1600
8-bit micro-controller
2 CODE OPTION TABLE
SN8P1602
Code Option
High_Clk
High_Clk / 2
OSG
Watch_Dog
LVD
Security
Content
RC
32K X’tal
12M X’tal
4M X’tal
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Function Description
Low cost RC for external high clock oscillator
Low frequency, power saving crystal (e.g. 32.768K) for external high
clock oscillator
High speed crystal /resonator (e.g. 12M) for external high clock oscillator
Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator
External high clock divided by two, Fosc = high clock / 2
Fosc = high clock
Enable Oscillator Safe Guard function
Disable Oscillator Safe Guard function
Enable Watch Dog function
Disable Watch Dog function
Enable the low voltage detect
Disable the low voltage detect
Enable ROM code Security function
Disable ROM code Security function
SN8P1603----------The LVD always turn on to improve the power on reset and brownout reset performance
Code Option
High_Clk
High_Clk / 2
OSG
Watch_Dog
Security
Content
RC
32K X’tal
12M X’tal
4M X’tal
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
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Function Description
Low cost RC for external high clock oscillator
Low frequency, power saving crystal (e.g. 32.768K) for external high
clock oscillator
High speed crystal /resonator (e.g. 12M) for external high clock oscillator
Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator
External high clock divided by two, Fosc = high clock / 2
Fosc = high clock
Enable Oscillator Safe Guard function
Disable Oscillator Safe Guard function
Enable Watch Dog function
Disable Watch Dog function
Enable ROM code Security function
Disable ROM code Security function
Page 15
Revision 1.94
SN8P1600
8-bit micro-controller
3 ADDRESS SPACES
PROGRAM MEMORY (ROM)
OVERVIEW
The SN8P1600 provides the program memory up to 1024 * 16-bit (4096 *16-bit for SN8P1604) to be addressed and is
able to fetch instructions through 10-bit wide PC (Program Counter). It can look up ROM data by using ROM code
registers (R, Y, Z).
1-word reset vector addresses
1-word interrupt vector addresses
1K words general purpose area (SN8P1602/1603)
4K words general purpose area (SN8P1604)
5-words reserved area
All of the program memory is partitioned into three coding areas. The 1st area is located from 00H to 03H(The Reset
vector area), the 2nd area is a reserved area 04H ~07H, the 3rd area is for the interrupt vector and the user code area
from 0008H to 0FFEH. The address 08H is the interrupt enter address point.
SN8P160 SN8P1602/SN8P160
4
3
0000H
0000H
0001H
0001H
0002H
0002H
0003H
0003H
0004H
0004H
0005H
0005H
0006H
0006H
0007H
0007H
0008H
0008H
0009H
0009H
.
.
.
.
000FH
000FH
0010H
0010H
0011H
0011H
.
.
.
.
0FFEH
03FEH
0FFFH
03FFH
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ROM
Reset vector
General purpose area
User reset vector
Jump to user start address
Jump to user start address
Jump to user start address
Reserved
Interrupt vector
User interrupt vector
User program
General purpose area
End of user program
Reserved
Page 16
Revision 1.94
SN8P1600
8-bit micro-controller
USER RESET VECTOR ADDRESS (0000H)
A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset,
then the chip will restart the program from address 0000h and all system registers will be set as default values. The
following example shows the way to define the reset vector in the program memory.
Example: After power on reset, external reset active or reset by watchdog timer overflow.
CHIP SN8P1602
ORG
JMP
.
0
START
ORG
10H
START:
; 0000H
; Jump to user program address.
; 0004H ~ 0007H are reserved
; 0010H, The head of user program.
; User program
.
.
.
.
ENDP
; End of program
INTERRUPT VECTOR ADDRESS (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Example 1: This demo program includes interrupt service routine and the user program is behind the
interrupt service routine.
CHIP SN8P1602
.DATA
.CODE
PFLAGBUF
ORG
JMP
.
0
START
; 0000H
; Jump to user program address.
; 0004H ~ 0007H are reserved
ORG
B0XCH
B0MOV
B0MOV
.
.
B0MOV
B0MOV
B0XCH
RETI
8
A, ACCBUF
A, PFLAG
PFLAGBUF, A
; Interrupt service routine
; B0XCH doesn’t change C, Z flag
A, PFLAGBUF
PFLAG, A
A, ACCBUF
START:
.
.
JMP
; Save PFLAG register in a buffer
; Restore PFLAG register from buffer
; B0XCH doesn’t change C, Z flag
; End of interrupt service routine
; The head of user program.
; User program
START
ENDP
SONiX TECHNOLOGY CO., LTD
; End of user program
; End of program
Page 17
Revision 1.94
SN8P1600
8-bit micro-controller
Example 2: The demo program includes interrupt service routine and the address of interrupt service
routine is in a special address of general-purpose area.
CHIP SN8P1602
.DATA
.CODE
PFLAGBUF
ORG
JMP
.
0
START
ORG
JMP
08
MY_IRQ
ORG
10H
START:
.
.
.
JMP
; 0008H, Jump to interrupt service routine address
; 0010H, The head of user program.
; User program
START
MY_IRQ:
B0XCH
B0MOV
B0MOV
.
.
B0MOV
B0MOV
B0XCH
RETI
; 0000H
; Jump to user program address.
; 0001H ~ 0007H are reserved
A, ACCBUF
A, PFLAG
PFLAGBUF, A
A, PFLAGBUF
PFLAG, A
A, ACCBUF
ENDP
; End of user program
;The head of interrupt service routine
; B0XCH doesn’t change C, Z flag
; Save PFLAG register in a buffer
; Restore PFLAG register from buffer
; B0XCH doesn’t change C, Z flag
; End of interrupt service routine
; End of program
Remark: It is easy to get the rules of SONIX program from demo programs given above. These points are
as following.
1. The address 0000H is a “JMP” instruction to make the program go to general-purpose ROM area. The
0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and
necessary.
2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H
(Example1) or to put a “JMP” instruction in 0008H then place the interrupt service routine in other
general-purpose ROM area (Example2) to get more modularized coding style.
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SN8P1600
8-bit micro-controller
CHECKSUM CALCULATION
The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses
(0004H~0007H and last address) when calculate the Checksum value.
Example:
The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of
user’s code
MOV
A,#END_USER_CODE$L
B0MOV
END_ADDR1,A
;save low end address to end_addr1
MOV
A,#END_USER_CODE$
M
B0MOV
END_ADDR2,A
;save middle end address to end_addr2
CLR
Y
;set Y to ooH
CLR
Z
;set Z to 00H
@@:
CALL
MOVC
B0BSET
ADD
MOV
ADC
JMP
YZ_CHECK
FC
DATA1,A
A,R
DATA2,A
END_CHECK
INCMS
JMP
JMP
Z
@B
Y_ADD_1
MOV
CMPRS
JMP
MOV
CMPRS
JMP
JMP
A,END_ADDR1
A,Z
AAA
A,END_ADDR2
A,Y
AAA
CHECKSUM_END
MOV
CMPRS
RET
MOV
CMPRS
RET
INCMS
INCMS
INCMS
INCMS
RET
A,#04H
A,Z
;call function of check yz value
;
;clear C glag
;add A to Data1
;add R to Data2
;check if the YZ address =
the end of code
AAA:
;Z=Z+1
;if Z!= 00H calculate to next address
;if Z=00H increase Y
END_CHECK:
;check if Z = low end address
;if Not jump to checksum calculate
;if Yes, check if Y = middle end address
;if Not jump to checksum calculate
;if Yes checksum calculated is done.
;check if YZ=0004H
YZ_CHECK:
;check if Z=04H
;if Not return to checksum calculate
A,#00H
A,Y
;if Yes, check if Y=00H
;if Not return to checksum calculate
;if Yes, increase 4 to Z
Z
Z
Z
Z
;set YZ=0008H then return
Y_ADD_1:
INCMS
NOP
JMP
Y
;increase Y
@B
;jump to checksum calculate
CHECKSUM_END:
……….
……….
END_USER_CODE:
SONiX TECHNOLOGY CO., LTD
;Label of program end
Page 19
Revision 1.94
SN8P1600
8-bit micro-controller
GENERAL PURPOSE PROGRAM MEMORY AREA
The 1017/4089-word at ROM locations 0009H~03FEH/0FFEH are used as general-purpose memory. The area is
stored instruction’s op-code and look-up table data. The SN8P1600 includes jump table function by using program
counter (PC) and look-up table function by using ROM code registers (R, Y, Z).
The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table
function and look-up table function, the program counter can’t leap over the boundary by program counter
automatically. Users need to modify the PCH value to “PCH+1” when the PCL overflows (from 0FFH to 000H).
LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to the bit 8~bit 15 and Z register to the bit 0~bit 7 data of ROM
address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data
stored in R register.
Example: To look up the ROM data located “TABLE1”.
@@:
TABLE1:
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INCMS
JMP
INCMS
NOP
Z
@F
Y
MOVC
.
DW
DW
DW
.
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
;
; Increment the index address for next address
; Z+1
; Not overflow
; Z overflow (FFH
00),
Y=Y+1
; Not overflow
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
;“
;“
CAUSION: The Y register can't increase automatically if Z register cross boundary from 0xFF to 0x00.
Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y
register must be added one. The following INC_YZ macro shows a simple method to process Y and Z
registers automatically.
Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users
can omit “B0MOV X, #TABLE1$H”. SONiX ICE support more larger program memory addressing
capability. So make sure X register is “0” to avoid unpredicted error in loop-up table operation.
Example: INC_YZ Macro
INC_YZ
MACRO
INCMS
JMP
INCMS
NOP
Z
@F
; Z+1
; Not overflow
Y
; Y+1
; Not overflow
@@:
ENDM
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer
following example for detailed information:
Example: Increase Y and Z register by B0ADD/ADD instruction
B0MOV
B0MOV
Y, #TABLE1$M
Z, #TABLE1$L
; To set lookup table’s middle address.
; To set lookup table’s low address.
B0MOV
B0ADD
A, BUF
Z, A
; Z = Z + BUF.
B0BTS1
JMP
INCMS
NOP
FC
GETDATA
Y
; Check the carry flag.
; FC = 0
; FC = 1. Y+1.
.
0035H
5105H
2012H
;
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
.
.
;
; To define a word (16 bits) data.
;“
;“
GETDATA:
MOVC
TABLE1:
.
DW
DW
DW
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SN8P1600
8-bit micro-controller
JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The
way is easy to make a multi-stage program.
When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump
table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table
leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program
memory page (xx00H). Here one page mean 256 words.
Example :
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
JMP
JMP
JMP
JMP
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
; PCL = PCL + ACC, the PCH can’t be changed.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump
table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one
automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will
point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table
crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM
boundary (e.g. 0100H).
Example: If “jump table” crosses over ROM boundary will cause errors.
ROM Address
.
.
.
0X00FD
0X00FE
0X00FF
0X0100
0X0101
.
.
.
.
.
B0ADD
JMP
JMP
JMP
JMP
.
.
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
; PCL = PCL + ACC, the PCH can’t be changed.
; ACC = 0
; ACC = 1
; ACC = 2
jump table cross boundary here
; ACC = 3
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
@JMP_A
MACRO
IF
JMP
ORG
ENDIF
ADD
ENDM
VAL
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
($ | 0XFF)
($ | 0XFF)
PCL, A
Note: “VAL” is the number of the jump table listing number.
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SN8P1600
8-bit micro-controller
Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; If ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h.
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SN8P1600
8-bit micro-controller
DATA MEMORY (RAM)
OVERVIEW
The SN8P1600 has internally built-in data memory up to 48/128 bytes for storing the general-purpose data.
48 * 8-bit general purpose area in bank 0 (SN8P1602/1603)
128 * 8-bit general purpose area in bank 0 (SN8P1604)
128 * 8-bit system register area
The memory is separated into bank 0. The bank 0 uses the first 48/128 bytes as general-purpose area, and the
remaining 128 bytes as system register.
SN8P1604 SN8P1602/SN
8P1603
000h
000h
“
“
“
“
“
“
“
“
“
“
07Fh
02Fh
BANK 0
080h
080h
“
“
“
“
“
“
“
“
“
“
0FFh
0FFh
SONiX TECHNOLOGY CO., LTD
RAM location
000h~02FH/07FH of Bank 0 store
general-purpose data (48 bytes
/128bytes).
General purpose area
080h~0FFh of Bank 0 store system
registers (128 bytes).
System register
End of bank 0 area
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SN8P1600
8-bit micro-controller
WORKING REGISTERS
The RAM bank0 locations 82H to 84H store the specially defined registers such as register R, Y, Z, respectively shown
in the following table. These registers can use as the general-purpose working buffer or access ROM’s and RAM’s
data. For instance, all of the ROM table can be looked-up by R, Y and Z registers. The data of RAM memory can be
indirectly accessed with Y and Z registers.
Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. First, Y and Z registers
can be used as working registers. Second, these two registers can be used as data pointers for @YZ register. Third,
the registers can address ROM location to look up ROM data.
084H
Y
Read/Write
After reset
Bit 7
YBIT7
R/W
0
Bit 6
YBIT6
R/W
0
Bit 5
YBIT5
R/W
0
Bit 4
YBIT4
R/W
0
Bit 3
YBIT3
R/W
0
Bit 2
YBIT2
R/W
0
Bit 1
YBIT1
R/W
0
Bit 0
YBIT0
R/W
0
083H
Z
Read/Write
After reset
Bit 7
ZBIT7
R/W
0
Bit 6
ZBIT6
R/W
0
Bit 5
ZBIT5
R/W
0
Bit 4
ZBIT4
R/W
0
Bit 3
ZBIT3
R/W
0
Bit 2
ZBIT2
R/W
0
Bit 1
ZBIT1
R/W
0
Bit 0
ZBIT0
R/W
0
The @YZ that is data point_1 index buffer located at address 0E7H in RAM bank 0. It employs Y and Z registers to
addressing RAM location to read/write data through ACC. The Lower 4-bit of Y register points to RAM bank number
and Z register to RAM address number, respectively. The higher 4-bit data of Y register is truncated in RAM indirectly
access mode.
Example: Following example uses indirectly addressing mode to access data in the RAM address 025H of
bank0.
B0MOV
B0MOV
B0MOV
Y, #00H
Z, #25H
A, @YZ
; To set RAM bank 0 for Y register
; To set location 25H for Z register
; To read a data into ACC
Example: Clear general-purpose data memory area of bank 0 using @YZ register.
B0MOV
B0MOV
Y, #0
Z, #07FH
; Y = 0, bank 0
; Z = 7FH, the last address of the data memory area
CLR
@YZ
; Clear @YZ to be zero
DECMS
JMP
Z
CLR_YZ_BUF
; Z – 1, if Z= 0, finish the routine
; Not zero
CLR
@YZ
CLR_YZ_BUF:
END_CLR:
; End of clear general purpose data memory area of bank 0
.
Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about Y, Z register look-up table application.
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SN8P1600
8-bit micro-controller
R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register. First, R register can be used as working
register. Second, the R register stores high-byte data of look-up ROM data. After MOVC instruction executed, the
high-byte data of specified ROM address will store in R register and the low-byte data in ACC.
082H
R
Read/Write
After reset
Bit 7
RBIT7
R/W
0
Bit 6
RBIT6
R/W
0
Bit 5
RBIT5
R/W
0
Bit 4
RBIT4
R/W
0
Bit 3
RBIT3
R/W
0
Bit 2
RBIT2
R/W
0
Bit 1
RBIT1
R/W
0
Bit 0
RBIT0
R/W
0
Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
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SN8P1600
8-bit micro-controller
PROGRAM FLAG
The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there
is carry, borrow occurrence, then these flags will be set to PFLAG register.
086H
PFLAG
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
CARRY FLAG
C = 1: When executed arithmetic addition with overflow or executed arithmetic subtraction without borrow or executed
rotation instruction with logic “1” shifting out.
C = 0: When executed arithmetic addition without overflow or executed arithmetic subtraction with borrow or executed
rotation instruction with logic “0” shifting out.
DECIMAL CARRY FLAG
DC = 1: If executed arithmetic addition with overflow of low nibble or executed arithmetic subtraction without borrow of
low nibble.
DC = 0: If executed arithmetic addition without overflow of low nibble or executed arithmetic subtraction with borrow of
low nibble.
ZERO FLAG
Z = 1: When the content of ACC or target memory is zero after executing instructions involving a zero flag.
Z = 0: When the content of ACC or target memory is not zero after executing instructions involving a zero flag.
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SN8P1600
8-bit micro-controller
ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
Example: Read and write ACC value.
; Read ACC data and store in BUF data memory
MOV
BUF, A
.
.
; Write a immediate data into ACC
MOV
A, #0FH
; Write ACC data from BUF data memory
MOV
A, BUF
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be exchanged
to other data memories defined by users. Thus, once interrupt occurs, these data must be stored in the data memory
based on the user’s program as follows.
Example: Protect ACC and working registers.
ACCBUF
PFLAGBUF
EQU
EQU
00H
01H
; ACCBUF is ACC data buffer.
; PFLAGBUF is PFLAG data buffer.
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF,A
; Store ACC value
; Store PFLAG value
.
.
.
.
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG,A
A, ACCBUF
INT_SERVICE:
RETI
; Re-load PFLAG value
; Re-load ACC
; Exit interrupt service vector
Note: To save and re-load ACC data must be used “B0XCH” instruction, or the PFLAG value maybe
modified by ACC.
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SN8P1600
8-bit micro-controller
STACK OPERATIONS
OVERVIEW
The stack buffer of SN8P1600 has 4-level high area and each level is 10-bit length. These buffers are designed to
push and pop up program counter’s (PC) data when interrupt service routine is executed. The STKP register is a
pointer designed to point active level in order to push or pop up data from stack buffer of kernel circuit. The STKnH and
STKnL are the 10-bit stack buffers to store program counter (PC) data.
RET /
CALL /
RETI
interrupt
PCH
PCL
STK3H
STK3L
STKP = 3
STKP + 1
STKP - 1
STK2L
STK2H
STKP = 2
STKP
STKP
STK1H
STK1L
STK0H
STK0L
STKP = 1
STKP = 0
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SN8P1600
8-bit micro-controller
STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 10-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack and reading from the top of stack. Push operation
decrements the STKP and the pop operation increments each time. That makes the STKP always point to the top
address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0DFH
STKP
Read/Write
After reset
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
STKPBn: Stack pointer. (n = 0 ~ 2)
GIE: Global interrupt control bit. 0 = disable, 1 = enable. There is more on this in interrupt chapter.
Example: Stack pointer (STKP) reset routine.
MOV
B0MOV
A, #00000111B
STKP, A
STKn = <STKnH , STKnL> (n = 3 ~ 0)
SN8P1602/1603
0F0H~0FFH
Bit 7
STKnH
Read/Write
After reset
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
SnPC9
R/W
0
Bit 0
SnPC8
R/W
0
SN8P1604
0F0H~0FFH
Bit 7
STKnH
Read/Write
After reset
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
SnPC11
R/W
0
Bit 2
SnPC10
R/W
0
Bit 1
SnPC9
R/W
0
Bit 0
SnPC8
R/W
0
Bit 5
SnPC5
R/W
0
Bit 4
SnPC4
R/W
0
Bit 3
SnPC3
R/W
0
Bit 2
SnPC2
R/W
0
Bit 1
SnPC1
R/W
0
Bit 0
SnPC0
R/W
0
SN8P1602/1603/1604
0F0H~0FFH
Bit 7
Bit 6
SnPC7
SnPC6
STKnL
Read/Write
R/W
R/W
After reset
0
0
STKnH: Store PCH data as interrupt or call executing. The n expressed 0 ~3.
STKnL: Store PCL data as interrupt or call executing. The n expressed 0 ~3.
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SN8P1600
8-bit micro-controller
STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
0
1
2
3
4
>4
STKPB2
STKP Register
STKPB1
STKPB0
1
1
1
1
0
0
1
1
0
0
1
1
Stack Buffer
High Byte Low Byte
1
0
1
0
1
0
Free
STK0H
STK1H
STK2H
STK3H
-
Free
STK0L
STK1L
STK2L
STK3L
-
Description
Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
4
3
2
1
0
STKPB2
STKP Register
STKPB1
STKPB0
0
1
1
1
1
SONiX TECHNOLOGY CO., LTD
1
0
0
1
1
Stack Buffer
High Byte Low Byte
1
0
1
0
1
STK3H
STK2H
STK1H
STK0H
Free
Page 31
STK3L
STK2L
STK1L
STK0L
Free
Description
-
Revision 1.94
SN8P1600
8-bit micro-controller
PROGRAM COUNTER
The program counter (PC) is a 10-bit binary counter separated into the high-byte 2 bits and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL
instruction is executed, the destination address will be inserted to bit 0 ~ bit 9.
SN8P1602/SN8P1603
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
PC9
PC
After
0
reset
PCH
SN8P1604
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
PC11 PC10 PC9
PC
After
0
0
0
reset
PCH
SONiX TECHNOLOGY CO., LTD
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
0
0
0
0
0
0
0
0
0
PCL
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
0
0
0
0
0
0
0
0
0
Page 32
PCL
Revision 1.94
SN8P1600
8-bit micro-controller
ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is matched, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is matched, the PC will add 2 steps to skip next instruction.
FC
C0STEP
; To skip, if Carry_flag = 1
; Else jump to C0STEP.
C0STEP:
B0BTS1
JMP
.
NOP
A, BUF0
FZ
C1STEP
; Move BUF0 value to ACC.
; To skip, if Zero flag = 0.
; Else jump to C1STEP.
C1STEP:
B0MOV
B0BTS0
JMP
.
NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
C0STEP:
CMPRS
JMP
.
NOP
A, #12H
C0STEP
; To skip, if ACC = 12H.
; Else jump to C0STEP.
If the result after increasing or decreasing by 1 is 0xFF or 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
C0STEP:
INCS
JMP
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
INCMS
JMP
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
DECS
JMP
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
DECMS
JMP
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
INCMS instruction:
C0STEP:
DECS instruction:
C0STEP:
DECMS instruction:
C0STEP:
SONiX TECHNOLOGY CO., LTD
Page 33
Revision 1.94
SN8P1600
8-bit micro-controller
MULTI-ADDRESS JUMPING
Users can jump round multi-address by either JMP instruction or ADD M, An instruction (M = PCL) to activate
multi-address jumping function. If carry flag occurs after execution of ADD PCL, A, the carry flag will not affect PCH
register.
Example: If PC = 0323H
(PCH = 03H、PCL = 23H)
; PC = 0323H
; PC = 0328H
MOV
B0MOV
.
.
.
MOV
B0MOV
Example: If PC = 0323H
A, #28H
PCL, A
.
.
.
A, #00H
PCL, A
; Jump to address 0328H
; Jump to address 0300H
(PCH = 03H、PCL = 23H)
; PC = 0323H
B0ADD
JMP
JMP
JMP
JMP
.
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
.
SONiX TECHNOLOGY CO., LTD
; PCL = PCL + ACC, the PCH cannot be changed.
; If ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
;
Page 34
Revision 1.94
SN8P1600
8-bit micro-controller
4 ADDRESSING MODE
OVERVIEW
The SN8P1600 provides three addressing modes to access RAM data, including immediate addressing mode, directly
addressing mode and indirectly address mode. The main purpose of the three different modes is described in the
following table.
IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location (“ MOV A, # I ”, “ B0MOV M, # I “) in
ACC or specific RAM.
Immediate addressing mode
MOV
A, #12H
; To set an immediate data 12H into ACC
DIRECTLY ADDRESSING MODE
The directly addressing mode uses address number to access memory location (“ MOV A,12H ”, “ MOV 12H, A ”).
Directly addressing mode
B0MOV
A, 12H
; To get a content of location 12H of bank 0 and save in ACC
INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to set up an address in data pointer registers (Y/Z) and uses MOV instruction to
read/write data between ACC and @YZ register (“ MOV A,@YZ ”, “ MOV @YZ, A ”).
Example: Indirectly addressing mode with @YZ register
CLR
B0MOV
B0MOV
Y
Z, #12H
A, @YZ
SONiX TECHNOLOGY CO., LTD
; To clear Y register to access RAM bank 0.
; To set an immediate data 12H into Z register.
; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
Page 35
Revision 1.94
SN8P1600
8-bit micro-controller
5 SYSTEM REGISTER
OVERVIEW
The RAM area located in 80H~FFH bank 0 is system register area. The main purpose of system registers is to control
peripheral hardware of the chip. Using system registers can control I/O ports, timers and counters by programming.
The memory map provides an easy and quick reference source for writing application program. These system registers
accessing is controlled by the selected memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV,
B0BSET, B0BCLR…).
SYSTEM REGISTER ARRANGEMENT (BANK 0)
BYTES of SYSTEM REGISTER
SN8P1602/1603
0
1
2
8
9
A
B
C
D
E
F
3
4
5
6
7
8
9
A
B
C
D
E
F
-
-
R
Z
Y
-
PFLAG
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1W
P1M
P2M
-
-
-
-
-
P0
P1
P2
-
-
-
-
-
-
-
-
-
-
-
-
@YZ
-
-
-
-
-
-
-
-
2
3
4
5
6
7
8
9
A
B
C
D
E
F
SN8P1604
0
1
8
9
A
B
C
D
E
F
INTRQ INTEN
OSCM
-
-
-
PCL
PCH
-
-
TC0M
TC0C
-
-
-
STKP
-
-
-
-
-
-
-
-
STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
-
-
R
Z
Y
-
PFLAG
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P1W
P1M
P2M
-
-
P5M
-
-
OSCM
-
-
-
PCL
PCH
P0
P1
P2
-
-
P5
-
-
-
-
-
-
TC1M
TC1C
TC1R
STKP
-
-
-
-
-
-
-
@YZ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INTRQ INTEN
STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
Description
PFLAG =
P1W =
PnM =
INTRQ =
OSCM =
TCnM =
STKP =
@YZ =
ROM page and special flag register.
Port 1 Wakeup register.
Port n input/output mode register.
Interrupt request register.
Oscillator mode register.
Timer n mode register.
Stack pointer buffer.
RAM YZ indirect addressing index pointer.
R=
Y, Z =
Pn =
INTEN =
PCH, PCL =
TCnC =
TC1R=
STK0~STK3 =
Working register and ROM look-up data buffer.
Working, @YZ and ROM addressing register.
Port n data buffer.
Interrupt enable register.
Program counter.
Timer n counting register.
TC1 8-bit reload register.
Stack 0 ~ stack 3 buffer.
Note:
a). All register names had been declared in SN8ASM assembler.
b). 1-bit register name had been declared in SN8ASM assembler with “F” prefix code.
c). When using instruction to check empty location, logic “H” will be returned.
d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.
SONiX TECHNOLOGY CO., LTD
Page 36
Revision 1.94
SN8P1600
8-bit micro-controller
BITS of SYSTEM REGISTER
SN8P1602/1603 system register table
Address
082H
083H
084H
086H
0C0H
0C1H
0C2H
0C8H
0C9H
0CAH
0CEH
0CFH
0D0H
0D1H
0D2H
0DAH
0DBH
0DFH
0E7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
0FFH
Bit7
RBIT7
ZBIT7
YBIT7
0
0
P27M
0
0
0
PC7
P27
TC0ENB
TC0C7
GIE
@YZ7
S3PC7
S2PC7
S1PC7
S0PC7
-
Bit6
RBIT6
ZBIT6
YBIT6
0
0
P26M
0
0
WDRST
PC6
P26
TC0rate2
TC0C6
@YZ6
S3PC6
S2PC6
S1PC6
S0PC6
-
Bit5
RBIT5
ZBIT5
YBIT5
0
0
P25M
TC0IRQ
TC0IEN
0
PC5
P25
TC0rate1
TC0C5
@YZ5
S3PC5
S2PC5
S1PC5
S0PC5
-
Bit4
RBIT4
ZBIT4
YBIT4
P14W
P14M
P24M
0
0
0
PC4
P14
P24
TC0rate0
TC0C4
@YZ4
S3PC4
S2PC4
S1PC4
S0PC4
-
Bit3
RBIT3
ZBIT3
YBIT3
P13W
P13M
P23M
0
0
CPUM0
PC3
P13
P23
0
TC0C3
@YZ3
S3PC3
S2PC3
S1PC3
S0PC3
-
Bit2
RBIT2
ZBIT2
YBIT2
C
P12W
P12M
P22M
0
0
CLKMD
PC2
P12
P22
0
TC0C2
STKPB2
@YZ2
S3PC2
S2PC2
S1PC2
S0PC2
-
Bit1
RBIT1
ZBIT1
YBIT1
DC
P11W
P11M
P21M
0
0
STPHX
PC1
PC9
P11
P21
0
TC0C1
STKPB1
@YZ1
S3PC1
S3PC9
S2PC1
S2PC9
S1PC1
S1PC9
S0PC1
S0PC9
Bit0
RBIT0
ZBIT0
YBIT0
Z
P10W
P10M
P20M
P00IRQ
P00IEN
0
PC0
PC8
P00
P10
P20
0
TC0C0
STKPB0
@YZ0
S3PC0
S3PC8
S2PC0
S2PC8
S1PC0
S1PC8
S0PC0
S0PC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
R
Z
Y
PFLAG
P1W wakeup register
P1M I/O direction
P2M I/O direction
INTRQ
INTEN
OSCM
PCL
PCH
P0 data buffer
P1 data buffer
P2 data buffer
TC0M
TC0C
STKP stack pointer
@YZ index pointer
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
SN8P1604 system register table
Address
082H
083H
084H
086H
0C0H
0C1H
0C2H
0C5H
0C8H
0C9H
0CAH
0CEH
0CFH
0D0H
0D1H
0D2H
0D5H
0DCH
0DDH
0DEH
0DFH
0E7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
0FFH
Bit7
RBIT7
ZBIT7
YBIT7
P17W
P17M
P27M
0
0
0
0
PC7
P17
P27
TC1ENB
TC1C7
TC1R7
GIE
@YZ7
S3PC7
S2PC7
S1PC7
S0PC7
-
Bit6
RBIT6
ZBIT6
YBIT6
P16W
P16M
P26M
0
TC1IRQ
TC1IEN
WDRST
PC6
P16
P26
TC1rate2
TC1C6
TC1R6
@YZ6
S3PC6
S2PC6
S1PC6
S0PC6
-
Bit5
RBIT5
ZBIT5
YBIT5
P15W
P15M
P25M
0
0
0
0
PC5
P15
P25
TC1rate1
TC1C5
TC1R5
@YZ5
S3PC5
S2PC5
S1PC5
S0PC5
-
Bit4
RBIT4
ZBIT4
YBIT4
P14W
P14M
P24M
0
0
0
0
PC4
P14
P24
TC1rate0
TC1C4
TC1R4
@YZ4
S3PC4
S2PC4
S1PC4
S0PC4
-
Bit3
RBIT3
ZBIT3
YBIT3
P13W
P13M
P23M
P53M
0
0
CPUM0
PC3
PC11
P13
P23
P53
0
TC1C3
TC1R3
@YZ3
S3PC3
S3PC11
S2PC3
S2PC11
S1PC3
S1PC11
S0PC3
S0PC11
Bit2
RBIT2
ZBIT2
YBIT2
C
P12W
P12M
P22M
P52M
0
0
CLKMD
PC2
PC10
P12
P22
P52
ALOAD1
TC1C2
TC1R2
STKPB2
@YZ2
S3PC2
S3PC10
S2PC2
S2PC10
S1PC2
S1PC10
S0PC2
S0PC10
Bit1
RBIT1
ZBIT1
YBIT1
DC
P11W
P11M
P21M
P51M
0
0
STPHX
PC1
PC9
P01
P11
P21
P51
TC1OUT
TC1C1
TC1R1
STKPB1
@YZ1
S3PC1
S3PC9
S2PC1
S2PC9
S1PC1
S1PC9
S0PC1
S0PC9
Bit0
RBIT0
ZBIT0
YBIT0
Z
P10W
P10M
P20M
P50M
P00IRQ
P00IEN
0
PC0
PC8
P00
P10
P20
P50
PWM1OUT
TC1C0
TC1R0
STKPB0
@YZ0
S3PC0
S3PC8
S2PC0
S2PC8
S1PC0
S1PC8
S0PC0
S0PC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
R
Z
Y
PFLAG
P1W wakeup register
P1M I/O direction
P2M I/O direction
P5M I/O direction
INTRQ
INTEN
OSCM
PCL
PCH
P0 data buffer
P1 data buffer
P2 data buffer
P5 data buffer
TC1M
TC1C
TC1R
STKP stack pointer
@YZ index pointer
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
Note: 1)To avoid system error, please be sure to put all the “0” as it indicates in the above table
2). For detail description please refer file of “System Register Quick Reference Table”
SONiX TECHNOLOGY CO., LTD
Page 37
Revision 1.94
SN8P1600
8-bit micro-controller
6 POWER ON RESET
OVERVIEW
SN8P1600 provides two system resets. One is external reset and the other is low voltage detector (LVD). The external
reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built-in internal circuit. When
one of the reset devices occurs, the system will reset and the system registers become initial value. The timing
diagram is as the following.
VDD
LVD Detect Level
External Reset
External Reset Detect Level
LVD
End of LVD Reset
Internal Reset Signal
End of External Reset
SN8P1600 power on reset timing diagram
Notice : The working current of the LVD is about 100uA.
SONiX TECHNOLOGY CO., LTD
Page 38
Revision 1.94
SN8P1600
8-bit micro-controller
EXTERNAL RESET DESCRIPTION
The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the
voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system
operation. It is necessary that the VDD must be stable.
VDD
External Reset
External Reset Detect Level
Internal Reset Signal
System Reset
End of External Reset
The external reset will fail, if the external reset voltage stabilizes before VDD voltage. Users must make sure the VDD
is stable earlier than external reset. The external reset circuit is a simple RC circuit as the following figure.
R
VDD
20K ohm
RST
C
0.1uF
MCU
VSS
VCC
GND
SONiX TECHNOLOGY CO., LTD
Page 39
Revision 1.94
SN8P1600
8-bit micro-controller
In power-fail condition as Brown-out reset. The reset pin may keep high level but the VDD is low voltage. That makes
the system reset fail and chip error. To connect a diode from reset pin to VDD is a good solution. This circuit can force
the capacitor to release electrical charge and drop the voltage, and solve the error.
R
DIODE
VDD
20K ohm
RST
C
0.1uF
MCU
VSS
VCC
GND
LOW VOLTAGE DETECTOR (LVD) DESCRIPTION
The LVD is a low voltage detector. It detects VDD level and reset the system as the VDD lower than the desired
voltage. The detect level is 2.4V. If the VDD lower than 2.4V, the system resets. The LVD function is controlled by code
option. Users can turn on it for special application like power-fail condition. LVD work with external reset function. They
are OR active.
VDD
LVD Detect Level
LVD
System Reset
End of LVD Reset
The LVD can protect system to work well under Brown-out reset, but it is a high consumptive circuit. In 3V condition,
the LVD consumes about 100uA. It is a very large consumption for battery system, but supports AC system well.
Note: LVD is enabled by code option.
SONiX TECHNOLOGY CO., LTD
Page 40
Revision 1.94
SN8P1600
8-bit micro-controller
7 OSCILLATORS
OVERVIEW
The SN8P1600 highly performs the dual clock micro-controller system. The dual clocks are high-speed clock and
low-speed clock. The high-speed clock frequency is supplied through the external oscillator circuit. The low-speed
clock frequency is supplied through on-chip RC oscillator circuit.
The external high-speed clock and the internal low-speed clock can be system clock (Fosc). The system clock is
divided by 4 to be the instruction cycle (Fcpu).
Fcpu = Fosc / 4
The system clock is required by the following peripheral modules:
Timer 0 (TC0)
Watchdog timer
CLOCK BLOCK DIAGRAM
HXRC(1:0) is code option
•00= RC
•01 =32 Khz Oscillator
•10 = High Speed Oscillator (>10Mhz)
•11 = Standard Oscillator (4Mhz)
STPHX
Divided by 2
1 : Disable
HXRC
CLKMD
fosc/4
CPUM0
0 : Enable
XIN
HXOSC.
fh
XOUT
OSG
Divided by 2
Divided by 4
fcpu
OSG : Oscillator Safe Guard
CPUM0
LXOSC.
1 : Disable -- System Default
fl
0 : Enable
CPUM0
HXOSC: External high-speed clock.
LXOSC: Internal low-speed clock.
OSG: Oscillator safe guard.
SONiX TECHNOLOGY CO., LTD
Page 41
Revision 1.94
SN8P1600
8-bit micro-controller
OSCM REGISTER DESCRIPTION
The OSCM register is an oscillator control register. It controls oscillator selection, system mode, watchdog timer clock
rate.
0CAH
OSCM
Read/Write
After reset
Bit 7
0
-
Bit 6
WDRST
R/W
0
Bit 5
0
-
Bit 4
0
-
Bit 3
CPUM0
R/W
0
Bit 2
CLKMD
R/W
0
Bit 1
STPHX
R/W
0
Bit 0
0
-
STPHX: Eternal high-speed oscillator control bit. 0 = free run, 1 = stop. This bit only controls external high-speed
oscillator. If STPHX=1, the internal low-speed RC oscillator is still running.
CLKMD: System high/Low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode.
CPUM0: CPU operating mode control bit. 0 = normal, 1 = sleep (power down) mode to turn off both high/low clock.
WDRST is watchdog timer control bits. The detail information is in watchdog timer chapter.
Note: The bit 0, 4, 7 of OSCM register must be “0”, or the system will be error.
SONiX TECHNOLOGY CO., LTD
Page 42
Revision 1.94
SN8P1600
8-bit micro-controller
EXTERNAL HIGH-SPEED OSCILLATOR
SN8P1600 can be operated in four different oscillator modes. There are external RC oscillator modes, high
crystal/resonator mode (12M code option), standard crystal/resonator mode (4M code option) and low crystal mode
(32K code option). For different application, the users can select one of satiable oscillator mode by programming code
option to generate system high-speed clock source after reset.
Example: Stop external high-speed oscillator.
B0BSET
FSTPHX
; To stop external high-speed oscillator only.
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; Oscillator called power down mode (sleep mode).
OSCILLATOR MODE CODE OPTION
SN8P1600 has four oscillator modes for different applications. These modes are 4M, 12M, 32K and RC. The main
purpose is to support different oscillator types and frequencies. MCU needs more current when operating at
High-speed mode than the low-speed mode. For crystals, there are three steps to select. If the oscillator is RC type, to
select “RC” and the system will divide the frequency by 2 automatically. User can select oscillator mode from code
option table before compiling. Following is the code option table.
Code Option
00
01
10
11
Oscillator Mode
RC mode
32K
12M
4M
Remark
Output the Fcpu square wave from Xout pin.
32768Hz
12MHz ~ 16MHz
3.58MHz
OSCILLATOR DEVIDE BY 2 CODE OPTION
SN8P1600 has a code option to divide external clock by 2,called “High_Clk / 2”. If “High_Clk / 2” is enabled, the
external clock frequency is divided by 8 for the Fcpu. Fcpu is equal to Fosc/8. If “High_Clk / 2” is disabled, the external
clock frequency is divided by 4 for the Fcpu. The Fcpu is equal to Fosc/4.
Note: In RC mode, “High_Clk / 2” is always enabled.
OSCILLATOR SAFE GUARD CODE OPTION
SN8P1600 builds in an oscillator safe guard (OSG) to make oscillator more stable. It is a low-pass filter circuit and
stops high frequency noise into system from external oscillator circuit. This function makes system to work better under
AC noisy conditions.
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SN8P1600
8-bit micro-controller
SYSTEM OSCILLATOR CIRCUITS
VDD
20PF
XIN
CRYSTAL
20PF
MCU
XOUT
VSS
Crystal/Ceramic Oscillator
VDD
R
XIN
XOUT
C
MCU
VSS
RC Oscillator
VDD
External Clock Input
XIN
XOUT
MCU
VSS
External clock input
Note1: The VDD and VSS of external oscillator circuit must be from micro-controller. Don’t connect them
from power terminal.
Note2: The external clock input mode can select RC type oscillator or crystal type oscillator of the code
option and input the external clock into XIN pin.
Note3: In RC type oscillator code option situation, the external clock frequency is divided by 2.
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8-bit micro-controller
External RC Oscillator Frequency Measurement
There are two ways to get the Fosc frequency of external RC oscillator. One measures the XOUT output waveform.
Under external RC oscillator mode, the XOUT outputs the square waveform whose frequency is Fcpu. The other
measures the external RC frequency by instruction cycle (Fcpu). The external RC frequency is the Fcpu multiplied by 4.
We can get the Fosc frequency of external RC from the Fcpu frequency. The sub-routine to get Fcpu frequency of
external oscillator is as the following.
Example: Fcpu instruction cycle of external oscillator
B0BSET
P1M.0
; Set P1.0 to be output mode for outputting Fcpu toggle
signal.
B0BSET
B0BCLR
JMP
P1.0
P1.0
@B
; Output Fcpu toggle signal in low-speed clock mode.
; Measure the Fcpu frequency by oscilloscope.
@@:
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SN8P1600
8-bit micro-controller
INTERNAL LOW-SPEED OSCILLATOR
The internal low-speed oscillator is built in the micro-controller. The low-speed clock source is a RC type oscillator
circuit. The low-speed clock can supplies clock for system clock and timer,.
Example: Stop internal low-speed oscillator.
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0 bit of OSCM
register.
The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of
the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The
relative between the RC frequency and voltage is as the following figure.
Internal RC vs. VDD
40
38.678
35.343
Fintrc (KHz)
35
32.008
30
28.673
25.338
25
22.003
20
18.668
15.333
15
11.998
10
8.663
7.329
5
0
1.80
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
6.50
VDD (Volts)
Example: Measure the internal RC frequency by instruction cycle (Fcpu). The internal RC frequency is the
Fcpu multiplied by 4. We can get the Fosc frequency of internal RC from the Fcpu frequency.
B0BSET
P1M.0
; Set P1.0 to be output mode for outputting Fcpu toggle signal.
B0BSET
FCLKMD
; Switch the system clock to internal low-speed clock mode.
B0BSET
B0BCLR
JMP
P1.0
P1.0
@B
; Output Fcpu toggle signal in low-speed clock mode.
; Measure the Fcpu frequency by oscilloscope.
@@:
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SN8P1600
8-bit micro-controller
SYSTEM MODE DESCRIPTION
OVERVIEW
The chip is featured with low power consumption by switching around three different modes as following.
High-speed mode
Low-speed mode
Power-down mode (Sleep mode)
In actual application, user can adjust the MCU to work in one of these three modes by using OSCM register. At the
high-speed mode, the instruction cycle (Fcpu) is Fosc/4. At 3V, low-speed mode, the Fcpu is 16KHz/4.
NORMAL MODE
In normal mode, the system clock source is external high-speed clock. After power on, the system works under normal
mode. The instruction cycle is fosc/4. When the external high-speed oscillator is 3.58MHz, the instruction cycle is
3.58MHz/4 = 895KHz. All software and hardware are executed and working. In normal mode, system can get into
power down mode and slow mode.
SLOW MODE
In slow mode, the system clock source is internal low-speed RC clock. To set CLKMD = 1, the system switch to slow
mode. In slow mode, the system works as normal mode but the slower clock. The system in slow mode can get into
normal mode and power down mode. To set STPHX = 1 to stop the external high-speed oscillator, and then the
system consumes less power.
POWER DOWN MODE
The power down mode is also called sleep mode. The MCU stops working as sleeping status. The power consumption
is very less as zero. The power down mode is usually applied to power-saving system like battery-powered
productions. To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed
oscillators are turned off. The system can be waked up by P0, P1 trigger signal.
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SN8P1600
8-bit micro-controller
SYSTEM MODE CONTROL
Power Down Mode
(Sleep Mode)
P0, P1 wake-up function active.
External reset circuit active.
CPUM0 = 01
CLKMD = 1
Normal Mode
CLKMD = 0
Slow Mode
SN8P1600 OTP Type.
Operating mode description
MODE
NORMAL
SLOW
HX osc.
LX osc.
CPU instruction
Running
Running
Executing
By STPHX
Running
Executing
POWER DOWN
(SLEEP)
Stop
Stop
Stop
TC0 timer
*Active
*Active
Inactive
Watchdog timer
Internal interrupt
External interrupt
Wakeup source
Active
All active
All active
-
Active
All active
All active
-
Inactive
All inactive
All inactive
P0, P1, Reset
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REMARK
* Active by
program
Revision 1.94
SN8P1600
8-bit micro-controller
SYSTEM MODE SWITCHING
Switch normal/slow mode to power down (sleep) mode.
CPUM0 = 1
B0BSET
FCPUM0
; set the system into power down mode.
During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
Switch normal mode to slow mode.
B0BSET
B0BSET
FCLKMD
FSTPHX
;To set CLKMD = 1, Change the system into slow mode
;To stop external high-speed oscillator for power saving.
Switch slow mode to normal mode
If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for
external clock stable.
@@:
B0BCLR
FSTPHX
; Turn on the external high-speed oscillator.
B0MOV
DECMS
JMP
Z, #27
Z
@B
; If VDD = 5V, internal RC=32KHz (typical) will delay
; 0.125ms X 81 = 10.125ms for external clock stable
B0BCLR
FCLKMD
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;
; Change the system back to the normal mode
Page 49
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SN8P1600
8-bit micro-controller
WAKEUP TIME
OVERVIEW
The external high-speed oscillator needs a delay time from stopping to operating. The delay is very necessary and
makes the oscillator work stably. The external high-speed oscillator sometimes starts and stops at different situations.
The delay time for external high-speed oscillator restart is called Wakeup time.
Following are two conditions need Wakeup time. One is switching power down mode to normal mode. The other is
switching slow mode to normal mode. For the first case, SN8P1600 provides 2048 oscillator clocks as the Wakeup
time. The second case, users need to calculate the Wakeup time.
HARDWARE WAKEUP
When the system is in power down mode (sleep mode), the external high-speed oscillator stops. When waked up from
power down mode, MCU waits for 2048 external high-speed oscillator clocks as the Wakeup time to stable the
oscillator circuit. After the Wakeup time, the system goes into the normal mode. The value of the Wakeup time is as the
following.
The Wakeup time = 1/Fosc * 2048 (sec) + X’tal settling time
The x’tal settling time is depended on the x’tal type. Typically, it is about 2~4mS.
Example: In power down mode (sleep mode), the system is waked up by P0 or P1 trigger signal. After the
Wakeup time, the system goes into normal mode. The Wakeup time of P0, P1 Wakeup function is as the
following.
The Wakeup time = 1/Fosc * 2048 = 0.57 ms
(Fosc = 3.58MHz)
The total wakeup time = 0.57ms + x’tal settling time
Under power down mode (sleep mode), there are only I/O ports with Wakeup function wake the system up to normal
mode. The Port 0 and Port 1 have Wakeup function. Port 0 Wakeup function always enables, but the Port 1 is
controlled by the P1W register.
SN8P1602/1603
0C0H
Bit 7
0
P1W
Read/Write
After reset
-
Bit 6
0
-
Bit 5
0
-
Bit 4
P14W
R/W
0
Bit 3
P13W
R/W
0
Bit 2
P12W
R/W
0
Bit 1
P11W
R/W
0
Bit 0
P10W
R/W
0
SN8P1604
0C0H
Bit 7
P17W
P1W
Read/Write
R/W
After reset
0
Bit 6
P16W
R/W
0
Bit 5
P15W
R/W
0
Bit 4
P14W
R/W
0
Bit 3
P13W
R/W
0
Bit 2
P12W
R/W
0
Bit 1
P11W
R/W
0
Bit 0
P10W
R/W
0
P10W~P14W: Port 1 Wakeup function control bits. 0 = none Wakeup function, 1 = Enable Wakeup function.
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8-bit micro-controller
8 TIMERS
WATCHDOG TIMER (WDT)
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. The instruction that clear the
watchdog timer (“B0BSET FWDRST“) should be executed within a certain period. If an instruction that clears the
watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and
system is restarted. The watchdog timer rate has two rates for high/low speed mode. WDT rate selection is handled by
oscillator code option. The watchdog timer disables at power down mode.
0CAH
OSCM
Read/Write
After reset
Bit 7
0
-
Bit 6
WDRST
R/W
0
Bit 5
0
-
Bit 4
0
-
Bit 3
CPUM0
R/W
0
Bit 2
CLKMD
R/W
0
Bit 1
STPHX
R/W
0
Bit 0
0
-
WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer counter.
Note: The bit 0, 4, 5, 7 must be “0”, or the system will be error.
Watchdog timer overflow table.
Code option of High_Clk
Watchdog timer overflow time
4M_X’tal / 12M_X’tal / RC
32K_X’tal
1 / ( fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz
1 / ( fcpu ÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz
Note: The watchdog timer can be enabled or disabled by the code option.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
B0BSET
.
CALL
CALL
.
.
.
JMP
FWDRST
.
SUB1
SUB2
.
.
.
MAIN
SONiX TECHNOLOGY CO., LTD
; Clear the watchdog timer counter.
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SN8P1600
8-bit micro-controller
TIMER0 (TC0) (SN8P1602/1603 Only)
OVERVIEW
The timer counter 0 (TC0) is used to generate an interrupt request when a specified time interval has elapsed. If the
TC0 timer has occur an overflow (from FFH to 00H), it will continue counting and issue a time-out signal to trigger TC0
interrupt to request interrupt service.
÷ 2(8-TC0rate)
TC0enb
Internal data bus
pre_load
TC0C
8-bit binary counter
FCpu
TC0 Time out
CPUM1,0
The main purposes of the TC0 timer is as following.
8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock
frequency.
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8-bit micro-controller
TC0M MODE REGISTER
The TC0M is an 8-bit read/write timer mode register. By loading different value into the TC0M register, users can
modify the timer frequency dynamically as program executing.
Eight rates for TC0 timer can be selected by TC0RATE0 ~ TC0RATE2 bits. The range is from fcpu/2 to fcpu/256. The
TC0M initial value is zero and the rate is fcpu/256. The bit7 of TC0M named TC0ENB is the control bit to start TC0
timer. The combination of these bits is to determine the TC0 timer clock frequency and the intervals.
0DAH
TC0M
Read/Write
After reset
Bit 7
TC0ENB
R/W
0
Bit 6
TC0rate2
R/W
0
Bit 5
TC0rate1
R/W
0
Bit 4
TC0rate0
R/W
0
Bit 3
0
0
Bit 2
0
-
Bit 1
0
-
Bit 0
0
-
TC0ENB: TC0 counter enable bit. “0” = disable, “1” = enable.
TC0RATE2~TC0RATE0: TC0 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 =
fcpu/2.
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8-bit micro-controller
TC0C COUNTING REGISTER
TC0C is an 8-bit counter register for the timer (TC0). TC0C must be reset whenever the TC0ENB is set to “1” to start
the timer. TC0C is incremented each time a clock pulse of the frequency determined by TC0RATE0 ~ TC0RATE2.
When TC0C has incremented to “0FFH”, it counts to “00H” an overflow generated. Under TC0 interrupt service request
(TC0IEN) enable condition, the TC0 interrupt request flag will be set to “1” and the system executes the interrupt
service routine. The TC0C has no auto reload function. After TC0C overflow, the TC0C is continuing counting. Users
need to reset TC0C value to get an accurate time.
0DBH
TC0C
Read/Write
After reset
Bit 7
TC0C7
R/W
0
Bit 6
TC0C6
R/W
0
Bit 5
TC0C5
R/W
0
Bit 4
TC0C4
R/W
0
Bit 3
TC0C3
R/W
0
Bit 2
TC0C2
R/W
0
Bit 1
TC0C1
R/W
0
Bit 0
TC0C0
R/W
0
The basic timer table interval time of TC0.
TC0RATE TC0CLOCK
000
001
010
011
100
101
110
111
fcpu/256
fcpu/128
fcpu/64
fcpu/32
fcpu/16
fcpu/8
fcpu/4
fcpu/2
High speed mode (fcpu = 3.58MHz / 4)
Max overflow interval One step = max/256
73.2 ms
286us
36.6 ms
143us
18.3 ms
71.5us
9.15 ms
35.8us
4.57 ms
17.9us
2.28 ms
8.94us
1.14 ms
4.47us
0.57 ms
2.23us
Low speed mode (fcpu = 32768Hz / 4)
Max overflow interval One step = max/256
8000 ms
31.25 ms
4000 ms
15.63 ms
2000 ms
7.8 ms
1000 ms
3.9 ms
500 ms
1.95 ms
250 ms
0.98 ms
125 ms
0.49 ms
62.5 ms
0.24 ms
The equation of TC0C initial value is as following.
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
Example: To set 10ms interval time for TC0 interrupt at 3.58MHz high-speed mode. TC0C value (74H) =
256 - (10ms * fcpu/64)
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
= 256 - (10ms * 3.58 * 106 / 4 / 64)
= 256 - (10-2 * 3.58 * 106 / 4 / 64)
= 116
= 74H
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8-bit micro-controller
TC0 TIMER OPERATION SEQUENCE
The TC0 timer’s sequence of operation may be as following.
Set the TC0C initial value to setup the interval time.
Set the TC0ENB to be “1” to enable TC0 timer.
TC0C is incremented by one after each clock pulse corresponding to TC0M selection.
TC0C overflow if TC0C from FFH to 00H.
When TC0C overflow occur, the TC0IRQ flag is set to be “1” by hardware.
Execute the interrupt service routine.
Users reset the TC0C value and resume the TC0 timer operation.
Example: Setup the TC0M and TC0C.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC0IEN
FTC0ENB
A,#20H
TC0M,A
A,#74H
TC0C,A
; To disable TC0 interrupt service
; To disable TC0 timer
;
; To set TC0 clock = fcpu / 64
; To set TC0C initial value = 74H
;(To set TC0 interval = 10 ms)
B0BSET
B0BCLR
B0BSET
FTC0IEN
FTC0IRQ
FTC0ENB
; To enable TC0 interrupt service
; To clear TC0 interrupt request
; To enable TC0 timer
Example: TC0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF, A
; B0xch instruction do not change C,Z flag
B0BTS1
JMP
FTC0IRQ
EXIT_INT
; Check TC0IRQ
; TC0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
.
.
JMP
FTC0IRQ
A,#74H
TC0C,A
.
.
EXIT_INT
; Reset TC0IRQ
; Reload TC0C
.
.
.
.
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG, A
A, ACCBUF
INT_SERVICE:
; TC0 interrupt service routine
; End of TC0 interrupt service routine and exit interrupt
vector
EXIT_INT:
RETI
SONiX TECHNOLOGY CO., LTD
; Restore ACC value.
; Exit interrupt vector
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SN8P1600
8-bit micro-controller
TIMER1 (TC1) (SN8P1604 Only)
OVERVIEW
The timer counter 1 (TC1) is used to generate an interrupt request when a specified time interval has elapsed. TC1
has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC1R) into which you write the
counter reference value, and an 8-bit counter register (TC1C) whose value is automatically incremented by counter
logic.
Aload1
TC1R reload
data buffer
Internal P5.3 I/O circuit
Auto. reload
R
Compare
S
TC1enb
TC1out
Buzzer
P5.3
÷2
PWM
PWM1OUT
load
fcpu
TC1C
8-bit binary counter
÷ 2(8-TC1Rate)
TC1 Time out
CPUM0
The main purposes of the TC1 timer is as following.
8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock
frequency.
Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ1 pin (P5.3).
PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM1 pin (P5.3).
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8-bit micro-controller
TC1M MODE REGISTER
The TC1M is an 8-bit read/write timer mode register. By loading different value into the TC1M register, users can
modify the timer frequency dynamically as program executing.
Eight rates for TC1 timer can be selected by TC0RATE1 ~ TC1RATE2 bits. The range is from fcpu/2 to fcpu/256. The
TC1M initial value is zero and the rate is fcpu/256. The bit7 of TC1M named TC1ENB is the control bit to start TC1
timer. The combination of these bits is to determine the TC1 timer clock frequency and the intervals.
0DCH
TC1M
Read/Write
After reset
Bit 7
TC1ENB
R/W
0
Bit 6
TC1rate2
R/W
0
Bit 5
TC1rate1
R/W
0
Bit 4
TC1rate0
R/W
0
Bit 3
0
0
Bit 2
ALOAD1
R/W
0
Bit 1
TC1OUT
R/W
0
Bit 0
PWM1OUT
R/W
0
TC1ENB: TC1 counter/BZ1/PWM1OUT enable bit. “0” = disable, “1” = enable.
TC1RATE2~TC1RATE0: TC1 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 =
fcpu/2.
ALOAD1: TC1 auto-reload control bit, “0” the auto-reload function is disabled. “1 “ is to enable the auto-reload function.
TC1OUT : TC1 Time-out toggle signal output control bit. “0”: No TC1 time-out output signal. “1”: When TC1 time-out
occurs, P5.3 output toggles.
PWM1OUT : PWM output control bit. “0”: No PWM output function. “1”: PWM will output waveform through pin P5.3.
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8-bit micro-controller
TC1C COUNTING REGISTER
TC1C is an 8-bit counter register for the timer (TC1). TC1C must be reset whenever the TC1ENB is set to “1” to start
the timer. TC1C is incremented each time a clock pulse of the frequency determined by TC1RATE0 ~ TC1RATE2.
When TC1C has incremented to “0FFH”, it counts to “00H” an overflow generated. Under TC1 interrupt service request
(TC1IEN) enable condition, the TC1 interrupt request flag will be set to “1” and the system executes the interrupt
service routine. When TC1C overflows, the TC1C will be restored automatically if ALOAD1 of TC1M register is
enabled.
0DDH
TC1C
Read/Write
After reset
Bit 7
TC1C7
R/W
-
Bit 6
TC1C6
R/W
-
Bit 5
TC1C5
R/W
-
Bit 4
TC1C4
R/W
-
Bit 3
TC1C3
R/W
-
Bit 2
TC1C2
R/W
-
Bit 1
TC1C1
R/W
-
Bit 0
TC1C0
R/W
-
The basic timer table interval time of TC1.
TC1RATE TC1CLOCK
000
001
010
011
100
101
110
111
fcpu/256
fcpu/128
fcpu/64
fcpu/32
fcpu/16
fcpu/8
fcpu/4
fcpu/2
High speed mode (fcpu = 3.58MHz / 4)
Max overflow interval One step = max/256
73.2 ms
286us
36.6 ms
143us
18.3 ms
71.5us
9.15 ms
35.8us
4.57 ms
17.9us
2.28 ms
8.94us
1.14 ms
4.47us
0.57 ms
2.23us
Low speed mode (fcpu = 32768Hz / 4)
Max overflow interval One step = max/256
8000 ms
31.25 ms
4000 ms
15.63 ms
2000 ms
7.8 ms
1000 ms
3.9 ms
500 ms
1.95 ms
250 ms
0.98 ms
125 ms
0.49 ms
62.5 ms
0.24 ms
The equation of TC1C initial value is as following.
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
Example: To set 10ms interval time for TC1 interrupt at 3.58MHz high-speed mode. TC1C value (74H) =
256 - (10ms * fcpu/64)
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
= 256 - (10ms * 3.58 * 106 / 4 / 64)
= 256 - (10-2 * 3.58 * 106 / 4 / 64)
= 116
= 74H
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8-bit micro-controller
TC1R AUTO-LOAD REGISTER
TC1R is an 8-bit register for the TC1 auto-reload function. TC1R’s value applies to TC1OUT and PWM1OUT
functions. . Under TC1OUT application, users must enable and set the TC1R register. The main purpose of TC1R is as
following.
Store the auto-reload value and set into TC1C when the TC1C overflow. (ALOAD1 = 1).
Store the duty value of PWM1OUT function.
0DEH
TC1R
Read/Write
After reset
Bit 7
TC1R7
W
-
Bit 6
TC1R6
W
-
Bit 5
TC1R5
W
-
Bit 4
TC1R4
W
-
Bit 3
TC1R3
W
-
Bit 2
TC1R2
W
-
Bit 1
TC1R1
W
-
Bit 0
TC1R0
W
-
The equation of TC1R initial value is like TC1C as following.
TC1R initial value = 256 - (TC1 interrupt interval time * input clock)
Note: The TC1R is write-only register can’t be process by INCMS, DECMS instructions.
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8-bit micro-controller
TC1 TIMER COUNTER OPERATION SEQUENCE
The TC1 timer’s sequence of operation can be following.
Set the TC1C initial value to setup the interval time.
Set the TC1ENB to be “1” to enable TC1 timer counter.
TC1C is incremented by one with each clock pulse which frequency is corresponding to TC1M selection.
TC1C overflow if TC1C from FFH to 00H.
When TC1C overflow occur, the TC1IRQ flag is set to be “1” by hardware.
Execute the interrupt service routine.
Users reset the TC1C value and resume the TC1 timer operation.
Example: Setup the TC1M and TC1C without auto-reload function.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC1IEN
FTC1ENB
A,#20H
TC1M,A
A,#74H
TC1C,A
; To disable TC1 interrupt service
; To disable TC1 timer
;
; To set TC1 clock = fcpu / 64
; To set TC1C initial value = 74H
;(To set TC1 interval = 10 ms)
B0BSET
B0BCLR
B0BSET
FTC1IEN
FTC1IRQ
FTC1ENB
; To enable TC1 interrupt service
; To clear TC1 interrupt request
; To enable TC1 timer
Example: Setup the TC1M and TC1C with auto-reload function.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
B0MOV
FTC1IEN
FTC1ENB
A,#20H
TC1M,A
A,#74H
TC1C,A
TC1R,A
; To disable TC1 interrupt service
; To disable TC1 timer
;
; To set TC1 clock = fcpu / 64
; To set TC1C initial value = 74H
; (To set TC1 interval = 10 ms)
; To set TC1R auto-reload register
B0BSET
B0BCLR
B0BSET
B0BSET
FTC1IEN
FTC1IRQ
FTC1ENB
ALOAD1
; To enable TC1 interrupt service
; To clear TC1 interrupt request
; To enable TC1 timer
; To enable TC1 auto-reload function.
SONiX TECHNOLOGY CO., LTD
Page 60
Revision 1.94
SN8P1600
8-bit micro-controller
Example: TC1 interrupt service routine without auto-reload function.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF, A
; B0XCH doesn’t change C, Z flag
B0BTS1
JMP
FTC1IRQ
EXIT_INT
; Check TC1IRQ
; TC1IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
.
.
JMP
FTC1IRQ
A,#74H
TC1C,A
.
.
EXIT_INT
; Reset TC1IRQ
; Reload TC1C
.
.
.
.
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG, A
A, ACCBUF
INT_SERVICE:
; Save PFLAG register in a buffer
; TC1 interrupt service routine
; End of TC1 interrupt service routine and exit interrupt
vector
EXIT_INT:
RETI
; Restore PFLAG register from buffer
; B0XCH doesn’t change C, Z flag
; Exit interrupt vector
Example: TC1 interrupt service routine with auto-reload.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF, A
; B0XCH doesn’t change C, Z flag
B0BTS1
JMP
FTC1IRQ
EXIT_INT
; Check TC1IRQ
; TC1IRQ = 0, exit interrupt vector
B0BCLR
.
.
JMP
FTC1IRQ
.
.
EXIT_INT
; Reset TC1IRQ
; TC1 interrupt service routine
.
.
.
.
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG, A
A, ACCBUF
INT_SERVICE:
; Save PFLAG register in a buffer
; End of TC1 interrupt service routine and exit interrupt
vector
EXIT_INT:
RETI
SONiX TECHNOLOGY CO., LTD
; Restore PFLAG register from buffer
; B0XCH doesn’t change C, Z flag
; Exit interrupt vector
Page 61
Revision 1.94
SN8P1600
8-bit micro-controller
TC1 CLOCK FREQUENCY OUTPUT (BUZZER)
TC1 timer counter provides a frequency output function. By setting the TC1 clock frequency, the clock signal is output
to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1 output signal divides by 2. The TC1 clock
has many combinations and easily to make difference frequency. This function applies as buzzer output to output
multi-frequency.
Figure 8-1. The TC1OUT Pulse Frequency
Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The
TC1OUT frequency is 1KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 2KHz. The
TC1 clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110.
TC1C = TC1R = 131.
MOV
B0MOV
A,#01100000B
TC1M,A
MOV
B0MOV
B0MOV
A,#131
TC1C,A
TC1R,A
; Set the auto-reload reference value
B0BSET
B0BSET
B0BSET
FTC1OUT
FALOAD1
FTC1ENB
; Enable TC1 output to P5.3 and disable P5.3 I/O function
; Enable TC1 auto-reload function
; Enable TC1 timer
SONiX TECHNOLOGY CO., LTD
; Set the TC1 rate to Fcpu/4
Page 62
Revision 1.94
SN8P1600
8-bit micro-controller
PWM FUNCTION DESCRIPTION (SN8P1604 Only)
OVERVIEW
PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin (P5.3). The 8-bit
counter counts modulus 256, from 0-255, inclusive. The value of the 8-bit counter is compared to the contents of the
reference register TC1R. When the reference register value TC1R is equal to the counter value TC1C, the PWM
output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio (duty) of the
PWM1 output is TC1R/256.
All PWM outputs remain inactive during the first 256 input clock signals. Then, when the counter value (TC1C)
changes from FFH back to 00H, the PWM output is forced to high level. The pulse width ratio (duty cycle) is defined by
the contents of the reference register (TC1R) and is programmed in increments of 1:256. The 8-bit PWM data register
TC1R is a write only register.
PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to
change the PWM’s duty cycle is to modify the TC1R.
Reference Register Value (TC1R)
0000 0000
0000 0001
0000 0010
.
.
1000 0000
1000 0001
.
.
1111 1110
1111 1111
0
1
..... 128
Duty
0/256
1/256
2/256
.
.
128/256
129/256
.
.
254/256
255/256
..... 254 255
0
1
..... 128
..... 254 255
TC1 Clock
TC1R = 00H
Low
High
TC1R = 01H
Low
High
TC1R = 80H
Low
High
TC1R = FFH
Low
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Revision 1.94
SN8P1600
8-bit micro-controller
PWM PROGRAM DESCRIPTION
Example: Setup PWM1 output from TC1 to PWM1OUT (P5.3). The external high-speed oscillator clock is
4MHz. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is from
external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 30.
MOV
B0MOV
MOV
B0MOV
A,#01100000B
TC1M,A
A,#0x00
TC1C,A
MOV
B0MOV
A,#30
TC1R,A
; Set the PWM duty to 30/256
B0BCLR
B0BSET
B0BSET
FTC1OUT
FPWM1OUT
FTC1ENB
; Disable TC1OUT function.
; Enable PWM1 output to P5.3 and disable P5.3 I/O function
; Enable TC1 timer
; Set the TC1 rate to Fcpu/4
;First Time Initial TC0
Note1: The TC1R is write-only register. Don’t process them using INCMS, DECMS instructions.
Note2: Set TC1C at initial is to make first duty-cycle correct. After TC1 is enabled, don’t modify TC1R
value to avoid duty cycle error of PWM output.
Example: Modify TC1R registers’ value.
MOV
B0MOV
A, #30H
TC1R, A
; Input a number using B0MOV instruction.
INCMS
B0MOV
B0MOV
BUF1
A, BUF1
TC1R, A
; Get the new TC1R value from the BUF1 buffer defined by
; programming.
Note3: That is better to set the TC1C and TC1R value together when PWM1 duty modified. It protects the
PWM1 signal no glitch as PWM1 duty changing.
Note4: The TC1OUT function must be set “0” when PWM1 output enable.
Note5: The PWM can work with interrupt request.
SONiX TECHNOLOGY CO., LTD
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Revision 1.94
SN8P1600
8-bit micro-controller
9 INTERRUPT
OVERVIEW
The SN8P1600 provides 2 interrupt sources, including one internal interrupts (TC0/TC1) and one external interrupts
(INT0). The external interrupt can Wakeup the chip while the system is switched from power down mode to high-speed
normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other
interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’
request. All of the interrupt request signals are stored in INTRQ register. The user can program the chip to check
INTRQ’s content for setting executive priority.
SN8P1602/1603
The interrupt trigger edge :
INT0 = falling edge
TC0 time out
INT0 trigger
INTEN Interrupt enable register
TC0IRQ
INTRQ
2-bit
Latchs
P00IRQ
Interrupt
enable
gating
Interrupt vector address (0008H)
Global interrupt request signal
SN8P1604
The interrupt trigger edge :
INT0 = falling edge
INTEN Interrupt enable register
TC1IRQ
TC1 time out
INT0 trigger
INTRQ
2-bit
Latches
P00IRQ
Interrupt
enable
gating
Interrupt vector address (0008H)
Global interrupt request signal
Note: The GIE bit must enable and all interrupt operations work.
SONiX TECHNOLOGY CO., LTD
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Revision 1.94
SN8P1600
8-bit micro-controller
INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
SN8P1602/1603
0C9H
Bit 7
0
INTEN
Read/Write
After reset
-
Bit 6
0
-
Bit 5
TC0IEN
R/W
0
Bit 4
0
-
Bit 3
0
-
Bit 2
0
-
Bit 1
0
-
Bit 0
P00IEN
R/W
0
SN8P1604
0C9H
Bit 7
0
INTEN
Read/Write
After reset
-
Bit 6
TC1IEN
R/W
0
Bit 5
0
-
Bit 4
0
-
Bit 3
0
-
Bit 2
0
-
Bit 1
0
-
Bit 0
P00IEN
R/W
0
P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable.
TC0IEN : Timer 0 interrupt control bit. 0 = disable, 1 = enable.
INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
SN8P1602/1603
0C8H
Bit 7
0
INTRQ
Read/Write
After reset
-
Bit 6
0
-
Bit 5
TC0IRQ
R/W
0
Bit 4
0
-
Bit 3
0
-
Bit 2
0
-
Bit 1
0
-
Bit 0
P00IRQ
R/W
0
SN8P1604
0C8H
Bit 7
0
INTRQ
Read/Write
After reset
-
Bit 6
TC1IRQ
R/W
0
Bit 5
0
-
Bit 4
0
-
Bit 3
0
-
Bit 2
0
-
Bit 1
0
-
Bit 0
P00IRQ
R/W
0
P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request.
TC0IRQ : TC0 timer interrupt request controls bit. 0 = non request, 1 = request.
When interrupt occurs, the related request bit of INTRQ register will be set to “1” no matter the related enable bit of
INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be “1”.
As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the
system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious
with the operation under multi-interrupt situation.
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
INTERRUPT OPERATION DESCRIPTION
SN8P1600 provides 2 interrupts. Each operation of the 2 interrupts is as following.
GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
0DFH
STKP
Read/Write
After reset
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
GIE: Global interrupt control bit. 0 = disable, 1 = enable.
Example: Set global interrupt control bit (GIE).
B0BSET
FGIE
Note: Set GIE bit as “1’ to enable
SONiX TECHNOLOGY CO., LTD
; Enable GIE
all interrupt.
Page 67
Revision 1.94
SN8P1600
8-bit micro-controller
INT0 (P0.0) INTERRUPT OPERATION
The INT0 has falling edge interrupt trigger. For SN8P1600, the INT0 just uses the falling edge to trigger the external
interrupt 0. When the INT0 trigger occurs, the P00IRQ will be set to “1” however the P00IEN is enable or disable. If the
P00IEN = 1, the trigger event sets the P00IRQ to be “1” and the system into interrupt vector (ORG 8). If the P00IEN =
0, the trigger event just only sets the P00IRQ to be “1” but the system doesn’t get into interrupt vector. Users need to
care the operation under multi-interrupt situation.
Example: INT0 interrupt request setup.
B0BSET
B0BCLR
B0BSET
FP00IEN
FP00IRQ
FGIE
; Enable INT0 interrupt service
; Clear INT0 interrupt request flag
; Enable GIE
Example: INT0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF, A
; Store ACC value.
B0BTS1
JMP
FP00IRQ
EXIT_INT
; Check P00IRQ
; P00IRQ = 0, exit interrupt vector
B0BCLR
.
.
FP00IRQ
.
.
; Reset P00IRQ
; INT0 interrupt service routine
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG, A
A, ACCBUF
INT_SERVICE:
EXIT_INT:
RETI
SONiX TECHNOLOGY CO., LTD
; Restore ACC value.
; Exit interrupt vector
Page 68
Revision 1.94
SN8P1600
8-bit micro-controller
TC0/TC1 INTERRUPT OPERATION
When the TC0C/TC1C counter occurs overflow, the TC0IRQ/TC1IRQ will be set to “1” however the TC0IEN/TC1IEN is
enable or disable. If the TC0IEN = 1, the trigger event sets the TC0IRQ/TC1IRQ to be “1” and the system into interrupt
0vector. If the TC0IEN/TC1IEN = 0, the trigger event will make the TC0IRQ/TC1IEN to be “1” but the system not into
interrupt vector. Users need to care the operation under multi-interrupt situation.
Example: TC0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC0IEN
FTC0ENB
A, #20H
TC0M, A
A, #74H
TC0C, A
; Disable TC0 interrupt service
; Disable TC0 timer
;
; Set TC0 clock = Fcpu / 64
; Set TC0C initial value = 74H
; Set TC0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC0IEN
FTC0IRQ
FTC0ENB
; Enable TC0 interrupt service
; Clear TC0 interrupt request flag
; Enable TC0 timer
B0BSET
FGIE
; Enable GIE
Example: TC0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF, A
; Store ACC value.
B0BTS1
JMP
FTC0IRQ
EXIT_INT
; Check TC0IRQ
; TC0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
.
.
FTC0IRQ
A, #74H
TC0C, A
.
.
; Reset TC0IRQ
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG, A
A, ACCBUF
INT_SERVICE:
; Reset TC0C.
; TC0 interrupt service routine
EXIT_INT:
RETI
SONiX TECHNOLOGY CO., LTD
; Restore ACC value.
; Exit interrupt vector
Page 69
Revision 1.94
SN8P1600
8-bit micro-controller
MULTI-INTERRUPT OPERATION
In almost conditions, the software designer uses more than one interrupt requests. Processing multi-interrupt request
needs to set the priority of these interrupt requests. The IRQ flags of interrupts are controlled by the interrupt event. But
the IRQ flag “1” doesn’t mean the system to execute the interrupt vector. The IRQ flags can be set “1” by the events
without interrupt enable. Just only any the event occurs and the IRQ will be logic “1”. The IRQ and its trigger event
relationship is as the below table.
Interrupt Name
P00IRQ
TC0IRQ
TC1IRQ
Trigger Event Description
P0.0 trigger. OTP is falling edge.
TC0C overflow. (SN8P1602/1603)
TC1C overflow. (SN8P1604)
There are two works need to do for multi-interrupt conditions. One is to make a good priority for these interrupt
requests. Two is using IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check
interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following.
Example: How do users check the interrupt request in multi-interrupt situation?
ORG
8
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF,A
; Store ACC value.
; Store PFLAG value
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTTC0CHK
FP00IRQ
INTP00
B0BTS1
JMP
B0BTS0
JMP
FTC0IEN
INT_EXIT
FTC0IRQ
INTTC0
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG,A
A, ACCBUF
INTP00CHK:
INTTC0CHK:
; Check INT0 interrupt request
; Check P00IEN
; Jump check to next interrupt
; Check P00IRQ
; Jump to INT0 interrupt service routine
; Check TC0 interrupt request
; Check TC0IEN
; Jump to exit of IRQ
; Check TC0IRQ
; Jump to TC0 interrupt service routine
INT_EXIT:
RETI
SONiX TECHNOLOGY CO., LTD
; Restore PFLAG value
; Restore ACC value.
; Exit interrupt vector
Page 70
Revision 1.94
SN8P1600
8-bit micro-controller
10 I/O PORT
OVERVIEW
The SN8P1602/1603 provides up to 3 ports for users’ application, consisting of one input only port (P0), two I/O ports
(P1, P2,). The SN8P1602/1603 is without input pull-up resistors. The direction of I/O port is selected by PnM register.
After the system resets, these ports work as input function.
The SN8P1604 provides 4 ports for users’ application, consisting of one input port (P0) and three I/O ports (P1,P2,P5).
The direction of I/O port is selected by PnM register. After the system resets, these ports work as input port without pull
up resistors. If the user want to read-in a signal from I/O pin, it recommends to switch I/O pin as input mode to execute
read-in instruction. (B0BTS0 M.b, B0BTS1 M.b or B0MOV A,M). The pull-up resistor can be set up by the code option
in the programming phase.
SN8P1602/1603
Port1, 2 structure
PnM
Port0 structure
Pin
Latch
Int. bus
Pin
Int. bus
PnM
PnM
Note: All of the latch output circuits are push-pull structures.
SN8P1604
Port0 structure
Port1,2, 5 structure
PUR
PUR
PnM, Code Option
Code Option
Pin
PnM
Pin
Int. bus
Latch
Int. bus
PnM
PnM
Note: The pull-up resistor can be set up by the code option in the programming phase.
SONiX TECHNOLOGY CO., LTD
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Revision 1.94
SN8P1600
8-bit micro-controller
I/O PORT FUNCTION TABLE
SN8P1602/1603
Port/Pin
I/O
P0.0
I
P1.0~P1.4
I/O
P2.0~P2.7
I/O
Function Description
General-purpose input function
External interrupt (INT0)
Wakeup for power down mode
General-purpose input/output function
Wakeup for power down mode
General-purpose input/output function
Remark
Falling edge
Low level
Low level
Note: The P1.4 enables when the external oscillator is RC type.
SN8P1604
Port/Pin
I/O
P0.0
I
P0.1
I
P1.0~P1.7
I/O
P2.0~P2.7
P5.0~P5.3
I/O
I/O
SONiX TECHNOLOGY CO., LTD
Function Description
General-purpose input function
External interrupt (INT0)
Wakeup for power down mode
Wakeup for power down mode
General-purpose input/output function
Wakeup for power down mode
General-purpose input/output function
General-purpose input/output function
Page 72
Remark
Falling edge
Low level
Low level
Low level
Revision 1.94
SN8P1600
8-bit micro-controller
I/O PORT MODE
The port direction is programmed by PnM register. Port 0 is always input mode. Port 1 and Port 2 can select input or
output direction. The each bit of PnM is set to “0”, the I/O pin is input mode. The each bit of PnM is set to “1”, the I/O
pin is output mode.
SN8P1602/1603
0C1H
Bit 7
0
P1M
Read/Write
After reset
-
Bit 6
0
-
Bit 5
0
-
Bit 4
P14M
R/W
0
Bit 3
P13M
R/W
0
Bit 2
P12M
R/W
0
Bit 1
P11M
R/W
0
Bit 0
P10M
R/W
0
SN8P1604
0C1H
Bit 7
P17M
P1M
Read/Write
R/W
After reset
0
Bit 6
P16M
R/W
0
Bit 5
P15M
R/W
0
Bit 4
P14M
R/W
0
Bit 3
P13M
R/W
0
Bit 2
P12M
R/W
0
Bit 1
P11M
R/W
0
Bit 0
P10M
R/W
0
SN8P1602/1603/1604
0C2H
Bit 7
P27M
P2M
Read/Write
R/W
After reset
0
Bit 6
P26M
R/W
0
Bit 5
P25M
R/W
0
Bit 4
P24M
R/W
0
Bit 3
P23M
R/W
0
Bit 2
P22M
R/W
0
Bit 1
P21M
R/W
0
Bit 0
P20M
R/W
0
Bit 6
0
-
Bit 5
0
-
Bit 4
0
-
Bit 3
P53M
R/W
0
Bit 2
P52M
R/W
0
Bit 1
P51M
R/W
0
Bit 0
P50M
R/W
0
SN8P1604
0C5H
Bit 7
0
P5M
Read/Write
After reset
-
The PnM registers are read/write bi-direction registers. Users can program them by bit control
instructions (B0BSET, B0BCLR).
Example: I/O mode selecting.
CLR
CLR
P1M
P2M
; Set all ports to be input mode.
MOV
B0MOV
B0MOV
A, #0FFH
P1M, A
P2M, A
; Set all ports to be output mode.
B0BCLR
P1M.2
; Set P1.2 to be input mode.
B0BSET
P1M.2
; Set P1.2 to be output mode.
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Revision 1.94
SN8P1600
8-bit micro-controller
I/O PORT DATA REGISTER
SN8P1602/1603
0D0H
Bit 7
P0
Read/Write
After reset
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
P00
R
0
SN8P1604
0D0H
Bit 7
P0
Read/Write
After reset
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
P01
R
0
Bit 0
P00
R
0
SN8P1602/1603
0D1H
Bit 7
P1
Read/Write
After reset
-
Bit 6
-
Bit 5
-
Bit 4
P14
R/W
0
Bit 3
P13
R/W
0
Bit 2
P12
R/W
0
Bit 1
P11
R/W
0
Bit 0
P10
R/W
0
SN8P1604
0D1H
Bit 7
P17
P1
Read/Write
R/W
After reset
0
Bit 6
P16
R/W
0
Bit 5
P15
R/W
0
Bit 4
P14
R/W
0
Bit 3
P13
R/W
0
Bit 2
P12
R/W
0
Bit 1
P11
R/W
0
Bit 0
P10
R/W
0
SN8P1602/1603/1604
0D2H
Bit 7
P27
P2
Read/Write
R/W
After reset
0
Bit 6
P26
R/W
0
Bit 5
P25
R/W
0
Bit 4
P24
R/W
0
Bit 3
P23
R/W
0
Bit 2
P22
R/W
0
Bit 1
P21
R/W
0
Bit 0
P20
R/W
0
SN8P1604
0D5H
Bit 7
P5
Read/Write
After reset
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P53
R/W
0
Bit 2
P52
R/W
0
Bit 1
P51
R/W
0
Bit 0
P50
R/W
0
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
Example: Read data from input port.
B0MOV
B0MOV
B0MOV
A, P0
A, P1
A, P2
; Read data from Port 0
; Read data from Port 1
; Read data from Port 2
Example: Write data to output port.
MOV
B0MOV
B0MOV
A, #55H
P1, A
P2, A
; Write data 55H to Port 1 and Port 2
Example: Write one bit data to output port.
B0BSET
B0BSET
P1.3
P2.5
; Set P1.3 and P2.5 to be “1”.
B0BCLR
B0BCLR
P1.3
P2.5
; Set P1.3 and P2.5 to be “0”.
P0.0
; Bit test 1 for P0.0
P1.2
; Bit test 0 for P1.2
Example: Port bit test.
B0BTS1
.
B0BTS0
.
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
11 External Reset Circuit
SN8P1602 External Reset Circuit Example
External Reset Circuit
Pull-up Resistor
VCC
VCC
R5
R1
R3
U1
R4
100K ohm
40K ohm
33K ohm
1
2
3
4
5
6
7
8
9
1K ohm
Q2
NPN
R2
10K ohm
Q1
NPN
P1.2
P1.3
P0.0
RST
VSS
P2.0
P2.1
P2.2
P2.3
P1.1
P1.0
XIN
XOUT
VDD
P2.7
P2.6
P2.5
P2.4
18
17
16
15
14
13
12
11
10
External Oscillator
Y1
VCC
? Hz
C2
C3
20P
20P
SN8P1602
C1
0.1uF (104)
Bypass Cap
VCC
P2.0
D1
R10
100
P2.1
D2
R11
100
R6
100K
P1.0
P2.2
D3
R12
100
R7
100K
P1.1
P2.3
D4
R13
100
R8
100K
P1.2
P2.4
D5
R14
100
R9
100K
P1.3
P2.5
D6
R15
100
P2.6
D7
R16
100
P2.7
D8
R17
100
S1
S2
S3
S4
Output Application
Input Application
Notice :
The SN8P1602 do not have the internal power on reset circuit. It is very important to connect the external
component to implement the reset function. The simple RC circuit does not get a good brownout reset.
The External reset circuit in the demo schematic can improve the SN8P1602 power-on/Brown-out reset
performance, but it increases the system power consumption (about 200µA).
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
SN8P1603 External Reset Circuit Example
Pull-up Resistor
VCC
VCC
R2
U1
R1
100K
1
2
3
4
5
6
7
8
9
20K
External Reset Circuit
P1.2
P1.3
P0.0
RST
VSS
P2.0
P2.1
P2.2
P2.3
External Oscillator
18
17
16
15
14
13
12
11
10
P1.1
P1.0
XIN
XOUT
VDD
P2.7
P2.6
P2.5
P2.4
Y1
VCC
? Hz
C2
C3
20P
20P
SN8P1603
C1
0.1uF (104)
Bypass Cap
VCC
P2.0
D1
R7
100
P2.1
D2
R8
100
R3
100K
P1.0
P2.2
D3
R9
100
R4
100K
P1.1
P2.3
D4
R10
100
R5
100K
P1.2
P2.4
D5
R11
100
R6
100K
P1.3
P2.5
D6
R12
100
P2.6
D7
R13
100
P2.7
D8
R14
100
S1
S2
S3
S4
Output Application
Input Application
Notice :
The SN8P1603 have built-in POR(LVD) function. It has a excellent power-on/brown-out reset performance.
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
SN8P1604
Code Option
High_Clk
High_Clk / 2
OSG
Watch_Dog
LVD
Security
Pull_Up
Content
RC
32K X’tal
12M X’tal
4M X’tal
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Function Description
Low cost RC for external high clock oscillator
Low frequency, power saving crystal (e.g. 32.768K) for external high
clock oscillator
High speed crystal /resonator (e.g. 12M) for external high clock oscillator
Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator
External high clock divided by two, Fosc = high clock / 2
Fosc = high clock
Enable Oscillator Safe Guard function
Disable Oscillator Safe Guard function
Enable Watch Dog function
Disable Watch Dog function
Enable the low voltage detect function
Disable the low voltage detect function
Enable ROM code Security function
Disable ROM code Security function
Enable on-chip pull-up resisters
Disable on-chip pull-up resisters
Notice:
The LVD function can improve the power on reset and brown-out reset performance. It will
increase about extra 100µA current consumption at 5V if LVD is enabled. The minimum working
voltage will be affect by the OSG option. It is very important to check this code option.
Turn on the OSG will improve the EMI performance. But the side effect is to increase the lowest
valid working voltage level.
If users select “32K X’tal” in “High_Clk” option, assembler will force “OSG” to be enabled.
If users select “RC” in “High_Clk” option, assembler will force “High_Clk / 2” to be enabled.
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
12 CODING ISSUE
TEMPLATE CODE
;*******************************************************************************
; FILENAME : TEMPLATE.ASM
; AUTHOR
: SONiX
; PURPOSE
: Template Code for SN8X16XX
; REVISION : 09/01/2002 V1.0
First issue
;*******************************************************************************
;* (c) Copyright 2002, SONiX TECHNOLOGY CO., LTD.
;*******************************************************************************
CHIP
SN8P1602
; Select the CHIP
;------------------------------------------------------------------------------;
Include Files
;------------------------------------------------------------------------------.nolist
; do not list the macro file
INCLUDESTD
INCLUDESTD
INCLUDESTD
MACRO1.H
MACRO2.H
MACRO3.H
.list
; Enable the listing function
;------------------------------------------------------------------------------;
Constants Definition
;------------------------------------------------------------------------------;
ONE
EQU
1
;------------------------------------------------------------------------------;
Variables Definition
;------------------------------------------------------------------------------.DATA
org
0h
;Data section start from RAM address 0
Wk00
DS
1
;Temporary buffer for main loop
Iwk00
DS
1
;Temporary buffer for ISR
AccBuf
DS
1
;Accumulater buffer
PflagBuf
DS
1
;PFLAG buffer
;------------------------------------------------------------------------------;
Bit Variables Definition
;------------------------------------------------------------------------------Wk00B0
Iwk00B1
EQU
EQU
Wk00.0
Iwk00.1
SONiX TECHNOLOGY CO., LTD
;Bit 0 of Wk00
;Bit 1 of Iwk00
Page 79
Revision 1.94
SN8P1600
8-bit micro-controller
;------------------------------------------------------------------------------;
Code section
;------------------------------------------------------------------------------.CODE
ORG
jmp
0
Reset
ORG
jmp
8
Isr
;Code section start
;Reset vector
;Address 4 to 7 are reserved
;Interrupt vector
ORG
10h
;------------------------------------------------------------------------------; Program reset section
;------------------------------------------------------------------------------Reset:
mov
A,#07Fh
;Initial stack pointer and
b0mov
STKP,A
;disable global interrupt
b0mov
PFLAG,#00h
;pflag = x,x,x,x,x,c,dc,z
mov
A,#40h
;Clear watchdog timer and initial system mode
b0mov
OSCM,A
call
call
b0bset
ClrRAM
SysInit
FGIE
;Clear RAM
;System initial
;Enable global interrupt
;------------------------------------------------------------------------------; Main routine
;------------------------------------------------------------------------------Main:
b0bset
FWDRST
;Clear watchdog timer
call
MnApp
jmp
Main
;------------------------------------------------------------------------------; Main application
;------------------------------------------------------------------------------MnApp:
; Put your main program here
ret
;----------------------------------; Jump table routine
;----------------------------------ORG
0x0100
;The jump table should start from the head
;of boundary.
b0mov
A,Wk00
and
A,#3
ADD
PCL,A
jmp
JmpSub0
jmp
JmpSub1
jmp
JmpSub2
;-----------------------------------
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SN8P1600
8-bit micro-controller
JmpSub0:
; Subroutine 1
jmp
JmpExit
JmpSub1:
; Subroutine 2
jmp
JmpExit
JmpSub2:
; Subroutine 3
jmp
JmpExit
JmpExit:
ret
;Return Main
;------------------------------------------------------------------------------; Isr (Interrupt Service Routine)
; Arguments :
; Returns
:
; Reg Change:
;------------------------------------------------------------------------------Isr:
;----------------------------------; Save ACC
;----------------------------------b0xch
A,AccBuf
b0mov
b0mov
A,PFLAG
PflagBuf,A
;B0xch instruction do not change C,Z flag
;----------------------------------; Interrupt service routine
;----------------------------------b0bts0
jmp
b0bts0
jmp
FP00IRQ
INT0isr
FTC0IRQ
TC0isr
;----------------------------------; Exit interrupt service routine
;----------------------------------IsrExit:
b0mov
b0mov
b0xch
A, PflagBuf
PFLAG, A
A,AccBuf
reti
SONiX TECHNOLOGY CO., LTD
;Restore the PFlag
;Restore the Reg. A
;B0xch instruction do not change C,Z flag
;Exit the interrupt routine
Page 81
Revision 1.94
SN8P1600
8-bit micro-controller
;------------------------------------------------------------------------------; INT0 interrupt service routine
;------------------------------------------------------------------------------INT0isr:
b0bclr
FP00IRQ
;Process P0.0 external interrupt here
jmp
IsrExit
;------------------------------------------------------------------------------; TC0 interrupt service routine
;------------------------------------------------------------------------------TC0isr:
b0bclr
FTC0IRQ
;Process TC0 interrupt here
jmp
IsrExit
;------------------------------------------------------------------------------; SysInit
; System initial to define Register, RAM, I/O, Timer......
;------------------------------------------------------------------------------SysInit:
ret
;------------------------------------------------------------------------------; ClrRAM
; Use index @YZ to clear RAM (00h~2Fh)
;------------------------------------------------------------------------------ClrRAM:
clr
b0mov
ClrRAM10:
clr
decms
jmp
clr
Y
Z,#0x2f
;
;Set @YZ address from 2fh
@YZ
Z
ClrRAM10
@YZ
;Clear @YZ content
;z = z – 1 , skip next if z=0
;Clear address $00
ret
;------------------------------------------------------------------------------ENDP
SONiX TECHNOLOGY CO., LTD
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Revision 1.94
SN8P1600
8-bit micro-controller
CHIP DECLARATION IN ASSEMBLER
Assembler
OTP Device Part Number
MASK Device Part Number
CHIP SN8P1602
SN8P1602
SN8A1602A
CHIP SN8P1603
SN8P1603
SN8A1602A
CHIP SN8P1604
SN8P1604
SN8A1604A
PROGRAM CHECK LIST
Item
Undefined Bits
PWM1
Interrupt
Non-Used I/O
Sleep Mode
Stack Buffer
Description
All bits those are marked as “0” (undefined bits) in system registers should be set “0” to
avoid unpredicted system errors.
Set PWM1 (P5.3) pin as output mode.
Do not enable interrupt before initializing RAM.
Non-used I/O ports should be set as output low mode or pull-up at input mode to save
current consumption.
Enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup.
Be careful of function call and interrupt service routine operation. Don’t let stack buffer
overflow or underflow.
1. Write 0x7F into STKP register to initial stack pointer and disable global interrupt
System Initial
2. Clear all RAM.
3. Initialize all system register even unused registers.
1. Enable OSG and High_Clk / 2 code option together
2. Enable the watchdog option to protect system crash.
Noisy Immunity
3. Non-used I/O ports should be set as output low mode
4. Constantly refresh important system registers and variables in RAM to avoid system
crash by a high electrical fast transient noise.
5. Enable the LVD option to improve the power on reset or brown-out reset performance
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SN8P1600
8-bit micro-controller
13 INSTRUCTION SET TABLE
Field
M
O
V
E
A
R
I
T
H
M
E
T
I
C
L
O
G
I
C
P
R
O
C
E
S
S
B
R
A
N
C
H
M
I
S
C
Note:
Mnemonic
MOV
A,M
MOV
M,A
B0MOV
A,M
B0MOV
M,A
MOV
A,I
B0MOV
M,I
XCH
A,M
B0XCH
A,M
MOVC
A←M
M←A
A ← M (bnak 0)
M (bank 0) ← A
A←I
M ← I, (M = only for Working registers R, Y, Z , RBANK & PFLAG)
A ←→M
A ←→M (bank 0)
R, A ← ROM [Y,Z]
ADC
ADC
ADD
ADD
B0ADD
ADD
SBC
SBC
SUB
SUB
SUB
DAA
A,M
M,A
A,M
M,A
M,A
A,I
A,M
M,A
A,M
M,A
A,I
A ← A + M + C, if occur carry, then C=1, else C=0
M ← A + M + C, if occur carry, then C=1, else C=0
A ← A + M, if occur carry, then C=1, else C=0
M ← A + M, if occur carry, then C=1, else C=0
M (bank 0) ← M (bank 0) + A, if occur carry, then C=1, else C=0
A ← A + I, if occur carry, then C=1, else C=0
A ← A - M - /C, if occur borrow, then C=0, else C=1
M ← A - M - /C, if occur borrow, then C=0, else C=1
A ← A - M, if occur borrow, then C=0, else C=1
M ← A - M, if occur borrow, then C=0, else C=1
A ← A - I, if occur borrow, then C=0, else C=1
To adjust ACC’s data format from HEX to DEC.
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
A,M
M,A
A,I
A,M
M,A
A,I
A,M
M,A
A,I
SWAP
SWAPM
RRC
RRCM
RLC
RLCM
CLR
BCLR
BSET
B0BCLR
B0BSET
CMPRS
CMPRS
INCS
INCMS
DECS
DECMS
BTS0
BTS1
B0BTS0
B0BTS1
JMP
CALL
RET
RETI
NOP
Description
C
-
DC
-
Z
√
√
-
Cycle
1
1
1
1
1
1
1
1
2
√
√
√
√
√
√
√
√
√
√
√
-
√
√
√
√
√
√
√
√
√
√
√
-
1
1
1
1
1
1
1
1
1
1
1
1
A ← A and M
M ← A and M
A ← A and I
A ← A or M
M ← A or M
A ← A or I
A ← A xor M
M ← A xor M
A ← A xor I
√
√
√
√
√
√
√
√
√
√
√
√
-
-
1
1
1
1
1
1
1
1
1
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
A (b3~b0, b7~b4) ←M(b7~b4, b3~b0)
M(b3~b0, b7~b4) ← M(b7~b4, b3~b0)
A ← RRC M
M ← RRC M
A ← RLC M
M ← RLC M
M←0
M.b ← 0
M.b ← 1
M(bank 0).b ← 0
M(bank 0).b ← 1
√
√
√
√
-
-
√
√
√
√
√
√
√
√
√
-
A,I
A,M
M
M
M
M
M.b
M.b
M.b
M.b
d
d
ZF,C ← A - I, If A = I, then skip next instruction
ZF,C ← A – M, If A = M, then skip next instruction
A ← M + 1, If A = 0, then skip next instruction
M ← M + 1, If M = 0, then skip next instruction
A ← M - 1, If A = 0, then skip next instruction
M ← M - 1, If M = 0, then skip next instruction
If M.b = 0, then skip next instruction
If M.b = 1, then skip next instruction
If M(bank 0).b = 0, then skip next instruction
If M(bank 0).b = 1, then skip next instruction
PC15/14 ← RomPages1/0, PC13~PC0 ← d
Stack ← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d
√
√
-
-
√
√
-
1+S
1+S
1+S
1+S
1+S
1+S
1+S
1+S
1+S
1+S
2
2
PC ← Stack
PC ← Stack, and to enable global interrupt
No operation
-
-
-
2
2
1
1
1
1
1
1
1
1
1
1
1
1
Any instruction that read/write from OSCM, will add an extra cycle.
SONiX TECHNOLOGY CO., LTD
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SN8P1600
8-bit micro-controller
14 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(All of the voltages referenced to Vss)
Supply voltage (Vdd) ………………………………………………………………………………………………………………………… - 0.3V ~ 6.0V
Input in voltage (Vin)……………………………………………………………………………………………………Vss - 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr)……………………………………………………………………………………………-20°C ~ + 70°C
Storage ambient temperature (Tstor)……………………………………………………………………………………………-30°C ~ + 125°C
Power consumption (Pc)………………………………………………………………………………………………………………………………………………500 mW
STANDARD ELECTRICAL CHARACTERISTICS
SN8P1602
(All of voltages referenced to Vss, Vdd = 5.0V, fosc = 3.579545 MHz, ambient temperature is 25°C unless otherwise notice.)
PARAMETER
SYM.
Operating voltage
Vdd
RAM Data Retention voltage
Vdr
ViL1
ViL2
ViL3
ViL4
ViH1
ViH2
ViH3
ViH4
Ilekg
Ilekg
IoH
IoL
IoH
IoL
Tint0
Fosc
Input Low Voltage
Input High Voltage
Reset pin leakage current
I/O port input leakage current
Port1 output source current
sink current
Port2 output source current
sink current
INTn trigger pulse width
Oscillator Frequency
Idd1
Supply Current
(LVD OFF)
Idd2
Idd3
LVD Detect Voltage
LVD current
Vdet
Ilvd
DESCRIPTION
Normal mode, Vpp = Vdd (Check OSG note)
Programming mode, Vpp = 12.5V
All input pins except those specified below
Input with Schmitt trigger buffer - Port0
Reset pin ; Xin ( in RC mode )
Xin ( in X’tal mode )
All input pins except those specified below
Input with Schmitt trigger buffer –Port0
Reset pin ; Xin ( in RC mode )
Xin ( in X’tal mode )
Vin = Vdd
Pull-up resistor disable, Vin = Vdd
Vop = Vdd – 0.5V
Vop = Vss + 0.5V
Vop = Vdd – 0.5V
Vop = Vss + 0.5V
INT0 interrupt request pulse width
Crystal type or ceramic resonator
VDD = 3V, RC type for external mode
VDD = 5V, RC type for external mode
Vdd= 5V 4Mhz
Run Mode
Vdd= 3V 4Mhz
Vdd= 3V 32768Hz
Vdd= 5V 32KHz Int RC
Slow mode
(Stop High Clock)
Vdd= 3V 16KHz Int RC
Vdd= 5V
Sleep mode
Vdd= 3V (SN8P1602)
Low voltage detect level
LVD enable operating current
SONiX TECHNOLOGY CO., LTD
Page 85
MIN.
2.2
4.5
Vss
Vss
Vss
Vss
0.7Vdd
0.8Vdd
0.9Vdd
0.7Vdd
2/fcpu
32768
2.4
-
TYP.
5.0
5.0
1.5
15
15
15
15
4M
6M
10M
7
1.7
50
80
15
9
2.5
2.5
100
MAX.
5.5
5.5
0.3Vdd
0.2Vdd
0.3Vdd
0.3Vdd
Vdd
Vdd
Vdd
Vdd
1
2
16M
15
3.5
100
150
30
18
6
2.8
180
UNIT
V
V
V
V
V
V
V
V
V
V
uA
uA
mA
mA
cycle
Hz
mA
mA
uA
uA
uA
uA
uA
V
uA
Revision 1.94
SN8P1600
8-bit micro-controller
SN8P1603
(All of voltages referenced to Vss, Vdd = 5.0V, fosc = 3.579545 MHz, ambient temperature is 25°C unless otherwise notice.)
PARAMETER
SYM.
Operating voltage
Vdd
RAM Data Retention voltage
Vdr
ViL1
ViL2
ViL3
ViL4
ViH1
ViH2
ViH3
ViH4
Ilekg
Ilekg
IoH
IoL
IoH
IoL
Tint0
Fosc
Input Low Voltage
Input High Voltage
Reset pin leakage current
I/O port input leakage current
Port1 output source current
sink current
Port2 output source current
sink current
INTn trigger pulse width
Oscillator Frequency
Idd1
Supply Current
(LVD ON)
Idd2
Idd3
LVD Detect Voltage
Vdet
DESCRIPTION
Normal mode, Vpp = Vdd (Check OSG note)
Programming mode, Vpp = 12.5V
All input pins except those specified below
Input with Schmitt trigger buffer - Port0
Reset pin ; Xin ( in RC mode )
Xin ( in X’tal mode )
All input pins except those specified below
Input with Schmitt trigger buffer –Port0
Reset pin ; Xin ( in RC mode )
Xin ( in X’tal mode )
Vin = Vdd
Pull-up resistor disable, Vin = Vdd
Vop = Vdd – 0.5V
Vop = Vss + 0.5V
Vop = Vdd – 0.5V
Vop = Vss + 0.5V
INT0 interrupt request pulse width
Crystal type or ceramic resonator
VDD = 3V, RC type for external mode
VDD = 5V, RC type for external mode
Vdd= 5V 4Mhz
Run Mode
Vdd= 3V 4Mhz
Vdd= 3V 32768Hz
Vdd= 5V 32KHz Int RC
Slow mode
(Stop High Clock)
Vdd= 3V 16KHz Int RC
Vdd= 5V
Sleep mode
Vdd= 3V (SN8P1603)
Low voltage detect level
SONiX TECHNOLOGY CO., LTD
Page 86
MIN.
3
4.5
Vss
Vss
Vss
Vss
0.7Vdd
0.8Vdd
0.9Vdd
0.7Vdd
2/fcpu
32768
2.4
TYP.
5.0
5.0
1.5
15
15
15
15
4M
6M
10M
7.5
1.8
130
300
100
200
70
2.5
MAX.
5.5
5.5
0.3Vdd
0.2Vdd
0.3Vdd
0.3Vdd
Vdd
Vdd
Vdd
Vdd
1
2
16M
15
3.6
300
600
200
400
150
2.8
UNIT
V
V
V
V
V
V
V
V
V
V
uA
uA
mA
mA
cycle
Hz
mA
mA
uA
uA
uA
uA
uA
V
Revision 1.94
SN8P1600
8-bit micro-controller
SN8P1604
(All of voltages referenced to Vss, Vdd = 5.0V, fosc = 3.579545 MHz, ambient temperature is 25°C unless otherwise notice.)
PARAMETER
SYM.
Operating voltage
Vdd
RAM Data Retention voltage
Vdr
ViL1
ViL2
ViL3
ViL4
ViH1
ViH2
ViH3
ViH4
Ilekg
Rup
Ilekg
IoH
IoL
IoH
IoL
Tint0
Fosc
Input Low Voltage
Input High Voltage
Reset pin leakage current
I/O port pull-up resistor
I/O port input leakage current
Port1 output source current
sink current
Port2 output source current
sink current
INTn trigger pulse width
Oscillator Frequency
Idd1
Supply Current
(LVD OFF)
Idd2
Idd3
LVD Detect Voltage
LVD current
Vdet
Ilvd
DESCRIPTION
Normal mode, Vpp = Vdd (Check OSG note)
Programming mode, Vpp = 12.5V
All input pins except those specified below
Input with Schmitt trigger buffer - Port0
Reset pin ; Xin ( in RC mode )
Xin ( in X’tal mode )
All input pins except those specified below
Input with Schmitt trigger buffer –Port0
Reset pin ; Xin ( in RC mode )
Xin ( in X’tal mode )
Vin = Vdd
Vin = Vss , Vdd = 5V
Pull-up resistor disable, Vin = Vdd
Vop = Vdd – 0.5V
Vop = Vss + 0.5V
Vop = Vdd – 0.5V
Vop = Vss + 0.5V
INT0 ~ INT2 interrupt request pulse width
Crystal type or ceramic resonator
VDD = 3V, RC type for external mode
VDD = 5V, RC type for external mode
Vdd= 5V 4Mhz
Run Mode
Vdd= 3V 4Mhz
Vdd= 3V 32768Hz
Vdd= 5V 32KHz Int RC
Slow mode
(Stop High Clock)
Vdd= 3V 16KHz Int RC
Vdd= 5V
Sleep mode
Vdd= 3V (SN8P1602)
Low voltage detect level
LVD enable operating current
SONiX TECHNOLOGY CO., LTD
Page 87
MIN.
2.2
4.5
Vss
Vss
Vss
Vss
0.7Vdd
0.8Vdd
0.9Vdd
0.7Vdd
2/fcpu
32768
2.4
-
TYP.
5.0
5.0
1.5
50
15
15
15
15
4M
6M
10M
7
1.7
50
80
15
9
2.5
2.5
100
MAX.
5.5
5.5
0.3Vdd
0.2Vdd
0.3Vdd
0.3Vdd
Vdd
Vdd
Vdd
Vdd
1
2
16M
15
3.5
100
150
30
18
6
2.8
180
UNIT
V
V
V
V
V
V
V
V
V
V
uA
KΩ
uA
mA
mA
cycle
Hz
mA
mA
uA
uA
uA
uA
uA
V
uA
Revision 1.94
SN8P1600
8-bit micro-controller
OSG Note :
Notice : The minimum working voltage is depended on the working frequency and OSG status.
Turn on the OSG code option in the SN8ASM will improve the EMI performance, but it will increase the lowest valid
working voltage level.
The safe operating voltage must above the curve (max.) to get a stable power environment.
Typical VDD vs. Frequency (OSG On)
OSG On --Voltage v.s. Frequency
Working Voltage (V)
6
5
4
OSG On (Max.)
3
OSG On (Typical)
2
1
0
1
2
4
6
8
10 12 16 18 20 22 24
Working frequency (Mhz)
Typical VDD vs. Frequency (OSG Off)
OSG Off-- Voltage v.s. Frequency
3
Voltage(V)
2.5
2
OSG Off (Max.)
1.5
OSG Off (Typical)
1
0.5
0
1
2
4
6
8
10 12 16 18 20 22 24
Frequency(Mhz)
Notice : The system working frequency is only warranty under 16Mhz.
SONiX TECHNOLOGY CO., LTD
Page 88
Revision 1.94
SN8P1600
8-bit micro-controller
15 PACKAGE INFORMATION
P-DIP 18 PIN
SYMBOLS
A
A1
A2
D
E
E1
L
ｅB
θ°
MIN
NOR
MAX
MIN
(inch)
0.015
0.125
0.880
0.245
0.115
0.335
0°
SONiX TECHNOLOGY CO., LTD
0.130
0.900
0.300
0.250
0.130
0.355
7°
NOR
MAX
(mm)
0.210
0.135
0.920
0.381
3.175
22.352
0.255
0.150
0.375
15°
6.223
2.921
8.509
0°
Page 89
3.302
22.860
7.620
6.350
3.302
9.017
7°
5.334
3.429
23.368
6.477
3.810
9.525
15°
Revision 1.94
SN8P1600
8-bit micro-controller
SOP 18 PIN
SYMBOLS
A
A1
D
E
H
L
θ°
MIN
NOR
MAX
MIN
(inch)
0.093
0.004
0.447
0.291
0.394
0.016
0°
SONiX TECHNOLOGY CO., LTD
0.099
0.008
0.455
0.295
0.407
0.033
4°
NOR
MAX
(mm)
0.104
0.012
0.463
0.299
0.419
0.050
8°
Page 90
2.362
0.102
11.354
7.391
10.008
0.406
0°
2.502
0.203
11.557
7.493
10.325
0.838
4°
2.642
0.305
11.760
7.595
10.643
1.270
8°
Revision 1.94
SN8P1600
8-bit micro-controller
SSOP 20 PIN
SYMBOLS
A
A1
A2
b
c
D
E
E1
[e]
h
L
L1
ZD
Y
θ°
MIN
NOR
MAX
MIN
(inch)
0.053
0.004
0.008
0.007
0.337
0.228
0.150
0.010
0.016
0.039
0°
SONiX TECHNOLOGY CO., LTD
0.063
0.006
0.010
0.008
0.341
0.236
0.154
0.025
0.017
0.025
0.041
0.059
-
NOR
MAX
(mm)
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
1.350
0.100
0.200
0.180
8.560
5.800
3.800
0.020
0.050
0.043
0.250
0.400
1.000
0.004
8°
0°
Page 91
1.600
0.150
0.254
0.203
8.660
6.000
3.900
0.635
0.420
0.635
1.050
1.500
-
1.750
0.250
1.500
0.300
0.250
8.740
6.200
4.000
0.500
1.270
1.100
0.100
8°
Revision 1.94
SN8P1600
8-bit micro-controller
SOP28PIN
SYMBOLS
A
A1
D
E
H
L
θ°
MIN
NOR
MAX
(inch)
0.093
0.004
0.697
0.291
0.394
0.016
0°
SONiX TECHNOLOGY CO., LTD
MIN
NOR
MAX
2.502
0.203
17.907
7.493
10.325
0.838
4°
2.642
0.305
18.110
7.595
10.643
1.270
8°
(mm)
0.099
0.008
0.705
0.295
0.407
0.033
4°
0.104
0.012
0.713
0.299
0.419
0.050
8°
Page 92
2.362
0.102
17.704
7.391
10.008
0.406
0°
Revision 1.94
SN8P1600
8-bit micro-controller
SK-DIP28PIN
SYMBOLS
A
A1
A2
D
E
E1
L
ｅB
θ°
MIN
NOR
MAX
(inch)
0.015
0.114
1.390
0.310
0.283
0.115
0.330
0°
SONiX TECHNOLOGY CO., LTD
MIN
NOR
MAX
3.302
35.306
5.334
3.429
35.560
7.315
3.302
8.890
7°
7.442
3.810
9.398
15°
(mm)
0.130
1.390
0.210
0.135
1.400
0.288
0.130
0.350
7°
0.293
0.150
0.370
15°
Page 93
0.381
2.896
35.306
7.874
7.188
2.921
8.382
0°
Revision 1.94
SN8P1600
8-bit micro-controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or
design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed,
intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a
situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such
unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries,
affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use
even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C.
Tel: 886-3-551 0520
Fax: 886-3-551 0523
Taipei Office:
Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C.
Tel: 886-2-2759 1980
Fax: 886-2-2759 8180
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Address: Flat 3 9/F Energy Plaza 92 Granville Road, Tsimshatsui East Kowloon.
Tel: 852-2723 8086
Fax: 852-2723 9179
Technical Support by Email:
[email protected]
SONiX TECHNOLOGY CO., LTD
Page 94
Revision 1.94