NEC D43256BGU

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD43256B
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
Description
The µPD43256B is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available (L, LL, A, and B versions). And A and B versions are wide voltage operations.
The µPD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Wide voltage range (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• 2 V data retention
• OE input for easy application
Part number
µPD43256B-L
µPD43256B-LL
µPD43256B-A
µPD43256B-BNote 2
Access time
ns (MAX.)
Operating
supply voltage
V
Operating
temperature
°C
Standby
supply current
µA (MAX.)
Data retention
supply currentNote 1
µA (MAX.)
70, 85
4.5 to 5.5
0 to 70
50
3
15
2
70, 85
85,
100Note 2,
120Note 2
100, 120, 150
3.0 to 5.5
2.7 to 5.5
Notes 1. TA ≤ 40 ˚C, VCC = 3 V
2. Access time : 85 ns (MAX.) (VCC = 4.5 to 5.5 V)
Version X and P
This data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in
the fifth character position in a lot number signifies version X, letter P, version P.
JAPAN
D43256B
Lot number
The information in this document is subject to change without notice.
Document No. M10770EJ9V0DS00 (9th edition)
Date Published May 1997 N
Printed in Japan
The mark
shows major revised points.
©
1990, 1993, 1994
µPD43256B
Ordering Information
Part number
µ PD43256BCZ-70L
µ PD43256BCZ-85L
Package
28-pin plastic
DIP (600 mil)
µ PD43256BCZ-70LL
µ PD43256BGU-85L
Operating
temperature
˚C
Remark
70
4.5 to 5.5
0 to 70
L Version
85
70
70
µ PD43256BGU-85LL
85
µ PD43256BGU-A85
85
µ PD43256BGU-A10
100
µ PD43256BGU-A12
120
µ PD43256BGU-B10
100
µ PD43256BGU-B12
120
µ PD43256BGW-85LL-9JL
µ PD43256BGW-A85-9JL
µ PD43256BGW-A10-9JL
70
85
100
µ PD43256BGW-B12-9JL
120
µ PD43256BGW-B15-9JL
150
µ PD43256BGW-A10-9KL
A Version
2.7 to 5.5
B Version
4.5 to 5.5
LL Version
3.0 to 5.5
A Version
2.7 to 5.5
B Version
4.5 to 5.5
LL Version
3.0 to 5.5
A Version
2.7 to 5.5
B Version
100
µ PD43256BGW-B10-9JL
µ PD43256BGW-A85-9KL
3.0 to 5.5
85
120
µ PD43256BGW-85LL-9KL
LL Version
150
28-pin plastic
TSOP (I)
(8 × 13.4 mm)
(Normal bent)
µ PD43256BGW-A12-9JL
µ PD43256BGW-70LL-9KL
L Version
85
µ PD43256BGU-70LL
µ PD43256BGW-70LL-9JL
LL Version
85
28-pin plastic
SOP (450 mil)
µ PD43256BGU-B15
2
Operating
supply voltage
V
70
µ PD43256BCZ-85LL
µ PD43256BGU-70L
Access time
ns (MAX.)
28-pin plastic
TSOP (I)
(8 × 13.4 mm)
(Reverse bent)
70
85
85
100
µ PD43256BGW-A12-9KL
120
µ PD43256BGW-B10-9KL
100
µ PD43256BGW-B12-9KL
120
µ PD43256BGW-B15-9KL
150
µPD43256B
Pin Configuration (Marking Side)
28-pin plastic DIP (600 mil)
µ PD43256BCZ
28-pin plastic SOP (450 mil)
µ PD43256BGU
A14
1
28
VCC
A12
2
27
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CS
A0
10
19
I/O8
I/O1
11
18
I/O7
I/O2
12
17
I/O6
I/O3
13
16
I/O5
GND
14
15
I/O4
A0 - A14
: Address inputs
I/O1 - I/O8 : Data inputs/outputs
CS
: Chip Select
WE
: Write Enable
OE
: Output Enable
V CC
: Power supply
GND
: Ground
3
µPD43256B
28-pin plastic TSOP (I) (8 × 13.4 mm)
(Normal bent)
µ PD43256BGW-9JL
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
28-pin plastic TSOP (I) (8 × 13.4 mm)
(Reverse bent)
µ PD43256BGW-9KL
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
µPD43256B
A0
|
A14
I/O1
|
I/O8
Row decoder
Address buffer
Block Diagram
Memory cell array
262,144 bits
Input data
controller
Sense/Switch
Output data
controller
Column decoder
Address buffer
CS
OE
WE
VCC
GND
Truth Table
CS
OE
WE
Mode
I/O
Supply current
H
×
×
Not selected
High impedance
I SB
L
H
H
Output disable
L
×
L
Write
D IN
L
L
H
Read
D OUT
I CCA
Remark ×: Don’t care
5
µPD43256B
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply voltage
V CC
–0.5 Note to +7.0
V
Input/Output voltage
VT
–0.5 Note to V CC + 0.5
V
Operating ambient temperature
TA
0 to 70
˚C
Storage temperature
T stg
–55 to +125
˚C
Note
–3.0 V (MIN.) (Pulse width 50 ns)
Caution Exposing the device to stress above those listed in absolute maximum ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational sections of this characteristics. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
µ PD43256B-A
µ PD43256B-B
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Supply voltage
V CC
4.5
5.5
3.0
5.5
2.7
5.5
V
High level input voltage
V IH
2.2
V CC + 0.5
2.2
V CC + 0.5
2.2
V CC + 0.5
V
Low level input voltage
V IL
–0.3 Note
+0.8
–0.3 Note
+0.5
–0.3 Note
+0.5
V
Operating ambient temperature
TA
0
70
0
70
0
70
˚C
Note
6
Symbol
µ PD43256B-L
µ PD43256B-LL
–3.0 V (MIN.) (Pulse width 50 ns)
µPD43256B
DC Characteristics (Recommended operating conditions unless otherwise noted) (1/2)
µ PD43256B-L
Parameter
Symbol
Test conditions
µ PD43256B-LL
MIN. TYP. MAX. MIN. TYP. MAX.
Unit
Input leakage current
I LI
V IN = 0 V to VCC
–1.0
+1.0 –1.0
+1.0
µA
I/O leakage current
I LO
V I/O = 0 V to V CC
OE = V IH or CS = V IH or WE = V IL
–1.0
+1.0 –1.0
+1.0
µA
mA
Operating supply current
Standby supply current
High level output voltage
Low level output voltage
I CCA1
CS = V IL, Minimum cycle time,
I I/O = 0 mA
45
45
I CCA2
CS = V IL, I I/O = 0 mA
10
10
I CCA3
CS ≤ 0.2 V, Cycle = 1 MHz,
I I/O = 0 mA
V IL ≤ 0.2 V, V IH ≥ V CC – 0.2 V
10
10
I SB
CS = V IH
3
3
mA
I SB1
CS ≥ V CC – 0.2 V
15
µA
V OH1
I OH = –1.0 mA
2.4
2.4
V OH2
I OH = –0.1 mA
V CC–0.5
V CC–0.5
V OL
I OL = 2.1 mA
1.0
50
0.5
0.4
V
0.4
V
Remarks 1. V IN: Input voltage
2. These DC Characteristics are in common regardless of package types.
7
µPD43256B
DC Characteristics (Recommended operating conditions unless otherwise noted) (2/2)
µ PD43256B-A
Parameter
Symbol
Test conditions
µ PD43256B-B
MIN. TYP. MAX. MIN. TYP. MAX.
Unit
Input leakage current
I LI
V IN = 0 V to VCC
–1.0
+1.0 –1.0
+1.0
µA
I/O leakage current
I LO
V I/O = 0 V to V CC
CS = V IH or WE = V IL or OE = V IH
–1.0
+1.0 –1.0
+1.0
µA
mA
Operating supply current
I CCA1
I CCA2
CS = V IL,
µ PD43256B-A85
Minimum cycle time, µ PD43256B-A10
I I/O = 0 mA
µ PD43256B-A12
45
—
µ PD43256B-B10
µ PD43256B-B12
µ PD43256B-B15
—
45
V CC ≤ 3.3 V
—
20
10
10
—
5
10
10
—
5
3
3
—
2
CS = V IL, I I/O = 0 mA
V CC ≤ 3.3 V
I CCA3
CS ≤ 0.2 V, Cycle = 1 MHz,
I I/O = 0 mA, V IL ≤ 0.2 V,
V IH ≥ V CC – 0.2 V
Standby supply current
I SB
V CC ≤ 3.3 V
CS = V IH
V CC ≤ 3.3 V
I SB1
CS ≥ V CC – 0.2 V
0.5
V CC ≤ 3.3 V
High level output voltage
V OH1
V OH2
V OL
V OL1
0.5
15
—
0.5
10
I OH = –1.0 mA, VCC ≥ 4.5 V
2.4
2.4
I OH = –0.5 mA, V CC < 4.5 V
2.4
2.4
I OH = –0.1 mA
—
—
VCC –0.1
VCC –0.1
I OH = –0.02 mA
Low level output voltage
15
mA
µA
V
I OL = 2.1 mA, V CC ≥ 4.5 V
0.4
0.4
I OL = 1.0 mA, V CC < 4.5 V
0.4
0.4
I OL = 0.02 mA
0.1
0.1
V
Remarks 1. V IN: Input voltage
2.
These DC characteristics are in common regardless of package types.
Capacitance (T A = 25 ˚C, f = 1 MHz)
Parameter
Symbol
Test conditions
MIN.
MAX.
Unit
Input capacitance
CIN
V IN = 0 V
5
pF
Input/Output capacitance
CI/O
V I/O = 0 V
8
pF
Remarks 1. V IN: Input voltage
2. These parameters are periodically sampled and not 100 % tested.
8
TYP.
µPD43256B
AC Characteristics (Recommended operating conditions unless otherwise noted)
AC Test Conditions
Input waveform (Rise/fall time ≤ 5 ns)
Input pulse levels
0.8 V to 2.2 V: µ PD43256B-L, 43256B-LL
0.5 V to 2.2 V: µ PD43256B-A, 43256B-B
1.5 V
Test points
1.5 V
1.5 V
Test points
1.5 V
Output waveform
Output load
µ PD43256B-A, 43256B-B : 1TTL + 100 pF
µ PD43256B-L, 43256B-LL:
AC characteristics with notes should be measured with the output load shown in
Figure 1 and Figure 2.
Figure 1
Figure 2
(For t AA, tACS , t OE, t OH)
(For t CHZ, t CLZ , t OHZ, t OLZ , t WHZ, t OW )
+5 V
+5 V
1.8 kΩ
I/O (Output)
1.8 kΩ
I/O (Output)
990 Ω
Remark
100 pF
CL
990 Ω
5 pF
CL
C L includes capacitances of the probe and jig, and stray capacitances.
9
µPD43256B
Read Cycle (1/2)
V CC ≥ 4.5 V
Parameter
µ PD43256B-85
µ PD43256B-A85/A10/A12
µ PD43256B-B10/B12/B15
µ PD43256B-70
Symbol
MIN.
MAX.
MIN.
70
Unit Condition
MAX.
Read cycle time
t RC
85
ns
Address access time
t AA
70
85
ns
CS access time
t ACS
70
85
ns
OE access time
t OE
35
40
ns
Output hold from address change
t OH
10
10
ns
CS to output in low impedance
t CLZ
10
10
ns
OE to output in low impedance
t OLZ
5
5
ns
CS to output in high impedance
t CHZ
30
30
ns
OE to output in high impedance
t OHZ
30
30
ns
Note 1
Note 2
Notes 1. See the output load shown in Figure 1 except for µ PD43256B-A, 43256B-B.
2. See the output load shown in Figure 2 except for µ PD43256B-A, 43256B-B.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
V CC ≥ 3.0 V
Parameter
V CC ≥ 2.7 V
Symbol µ PD43256B-A85 µ PD43256B-A10 µ PD43256B-A12 µ PD43256B-B10 µ PD43256B-B12 µ PD43256B-B15 Unit
Condition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time
t RC
85
100
120
100
120
150
ns
Address access time
t AA
85
100
120
100
120
150 ns Note
CS access time
t ACS
85
100
120
100
120
150 ns
OE access time
t OE
50
60
60
60
60
Output hold from address change
tOH
10
10
10
10
10
10
ns
CS to output in low impedance
tCLZ
10
10
10
10
10
10
ns
OE to output in low impedance
tOLZ
5
5
5
5
5
5
ns
CS to output in high impedance
tCHZ
35
35
40
35
40
50
ns
OE to output in high impedance
tOHZ
35
35
40
35
40
50
ns
70
ns
Note Loading condition is 1TTL + 100 pF.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
10
µPD43256B
Read Cycle Timing Chart
tRC
Address (Input)
tOH
tAA
tACS
CS (Input)
tCLZ
tCHZ
OE (Input)
tOE
tOHZ
tOLZ
I/O (Output)
Remark
High impedance
Data out
High impedance
In read cycle, WE should be fixed to high level.
11
µPD43256B
Write Cycle (1/2)
V CC ≥ 4.5 V
Parameter
µ PD43256B-85
µ PD43256B-A85/A10/A12
µ PD43256B-B10/B12/B15
µ PD43256B-70
Symbol
MIN.
MAX.
MIN.
Unit Condition
MAX.
Write cycle time
t WC
70
85
ns
CS to end of write
t CW
50
70
ns
Address valid to end of write
t AW
50
70
ns
Write pulse width
t WP
55
60
ns
Data valid to end of write
t DW
30
35
ns
Data hold time
t DH
0
0
ns
Address setup time
t AS
0
0
ns
Write recovery time
t WR
0
0
ns
WE to output in high impedance
t WHZ
Output active from end of write
t OW
30
30
10
ns
10
Note
ns
Note See the output load shown in Figure 2 except for µ PD43256B-A, 43256B-B.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
V CC ≥ 3.0 V
Parameter
V CC ≥ 2.7 V
Symbol µ PD43256B-A85 µ PD43256B-A10 µ PD43256B-A12 µ PD43256B-B10 µ PD43256B-B12 µ PD43256B-B15 Unit
Condition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time
t WC
85
100
120
100
120
150
ns
CS to end of write
t CW
70
70
90
70
90
100
ns
Address valid to end of write
t AW
70
70
90
70
90
100
ns
Write pulse width
t WP
60
60
80
60
80
90
ns
Data valid to end of write
t DW
60
60
70
60
70
80
ns
Data hold time
t DH
0
0
0
0
0
0
ns
Address setup time
t AS
0
0
0
0
0
0
ns
Write recovery time
t WR
0
0
0
0
0
0
ns
WE to output in high impedance
tWHZ
Output active from end of write
t OW
30
10
35
10
40
10
35
10
40
10
50
10
ns Note
ns
Note Loading condition is 1TTL + 100 pF.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
12
µPD43256B
Write Cycle Timing Chart 1 (WE Controlled)
tWC
Address (Input)
tCW
CS (Input)
tAW
tAS
tWP
tWR
WE (Input)
tOW
tWHZ
I/O (Input/Output)
Indefinite data out
tDW
High
impedance
Data in
tDH
High
impedance
Indefinite data out
Cautions 1. CS or WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE.
2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level,
read operation is executed. Therefore OE should be at high level to make the I/O pins high
impedance.
3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins
will remain high impedance state.
13
µPD43256B
Write Cycle Timing Chart 2 (CS Controlled)
tWC
Address (Input)
tAS
tCW
CS (Input)
tAW
tWP
tWR
WE (Input)
tDW
High impedance
I/O (Input)
tDH
Data In
High
impedance
Cautions 1. CS or WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
Remark Write operation is done during the overlap time of a low level CS and a low level WE.
14
µPD43256B
Low V CC Data Retention Characteristics
L Version ( µ PD43256B-L: T A = 0 to 70 ˚C)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
5.5
V
20 Note
µA
Data retention supply voltage V CCDR
CS ≥ V CC – 0.2 V
Data retention supply current
I CCDR
V CC = 3.0 V, CS ≥ V CC – 0.2 V
Chip deselection to data
retention mode
t CDR
0
ns
Operation recovery time
tR
5
ms
2.0
0.5
Note 3 µ A (T A ≤ 40 ˚C)
LL Version ( µ PD43256B-LL: T A = 0 to 70 ˚C)
A Version ( µ PD43256B-A: T A = 0 to 70 ˚C)
B Version ( µ PD43256B-B: T A = 0 to 70 ˚C)
Parameter
Symbol
Test conditions
MIN.
TYP.
Data retention supply voltage
V CCDR
CS ≥ V CC – 0.2 V
Data retention supply current
I CCDR
V CC = 3.0 V, CS ≥ V CC – 0.2 V
Chip deselection to data
retention mode
t CDR
0
ns
Operation recovery time
tR
5
ms
2.0
0.5
MAX.
Unit
5.5
V
7 Note
µA
Note 2 µ A (T A ≤ 40 ˚C), 1 µ A (T A ≤ 25 ˚C)
15
µPD43256B
Data Retention Timing Chart
tCDR
Data retention mode
tR
5.0 V
Note
4.5 V
VCC
CS
VIH (MIN.)
VCCDR
CS ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note
A Version: 3.0 V, B Version: 2.7 V
Remark The other pins (address, OE, WE, I/Os) can be in high impedance state.
16
µPD43256B
Package Drawings
28 PIN PLASTIC DIP (600 mil)
15
28
14
1
A
K
H
G
J
I
L
F
D
N
M
C
M
B
R
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch)
of its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS
INCHES
A
38.10 MAX.
1.500 MAX.
B
2.54 MAX.
0.100 MAX.
C
2.54 (T.P.)
D
0.50±0.10
0.100 (T.P.)
+0.004
0.020 –0.005
F
1.2 MIN.
0.047 MIN.
G
3.6±0.3
0.142±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.72 MAX.
0.226 MAX.
K
L
15.24 (T.P.)
13.2
0.600 (T.P.)
0.520
M
0.25 +0.10
–0.05
N
0.25
R
0 ~ 15 °
0.010 +0.004
–0.003
0.01
0 ~ 15°
P28C-100-600A1-1
17
µPD43256B
28 PIN PLASTIC SOP (450 mil)
28
15
P
detail of lead end
1
14
A
G
H
I
E
K
F
J
N
C
D
M
B
L
M
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
INCHES
A
19.05 MAX.
0.750 MAX.
B
1.27 MAX.
0.050 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40±0.10
0.016 +0.004
–0.005
E
0.2±0.1
0.008±0.004
F
3.0 MAX.
0.119 MAX.
G
2.55±0.1
0.100 +0.005
–0.004
H
11.8±0.3
0.465 +0.012
–0.013
I
8.4±0.1
0.331 +0.004
–0.005
J
1.7±0.2
0.067±0.008
K
0.20 +0.07
–0.03
0.008 +0.003
–0.002
L
0.7±0.2
0.028 +0.008
–0.009
M
0.12
0.005
N
0.10
P
5°±5°
0.004
5°±5°
P28GU-50-450A-1
18
µPD43256B
28PIN PLASTIC TSOP ( I ) (8×13.4)
1
28
detail of lead end
S
R
14
Q
15
P
J
I
A
G
H
L
B
C
N
D
M
M
K
NOTE
(1) Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
(2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.
<0.331 inch MAX.>)
ITEM MILLIMETERS
A
8.0±0.1
INCHES
0.315±0.004
B
C
0.6 MAX.
0.55 (T.P.)
0.024 MAX.
0.022 (T.P.)
D
0.22 +0.08
–0.07
0.009±0.003
G
H
1.0
12.4±0.2
0.039
0.488±0.008
I
11.8±0.1
0.465 +0.004
–0.005
J
0.8±0.2
0.031 +0.009
–0.008
K
0.145 +0.025
–0.015 0.006±0.001
L
0.5±0.1
0.020 +0.004
–0.005
M
0.08
0.003
N
0.10
0.004
P
13.4±0.2
0.528 +0.008
–0.009
Q
0.1±0.05
0.004±0.002
R
3 ° +7°
–3°
S
1.2 MAX.
3° +7°
–3°
0.048 MAX.
P28GW-55-9JL-1
19
µPD43256B
28PIN PLASTIC TSOP ( I ) (8×13.4)
1
28
detail of lead end
Q
R
S
14
15
K
M
D
N
M
H
L
C
I
J
A
B
G
P
NOTE
(1) Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
(2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.
<0.331 inch MAX.>)
ITEM MILLIMETERS
A
8.0±0.1
INCHES
0.315±0.004
B
C
0.6 MAX.
0.55 (T.P.)
0.024 MAX.
0.022 (T.P.)
D
0.22 +0.08
–0.07
0.009±0.003
G
H
1.0
12.4±0.2
0.039
0.488±0.008
I
11.8±0.1
0.465 +0.004
–0.005
J
0.8±0.2
0.031 +0.009
–0.008
K
0.145 +0.025
–0.015 0.006±0.001
L
0.5±0.1
0.020 +0.004
–0.005
M
0.08
0.003
N
0.10
0.004
P
13.4±0.2
0.528 +0.008
–0.009
Q
0.1±0.05
0.004±0.002
R
3 ° +7°
–3°
S
1.2 MAX.
3° +7°
–3°
0.048 MAX.
P28GW-55-9KL-1
20
µPD43256B
Recommended Soldering Conditions
The following conditions (See table below) must be met when soldering µ PD43256B. For more details, refer
to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case soldering is done
under different conditions.
Types of Surface Mount Device
µ PD43256BGU: 28-pin plastic SOP (450 mil)
µ PD43256BGW-9JL: 28-pin plastic TSOP (I) (8 × 13.4 mm) (Normal bent)
µ PD43256BGW-9KL: 28-pin plastic TSOP (I) (8 × 13.4 mm) (Reverse bent)
Please consult with our sales offices.
Type of Through Hole Mount Device
µ PD43256BCZ: 28-pin plastic DIP (600 mil)
Soldering process
Soldering conditions
Wave soldering
(only to leads)
Solder temperature: 260 ˚C or below,
Flow time: 10 seconds or below
Partial heating method
Terminal temperature: 300 ˚C or below,
Time: 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
21
µPD43256B
[MEMO]
22
µPD43256B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
23
µPD43256B
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
2