CXA2027Q Analog signal processor IC For the availability of this product, please contact the sales office. Description The CXA2027Q is an analog signal processor for CCD linear image sensor output signal. This device is suitable for 3 lines of full-color CCD linear image sensor (ILX516K/ILX518K/ILX520K: 3648 pixels × 3 lines/5363 pixels × 3 lines/7078 pixels × 3 lines). This device has a built-in sample-and-hold, clamp, multiplex, gain control amplifier circuits and can be connected directly with external AD converters. (Sony’s CXD2311AR, CXD1175AM or CXA1977R are recommended as AD converters.) Features • Sample-and-hold circuit • Pixel-clamp and line-clamp circuit • Multiplex circuit • ADC driver circuit • Gain control amplifier circuit • Offset control circuit • Clock frequency: 1.5 to 6MHz (after multiplex) Applications Color image scanner 48 pin QFP (Plastic) Absolute Maximum Ratings –0.3 to 7 V • Supply voltage VCC • Input voltage VI –0.3 to VCC + 0.3 V • Output voltage VO –0.3 to VCC + 0.3 V • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 640 mW Operating Conditions (Typ. in parentheses) • Supply voltage VCC 4.75 to 5.25 (5.0) V • Digital input voltage High VIH 3.5 to VCC (VCC) V • Digital input voltage Low VIL 0 to 0.8 (0) V • Operating temperature Topr 0 to +70 °C Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95210A78 CXA2027Q B-IN G-IN R-IN BUF SH MPX2 MPX1 CLP TD3 TD2 TD1 TD5 TD6 Block Diagram and Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 37 24 TD4 LPR 38 23 LCLP GCA LPG 39 LPB 40 D4-0 41 VCCA 42 D4-1 43 S/H GCA 21 VCCP S/H 19 GND 18 VRT VREF D/A GCA 17 LOG LOG LOG D/A D/A D/A LATCH LATCH LATCH D4-3 45 D4-4 20 SIGOUT Driver DC shift GCA S/H D4-2 44 22 GC 46 VRB 16 CLPC 15 LD4 14 LD3 VCCD 47 D5-0 48 D/A 13 1 2 3 4 5 6 7 8 9 10 11 12 D5-1 D5-2 D5-3 D5-4 D6-0 D6-1 D6-2 D6-3 D6-4 D6-5 LD0 LD1 D/A –2– LD2 CXA2027Q Pin Description Pin Symbol (I/O) No. Typical pin voltage Equivalent circuit DC Description AC 48 D5-0 (I) 5-bit data input pin 1 for G channel pixel clamp voltage adjustment (LSB) 1 D5-1 (I) 5-bit data input pin 2 for G channel pixel clamp voltage adjustment 2 D5-2 (I) 5-bit data input pin 3 for G channel pixel clamp voltage adjustment 3 D5-3 (I) 5-bit data input pin 4 for G channel pixel clamp voltage adjustment VCCD 4 D5-4 (I) 1.5k Lo: 0 to 0.8V Hi: 3.5 to 5V 41 VCCD 1.8V 48 129 D4-0 (I) 100µ 5-bit data input pin 5 for G channel pixel clamp voltage adjustment (MSB) 5-bit data input pin 1 for B channel pixel clamp voltage adjustment (LSB) 43 D4-1 (I) 5-bit data input pin 2 for B channel pixel clamp voltage adjustment 44 D4-2 (I) 5-bit data input pin 3 for B channel pixel clamp voltage adjustment 45 D4-3 (I) 5-bit data input pin 4 for B channel pixel clamp voltage adjustment 46 D4-4 (I) 5-bit data input pin 5 for B channel pixel clamp voltage adjustment (MSB) 5 D6-0 (I) 6-bit data input pin 1 for SIGOUT output line clamp voltage adjustment (LSB) 6 D6-1 (I) 6-bit data input pin 2 for SIGOUT output line clamp voltage adjustment 7 D6-2 (I) VCCD VCCD 1k Lo: 0 to 0.8V Hi: 3.5 to 5V 1.8V 5 129 6-bit data input pin 3 for SIGOUT output line clamp voltage adjustment 6-bit data input pin 4 for SIGOUT output line clamp voltage adjustment 8 D6-3 (I) 9 D6-4 (I) 6-bit data input pin 5 for SIGOUT output line clamp voltage adjustment 10 D6-5 (I) 6-bit data input pin 6 for SIGOUT output line clamp voltage adjustment (MSB) 100µ –3– CXA2027Q Pin Symbol (I/O) No. 11 LD0 (I) 12 LD1 (I) Typical pin voltage Equivalent circuit DC 5-bit data input pin 1 for pre-stage GCA gain adjustment (LSB) VCCD 13 LD2 (I) Description AC 5-bit data input pin 2 for pre-stage GCA gain adjustment VCCD 20k Lo: 0 to 0.8V Hi: 3.5 to 5V 5-bit data input pin 3 for pre-stage GCA gain adjustment 11 129 1.5k 14 LD3 (I) 5-bit data input pin 4 for pre-stage GCA gain adjustment 15 LD4 (I) 5-bit data input pin 5 for pre-stage GCA gain adjustment (MSB) VCCA VCCA 1.5k 16 CLPC Approx. 3.1V Additional capacitance pin for line clamp. Add 0.47µF between this pin and GND. 16 129 VCCA 6.7µ VCCA 2.0V 6k 3k 17 17 2k VRB (O) 2.0V VCCA VCCA 100µ 1k VCCA Output pin for AD converter reference voltage VRB 100µ 100µ 75µ VCCA VCCA 187.5 2k 18 VRT (O) 4.0V 750 18 Output pin for AD converter reference voltage VRT 4k 100µ 19 GND 0V GND pin –4– CXA2027Q Pin Symbol (I/O) No. Typical pin voltage Equivalent circuit DC Description AC VCCA 20 2.0V +MAX1.8V (2.0 to 3.8V) SIGOUT (O) VCCA 21 100µ Signal output pin (to AD converter) 1k 20 2mA VCCP Power supply pin (for signal output system) 5V VCCA VCCA VCCA 100µ 20k 22 GC (I) 4k 129 0 to 5V 22 30k Lo: 0 to 0.8V Hi: 3.5 to 5V VCCA 1.5k VCCA 100µ 23 LCLP (I) Lo: clamp OFF Hi: clamp ON 24 TD4 (O) 1.7 to 3.6V 25 TD6 (O) 2.0 to 3.6V 26 TD5 (O) 27 1.5V 23 129 2k VCCA TD2 (O) 29 TD3 (O) DA4 analog output test pin VCCA DA5 analog output test pin 24 DA1 analog output test pin 129 1.7 to 3.6V 126µ DA2 analog output test pin DA3 analog output test pin Lo: 0 to 0.8V Hi: 3.5 to 5V VCCA VCCA 250µ 30 CLP (I) Line clamp pulse input pin (Apply high level during the optical black period of CCD output) DA6 analog output test pin TD1 (O) 28 Voltage input pin for poststage GCA gain adjustment (Can be open; in that case outputs 3V) (Use with open) 21 129 Lo: clamp OFF Hi: clamp ON 1.5V 30 1k VCCA Pixel clamp pulse input pin (Apply high level during the precharge period of CCD output) VCCA 1.5k 31 MPX1 (I) Lo: 0 to 0.8V Hi: 3.5 to 5V 1.2V 31 129 100µ –5– MPX channel switching pulse input pin 1 (See high/low table under Pin 32 in following section.) CXA2027Q Pin Symbol (I/O) No. Typical pin voltage Equivalent circuit DC Description AC VCCA MPX channel switching pulse input pin 2. VCCA 130µ 32 MPX2 (I) 5k Lo: 0 to 0.8V Hi: 3.5 to 5V 2.4V 32 129 1.5k Pin 31 MPX1 L L H H Pin 32 MPX2 L H L H Pin 20 SIGOUT R channel G channel B channel B channel VCCA Lo: 0 to 0.8V Hi: 3.5 to 5V 1.5V 33 129 33 SH (I) 1m Lo: sample mode Hi: hold mode 1.5V 1.5V 1m 1m VCCA 34 BUF (O) 35 36 37 34 R-IN (I) G-IN (I) VCCA 260µ 2.4V +MAX1.8V (2.4 to 4.2V) Output test pin after MPX (use with open) 2k VCCA CCD effective signal level MAX1.5Vp-p (Note 1) Sample-and-hold pulse input pin. (Apply low level during the effective signal period (refer to Note 1) of CCD output) CCD signal R channel input pin VCCA 100µ 3.7V 35 129 CCD signal G channel input pin 1µ CCD signal B channel input pin B-IN (I) –6– CXA2027Q Pin Symbol (I/O) No. 38 Typical pin voltage Equivalent circuit DC Voltage input pin for setting R channel pre-stage GCA gain adjustment latch circuit to data input mode (high) or hold mode (low). LPR (I) VCCD 39 Description AC Lo: 0 to 0.8V data hold LPG (I) Hi: 3.5 to 5V data input VCCD Voltage input pin for setting G channel pre-stage GCA gain adjustment latch circuit to data input mode (high) or hold mode (low). 1.5k 38 129 28k Voltage input pin for setting B channel pre-stage GCA gain adjustment latch circuit to data input mode (high) or hold mode (low). 40 LPB (I) 42 VCCA 5V Power supply pin (for analog, general system) 47 VCCD 5V Power supply pin (for DA converter system) Note 1: Effective signal levels are defined as follows for CCD output signals. Reset level CCD output signal Precharge level Effective signal level Fig. 1 –7– CXA2027Q Description of Data Input Pin Polarity Pin name (Pin No.) Function CLP(30) Pixel clamp SH(33) Sample-and-hold MPX1/MPX2 (31/32) Channel switching for R,G,B Input level Characteristics High Clamp ON Low Clamp OFF High Hold mode Low Sample mode MPX1 MPX2 Low Low R-ch Low High G-ch High Low B-ch High High B-ch Output LPR/LPG/LPB (38/39/40) Channel switching for pre-stage GCA gain data input LD0 to LD4 (11/12/13/14/15) Pre-stage GCA gain data 11111 Maximum gain 00000 Minimum gain D4-0 to D4-4 (41/43/44/45/46) B-IN clamp voltage adjustment 11111 Maximum clamp voltage 00000 Minimum clamp voltage D5-0 to D5-4 (48/1/2/3/4) G-IN clamp voltage adjustment 11111 Maximum clamp voltage 00000 Minimum clamp voltage D6-0 to D6-5 (5/6/7/8/9/10) Output DC voltage adjustment 111111 Maximum DC output voltage 000000 Minimum DC output voltage LCLP(23) Line clamp High Data input Low Data hold High Clamp ON Low Clamp OFF –8– Others LPR: for R-ch LPG: for G-ch LPB: for B-ch LD0: LSB LD4: MSB D4-0: LSB D4-4: MSB D5-0: LSB D5-4: MSB D6-0: LSB D6-5: MSB CXA2027Q Electrical Characteristics (See Electrical Characteristics Measurement Circuit.) No. Item 1 Current consumption (1) Min. Typ. Max. Unit Icc1 Pre and Post-stage GCA gain = maximum SW11 to 15 = b, SW16 = a, SW22-1 = b, SW22-2 = b, SW23 = a, SW31 to 32 = a, SW35-1 = a 44 60 78 mA 2 Current consumption (2) Icc2 Pre and Post-stage GCA gain = minimum SW11 to 15 = a, SW16 = a, SW22-1 = b, SW22-2 = a, SW23 = a, SW31 to 32 = a, SW35-1 = a 54 73 94 mA 3 Digital input voltage High Vih 3.5 5 V 4 Digital input voltage Low Vil 0 0.8 V 5 VRB DC voltage Vrb VRB-VRT equivalent impedance 300Ω 1.96 2.00 2.04 V 6 VRT DC voltage Vrt VRB-VRT equivalent impedance 300Ω 3.94 3.99 4.06 V 7 VRT-VRB voltage Vtb VRB-VRT equivalent impedance 300Ω 1.95 1.98 2.05 V Pre-stage GCA gain min. Gfn Minimum pre-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = a, SW16 = a, SW22-1 = a, SW23 = a, SW35-1 = b, SW35-2 = a, SW31, 32 = (a, a) or (a, b) or (b, b) –1.67 –0.25 +1.11 dB Gfx Maximum pre-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = b, SW16 = a, SW22-1 = a, SW23 = a, SW35-1 = b, SW35-2 = a, SW31, 32 = (a, a) or (a, b) or (b, b) 11.77 13.92 16.03 dB Grn Minimum post-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = a, SW16 = a, SW22-1 = b, SW22-2 = a, SW23 = a, SW35-1 = b, SW35-2 = a, SW31 to 32 = a –8.33 –6.92 –5.61 dB Grx Maximum post-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = a, SW16 = a, SW22-1 = b, SW22-2 = b, SW23 = a, SW35-1 = b, SW35-2 = a, SW31 to 32 = a 3.55 7.12 dB Lin1 Difference between output value 1/2 level for input level Vx and output level for input level 1/2 Vx. Vx = 1.5V (SG35-2). See Note 2. SW11 to 15 = a, SW16 = b, SW22-1 = a, SW23 = b, SW31, 32 = (a, a) or (a, b) or (b, b), SW35-1 = b, SW35-2 = b –5 +5 % Lin2 Difference between output value 1/2 level for input level Vx and output level for input level 1/2 Vx. Vx = 0.3V (SG35-2). See Note 2. SW11 to 15 = a, SW16 = b, SW22-1 = a, SW23 = b, SW31, 32 = (a, a) or (a, b) or (b, b), SW35-1 = b, SW35-2 = b –5 +5 % 8 9 10 11 12 13 Pre-stage GCA gain max. Post-stage GCA gain min. Post-stage GCA gain max. Output signal linearity 1 Output signal linearity 2 Symbol Measurement conditions (VCC = 5V, Ta = 25°C) –9– 5.24 CXA2027Q Electrical Characteristics Measurement Circuit SW polarity a f = 1MHz b 11.5µs 36 35 34 SW31 SW35-1 Vx 63.6µs 7µs SW32 3.32V SW35-2 3.32V 63.6µs SG35-1 SG35-2 3.12VDC + 0.4Vp-p 33 32 31 5V 0V 30 29 28 26 27 25 37 SG23 24 38 23 SW23 GCA S/H 39 SW22-2 GCA 22 SW22-1 40 21 47µ 41 S/H 20 Driver DC shift GCA 0.01µ V20 5V 19 42 43 S/H V18 300 GCA D/A 44 1µ 18 VREF 0.01µ 17 45 46 LOG LOG LOG D/A D/A D/A LATCH LATCH LATCH 1µ 15 14 D/A 4 5 6 7 8 9 10 11 SW12 3 SW16 SW15 SW14 SW13 SW11 2 0.47µ 13 D/A 0.01µ 1 3.1V 16 47 48 V17 12 Note 2: No. 12, 13 Input SG35-2 Vx 4µs Line clamp pulse SG23 V20 (Vx) Output V20 Defined as: 1 V20 ( 2 Vx) V20 (Vx) × 1 2 –1 × 100 [%]. – 10 – No. 12 Vx = 1.5V No. 13 Vx = 0.3V CXA2027Q Pulse Timing [Pulse Timing 1 (pixel units)] CLP pulse and SH pulse Input the SH pulse at the end of the effective signal so as not to be affected by signal fluctuation caused by the clamp. SH pulse and MPX pulse (MPX1, MPX2) Input the SH pulse in sync with the reference channel. MPX1 pulse and MPX2 pulse Delay the timing of MPX2 when G changes to B. (Table 1, t3) Reset level CCD signal (R-IN/ G-IN/ B-IN) t4 Precharge level Effective signal level t1 50% CLP t2 50% SH tr = tf = 5ns 50% MPX1 t3 50% MPX2 SIGOUT t5 Data taken in at AD converter Output channel B R G B Min. Typ. t1 100ns t2 40ns 50ns t3 5ns 20ns t4 5ns t5 60ns Table 1 – 11 – R Max. LCLP CCD signal (R-IN/ G-IN/ B-IN) t6 [Pulse Timing 2 (line units)] – 12 – Table 2 10µs Min. Typ. Max. Dummy signal t6 1-line output period AAAAA A A AA A AA AAAAAA AA AA The LCLP pulse is recommended to be applied during the optical black period. Optical black CXA2027Q CXA2027Q [Pulse Timing 3 (latch data input)] Latch gate (LPR/LPG/LPB) t8 Input data (LD0 to LD4) t7 t9 t10 (input data decision time) Min. Typ. t7 50ns t8 50ns t9 50ns t10 800ns Table 3 – 13 – Max. CXA2027Q Notes on Operation 1. Pre-stage GCA The gain characteristics is as given in page 16. As a guideline, the calculation formula is 0.5 × 1.05n [times] (n = 0 to 31: n is D/A converter input in decimal). 2. Post-stage GCA The gain characteristics is as given in page 16. When the GC pin is open, gain becomes approximately double. 3. Line clamp When the LCLP pulse (line clamp pulse) is made high during the optical black period of CCD output, output (Pin 20) is clamped approximately to VRB (= 2.0V) voltage. 4. Pixel clamp The pixel clamp function (at Pins 35, 36 and 37) requires large charging and discharging current through the capacitor, therefore, keep the ground area below the emitter follower as wide as possible. The distance between the input capacitor and input pin should also be as short as possible. 5. DC offset adjustment between channels There is a slight difference between clamp voltages (black level voltage) of different channels due to component scatterings within the IC. Correct the B and G channel DC levels relative to R channel using D4-0 to D4-4 and D5-0 to D5-4. The adjustment step for the input pins (Pins 36 and 37) is approximately 5mV/LSB. The standard settings are D4-0 to D4-3 = “L”, D4-4 = “H”, and D5-0 to D5-3 = “L”, D5-4 = “H”. 6. Output DC voltage adjustment Output (Pin 20) clamp voltage varies slightly due to variations within the IC. Adjust output clamp voltage using D6-0 to D6-5. The adjustment step is approximately 1mV/LSB. The standard settings are D6-0, D6-1 = “H”, D6-2 to D6-5 = “L”. 7. Pulse input signals Sharp edges at input pulse signals may affect output. If there is a problem, insert a damping resistor (around 100 to 200Ω) to smooth the pulse’s edges. – 14 – VOUT-B VOUT-G VOUT-R 2.2kΩ 100Ω 2.2kΩ 100Ω 2.2kΩ 100Ω 37 B-IN 1000pF 12V 36 1000pF G-IN 12V 35 1000pF R-IN 12V SH 38 (N.C.) 24 26 (N.C.) TD4 GCA3 11 12 13 14 15 40 LOG × 0.5 to 2.27 GCA2 LATCH3 DA3 (5bit) × 0.5 to 2.27 DA4 (5bit) × 0.5 to 2.27 LATCH2 D4-3 41 43 44 45 46 GCA1 4 DA2 (5bit) LOG MPX2 MPX1 27 28 29 GCA × 1 to 3 SW (cont) 31 32 34 8 7 DA6 (6bit) 6 Driver 25 9 10 VRT 0.47µF CLPC 1µF SIGOUT 0.1µF 47µF 5V VRB 1µF 17 18 16 20 GND 19 VCCP 21 VCCD 47 VCCA 42 REF VOLTAGE DC shift 23 Digital data input 5 22 Pulse input VRB VRT VIN A/D Converter Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Digital data pulse input LATCH1 2 3 DA5 (5bit) 48 1 D5-1 LOG 39 SH3 SH2 SH1 DA1 (5bit) 30 33 D5-0 LD0 CCD Linear Image Sensor D5-3 LD2 CLP LPR D5-2 LD1 D4-1 LPB TD5 LPG D4-0 LD4 D4-4 (N.C.) D5-4 LD3 D4-2 Digital data input (N.C.) Pulse input D6-1 TD1 TD2 TD3 (N.C.) GC D6-2 BUF (N.C.) D6-0 LCLP D6-3 TD6 D6-5 D6-4 – 15 – (N.C.) Application Circuit CXA2027Q CXA2027Q Example of Representative Characteristics (VCC = 5V, Ta = 25°C) Pre-stage GCA gain characteristics data (unit) Post-stage GCA gain characteristics data (unit) 9 12 8 11 f = 1MHz f = 1MHz 7 10 6 9 5 8 4 7 2 Gain [dB] Gain [dB] 3 1 0 –1 6 5 4 3 –2 2 –3 1 –4 0 –5 –1 –6 –7 –2 0 5 10 15 20 25 30 LD0 to LD4 input data (expressed as decimal system) 0 2 3 GC pin input voltage [V] G, B channels clamp voltage adjustment range SIGOUT clamp voltage adjustment range 80 4 5 2060 60 2050 40 2040 SIGOUT voltage [mV] Difference from R channel clamp voltage [mV] 1 20 0 –20 2030 2020 2010 –40 2000 –60 VRB –80 0 5 10 15 20 25 1990 30 D4-0 to D4-4 or D5-0 to D5-4 input data (expressed as decimal system) – 16 – 0 10 20 30 40 50 60 D6-0 to D6-5 input data (expressed as decimal system) CXA2027Q Example of Temperature and Supply Voltage Fluctuation Characteristics Total gain temperature characteristics fluctuation Total gain supply voltage fluctuation 0.15 0.3 DA1, 2, 3 = all 0/GC = VCC DA1, 2, 3 = all 0/GC = open DA1, 2, 3 = all 0/GC = GND DA1, 2, 3 = all 1/GC = VCC DA1, 2, 3 = all 1/GC = open DA1, 2, 3 = all 1/GC = GND 5V 5.25V 4.75V 0.25 LD0 to LD4 = 0, GC = open 0.1 Ta = 25°C f = 1MHz Gain fluctuation [dB] Gain fluctuation [dB] 0.2 0.15 0.1 0.05 0.05 0 0 –0.05 0 10 20 30 50 40 60 –0.05 4.75 70 5 5.25 Temperature [°C] Vcc [V] VRT, VRB temperature characteristics voltage fluctuation Clamp voltage temperature characteristics fluctuation 2.5 2 VRT VRB VRT – VRB 2 VCC = 5V SIGOUT SIGOUT – VRB VCC = 5V 1.5 SIGOUT fluctuation voltage [mV] Fluctuation voltage [mV] 1.5 1 0.5 0 1 0.5 0 –0.5 –0.5 –1 –1 –1.5 0 10 20 30 40 50 60 –1.5 70 0 10 20 30 40 Temperature [°C] Temperature [°C] – 17 – 50 60 70 CXA2027Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 36 25 0.15 24 48 13 13.5 37 12 0.8 + 0.15 0.3 – 0.1 ± 0.12 M 0.9 ± 0.2 1 + 0.2 0.1 – 0.1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-48P-L04 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE ∗QFP048-P-1212-B LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.7g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 18 –