PHILIPS TDA8708

INTEGRATED CIRCUITS
DATA SHEET
TDA8708B
Video analog input interface
Product specification
Supersedes data of June 1994
File under Integrated Circuits, IC02
1996 Nov 26
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
FEATURES
APPLICATIONS
• 8-bit resolution
• Video signal decoding
• Sampling rate up to 32 MHz
• Scrambled TV (encoding and decoding)
• Binary or two’s complement 3-state TTL outputs
• Digital picture processing
• TTL-compatible digital inputs and outputs
• Frame grabbing.
• Internal reference voltage regulator
• Power dissipation of 365 mW (typical)
GENERAL DESCRIPTION
• Input selector circuit (one out of three video inputs)
The TDA8708B is an analog input interface for video signal
processing. It includes a video amplifier with clamp and
gain control, an 8-bit Analog-to-Digital Converter (ADC)
with a sampling rate of 32 MHz and an input selector.
• Clamp and Automatic Gain Control (AGC) functions for
CVBS and Y signals
• No sample-and-hold circuit required
• The TDA8708B has no white peak control in mode 2
whereas the TDA8708A has control in modes 1 and 2
• In-range output (not TTL levels).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.5
5.0
5.5
V
VCCD
digital supply voltage
4.5
5.0
5.5
V
VCCO
TTL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
−
37
45
mA
ICCD
digital supply current
−
24
30
mA
ICCO
TTL output supply current
−
12
16
mA
ILE
DC integral linearity error
−
−
±1
LSB
DLE
DC differential linearity error
−
−
±0.5
LSB
fclk(max)
maximum clock frequency
30
32
−
MHz
B
maximum −3 dB bandwidth (AGC amplifier)
12
18
−
MHz
Ptot
total power dissipation
−
365
500
mW
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA8708BT
1996 Nov 26
SO28
DESCRIPTION
plastic small outline package; 28 leads; body width 7.5 mm
2
VERSION
SOT136-1
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
BLOCK DIAGRAM
handbook, full pagewidth
video input
selection bit 0
video input
selection bit 1
14
video input 0
video input 1
video input 2
15
analog
voltage
output
VIDEO
AMPLIFIER
19
ADC
input
clock
input
20
5
decoupling
input
TTL outputs V CCO (+ 5 V)
21
7
16
17
18
9
INPUT
SELECTOR
8 - bit
ADC
AMP.
1
2
clamp capacitor
connection
24
3
AGC capacitor
connection
25
TTL
4
OUTPUTS 10
TDA8708B
11
12
AGC &
CLAMP
LOGIC
&
MODE
SELECTION
in-range
output
D6
D5
D4
D3
D2
D1
D0
BLACK LEVEL
DIGITAL COMPARATOR
28
SYNC LEVEL
DIGITAL COMPARATOR
27
sync level
sync pulse
26
black level
sync pulse
6
8
digital V CCD
(+ 5 V)
digital
ground
Fig.1 Block diagram.
1996 Nov 26
13
PEAK LEVEL
DIGITAL COMPARATOR
output format/
chip enable
(3-state input)
D7
3
22
analog V CCA
(+ 5 V)
23
analog
ground
MSA672
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
PINNING
SYMBOL
PIN
DESCRIPTION
D7
1
data output; bit 7 (MSB)
D6
2
data output; bit 6
D5
3
data output; bit 5
D4
4
data output; bit 4
CLK
5
clock input
VCCD
6
digital supply voltage (+5 V)
VCCO
7
TTL outputs supply voltage (+5 V)
DGND
8
digital ground
OF
9
output format/chip enable
(3-state input)
D7
1
28 IR
D6
2
27 GATE A
D5
3
26 GATE B
D4
4
25 AGC
CLK
5
24 CLAMP
VCCD
6
23 AGND
VCCO
7
DGND
8
21 DEC
9
20 ADCIN
D3
10
data output; bit 3
D2
11
data output; bit 2
D1
12
data output; bit 1
D0
13
data output; bit 0 (LSB)
I0
14
video input selection bit 0
OF
I1
15
video input selection bit 1
D3 10
19 ANOUT
VIN0
16
video input 0
D2 11
18 VIN2
VIN1
17
video input 1
D1 12
17 VIN1
VIN2
18
video input 2
D0 13
16 VIN0
ANOUT
19
analog voltage output
ADCIN
20
analog-to-digital converter input
DEC
21
decoupling input
VCCA
22
analog supply voltage (+5 V)
AGND
23
analog ground
CLAMP
24
clamp capacitor connection
AGC
25
AGC capacitor connection
GATE B
26
black level synchronization pulse
GATE A
27
sync level synchronization pulse
IR
28
in-range output
1996 Nov 26
I0
TDA8708B
14
22 VCCA
15
I1
MSA671
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
The voltage across the capacitor connected to the AGC
pin controls the gain of the video amplifier. This is the gain
control loop.
FUNCTIONAL DESCRIPTION
The TDA8708B provides a simple interface for decoding
video signals.
The sync level comparator is active during a positive-going
pulse at the GATE A input. This means that the sync pulse
of the composite video signal is used as an amplitude
reference. The bottom of the sync pulse is adjusted to
obtain a digital output of logic 0 at the converter output.
As the black level is at digital level 64, the sync pulse will
have a digital amplitude of 64 LSBs.
The TDA8708B operates in configuration mode 1
(see Fig.4) when the video signals are weak (i.e. when the
gain of the AGC amplifier has not yet reached its optimum
value). This enables a fast recovery of the synchronization
pulses in the decoder circuit. When the pulses at the
GATE A and GATE B inputs become distinct (GATE A and
GATE B pulses are synchronization pulses occurring
during the sync period and rear porch respectively) the
TDA8708B automatically switches to configuration mode 2
(see Fig.5).
The use of nominal signals will prevent the output from
exceeding a digital code of 213.
The clamp level control is accomplished by using the same
techniques as used for the gain control. The black-level
digital comparator is active during a positive-going pulse at
the GATE B input. The clamp capacitor will be charged or
discharged to adjust the digital output to code 64.
When the TDA8708B is in configuration mode 1, the gain
of the AGC amplifier will be roughly adjusted (sync level to
a digital output level of 0 and the peak level to a digital
output level of 255).
In configuration mode 2 the digital output of the ADC is
compared to internal digital reference levels.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCCA
analog supply voltage
−0.3
+7.0
V
VCCD
digital supply voltage
−0.3
+7.0
V
VCCO
TTL output supply voltage
−0.3
+7.0
V
∆VCC
supply voltage differences:
VCCA − VCCD
−1.0
+1.0
V
VCCO − VCCD
−1.0
+1.0
V
VCCA − VCCO
−1.0
+1.0
V
−0.3
VCCA
V
VI
input voltage
IO
output current
0
+10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
0
+70
°C
Tj
junction temperature
0
+125
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1996 Nov 26
PARAMETER
thermal resistance from junction to ambient in free air
5
VALUE
UNIT
70
K/W
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
CHARACTERISTICS
VCCA = V22 to V23 = 4.5 to 5.5 V; VCCD = V6 to V8 = 4.5 to 5.5 V; VCCO = V7 to V8 = 4.2 to 5.5 V; AGND and DGND
shorted together; VCCA to VCCD = −0.5 to +0.5 V; VCCO to VCCD = −0.5 to +0.5 V; VCCA to VCCO = −0.5 to +0.5 V;
Tamb = 0 to +70 °C; typical readings taken at VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
4.5
5.0
5.5
V
VCCD
digital supply voltage
4.5
5.0
5.5
V
VCCO
TTL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
−
37
45
mA
ICCD
digital supply current
ICCO
TTL output supply current
−
24
30
mA
TTL load (see Fig.8)
−
12
16
mA
Video amplifier inputs
VIN0 TO VIN2 INPUTS
VI(p-p)
input voltage (peak-to-peak value)
AGC load with external
capacitor; note 1
0.6
−
1.5
V
Zi
input impedance
fi = 6 MHz
10
20
−
kΩ
Ci
input capacitance
fi = 6 MHz
−
1
−
pF
I0 AND I1 TTL INPUTS (see Table 1)
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
2.0
−
VCCD
V
IIL
LOW level input current
VI = 0.4 V
−400
−
−
µA
IIH
HIGH level input current
VI = 2.7 V
−
−
20
µA
0
−
0.8
V
GATE A AND GATE B TTL INPUTS (see Figs 4 and 5)
VIL
LOW level input voltage
VIH
HIGH level input voltage
2.0
−
VCCD
V
IIL
LOW level input current
VI = 0.4 V
−400
−
−
µA
IIH
HIGH level input current
VI = 2.7 V
−
−
20
µA
tW
pulse width
see Fig.5
2
−
−
µs
AGC voltage for minimum gain
−
2.8
−
V
AGC voltage for maximum gain
−
4.0
−
V
−
V
AGC INPUT (PIN 25)
V25(min)
V25(max)
AGC output current
see Table 2
CLAMP INPUT (PIN 24)
V24
clamp voltage for code 128 output
I24
clamp output current
1996 Nov 26
−
3.5
see Table 3
6
Philips Semiconductors
Product specification
Video analog input interface
SYMBOL
PARAMETER
TDA8708B
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Video amplifier outputs
ANOUT OUTPUT (PIN 19)
V19(p-p)
AC output voltage
(peak-to-peak value)
VVIN = 1.33 V (p-p);
V25 = 3.6 V
−
1.33
−
V
I19
internal current source
RL = ∞
2.0
2.5
−
mA
IO(p-p)
output current driven by the load
VANOUT = 1.33 V (p-p);
note 2
−
−
1.0
mA
V19
DC output voltage for black level
note 3
−
VCCA − 2.24 −
V
Z19
output impedance
−
20
−
Ω
Video amplifier dynamic characteristics
αct
crosstalk between VIN inputs
VCCA = 4.75 to 5.25 V
−
−50
−45
dB
Gdiff
differential gain
VVIN = 1.33 V (p-p);
V25 = 3.6 V
−
2
−
%
ϕdiff
differential phase
VVIN = 1.33 V (p-p);
V25 = 3.6 V
−
0.8
−
deg
B
−3 dB bandwidth
12
−
−
MHz
S/N
signal-to-noise ratio
note 4
60
−
−
dB
SVRR1
supply voltage ripple rejection
note 5
−
45
−
dB
∆G
gain range
see Fig.10
−4.5
−
+6.0
dB
Gstab
gain stability as a function of supply
voltage and temperature
see Fig.10
−
−
5
%
Analog-to-digital converter inputs
CLK INPUT (PIN 5)
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
2.0
−
VCCD
V
IIL
LOW level input current
Vclk = 0.4 V
−400
−
−
µA
IIH
HIGH level input current
Vclk = 2.7 V
−
−
100
µA
|Zi|
input impedance
fclk = 10 MHz
−
4
−
kΩ
CI
input capacitance
fclk = 10 MHz
−
4.5
−
pF
OF INPUT (3-STATE; see Table 4)
VIL
LOW level input voltage
0
−
0.2
V
VIH
HIGH level input voltage
2.6
−
VCCD
V
V9
input voltage in high impedance state
−
1.15
−
V
IIL
LOW level input current
−370
−300
−
µA
IIH
HIGH level input current
−
300
450
µA
1996 Nov 26
7
Philips Semiconductors
Product specification
Video analog input interface
SYMBOL
TDA8708B
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ADCIN INPUT (PIN 20; see Table 5)
V20
input voltage
digital output = 00
−
VCCA − 2.42 −
V
V20
input voltage
digital output = 255
−
VCCA − 1.41 −
V
V20(p-p)
input voltage amplitude
(peak-to-peak value)
−
1.0
−
V
I20
input current
−
1.0
10
µA
Zi
input impedance
fi = 6 MHz
−
50
−
MΩ
Ci
input capacitance
fi = 6 MHz
−
1
−
pF
Analog-to-digital converter outputs
IR OUTPUT (PIN 28)
VOL
LOW level output voltage
−
−
1.7
V
VOH
HIGH level output voltage
1.9
−
−
V
IO
output current
−500
−
−
µA
DIGITAL OUTPUTS D0 TO D7
VOL
LOW level output voltage
IOL = 2 mA
0
−
0.6
V
VOH
HIGH level output voltage
IOL = −0.4 mA
2.4
−
VCCD
V
IOZ
output current in 3-state mode
0.4 V < VO < VCCD
−20
−
+20
µA
see Fig.6; note 6
30
32
−
MHz
Switching characteristics
fclk(max)
maximum clock input frequency
Analog signal processing (fclk = 32 MHz); see Fig.8
Gdiff
differential gain
V20 = 1.0 V (p-p);
see Fig.7; note 7
−
2
−
%
ϕdiff
differential phase
see Fig.7; note 7
−
2
−
deg
f1
fundamental harmonics (full-scale)
fi = 4.43 MHz; note 7
−
−
0
dB
fall
harmonics (full-scale);
all components
fi = 4.43 MHz; note 7
−
−55
−
dB
SVRR2
supply voltage ripple rejection
note 8
−
1
5
%/V
Transfer function (see Fig.8)
ILE
DC integral linearity error
−
−
±1
LSB
DLE
DC differential linearity error
−
−
±0.5
LSB
ILE
AC integral linearity error
−
−
±2
LSB
−
2
−
ns
note 9
Timing (fclk = 32 MHz) see Figs 6, 7 and 8
DIGITAL OUTPUTS (CL = 15 pF; IOL = 2 mA; RL = 2 kΩ)
tds
sampling delay time
th
output hold time
6
8
−
ns
td
output delay time
−
16
20
ns
tdEZ
3-state delay time; output enable
−
19
25
ns
tdDZ
3-state delay time; output disable
−
14
20
ns
1996 Nov 26
8
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
Notes
1. 0 dB is obtained at the AGC amplifier when applying Vi(p-p) = 1.33 V.
2. The output current at pin 19 should not exceed 1 mA. The load impedance RL should be referenced to VCCA and
defined as:
a) AC impedance ≥1 kΩ and the DC impedance >2.7 kΩ.
b) The load impedance should be coupled directly to the output of the amplifier so that the DC voltage supplied by
the clamp is not disturbed.
3. Control mode 2 is selected.
V ANOUTC ( p – p )
S
4. Signal-to-noise ratio measured with 5 MHz bandwidth: ---- = 20 log ------------------------------------------------- at B = 5 MHz .
V ANOUTY (RMS noise)
N
5. The voltage ratio is expressed as:
∆V CCA G
SVRR1 = 20 log ------------------ × -------- for VI = 1 V (p-p), gain at 100 kHz = 1 and 1 V supply variation.
V CCA ∆G
6. It is recommended that the rise and fall times of the clock are ≥2 ns. In addition, a ‘good layout’ for the digital and
analog grounds is recommended.
7. These measurements are realized on analog signals after a digital-to-analog conversion (TDA8702 is used).
8. The supply voltage rejection is the relative variation of the analog signal (full-scale signal at input) for 1 V of supply
variation:
∆ ( V I ( 00 ) – V I ( FF ) ) + ( V I ( 00 ) – V I ( FF ) )
SVRR2 = ----------------------------------------------------------------------------------------------------∆V CCA
9. Full-scale sine wave (fi = 4.4 MHz; fclk = 27 MHz).
1996 Nov 26
9
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
Table 1 Video input selection (CVBS)
Table 3 CLAMP output current
I1
I0
SELECTED INPUT
0
0
VIN0
0
1
VIN1
1
0
VIN2
1
1
1
VIN2
1
DIGITAL
OUTPUT
1
1
0
X(2)
1
0
MODE
output < 0
130 µA
1
output > 0
−2.5 µA
1
0
X
0 µA
2
0
1
output < 64
+50 µA
2
64 < output
−50 µA
2
Note
MODE(1)
IAGC
ICLAMP
X(1)
Table 2 AGC output current
GATE A GATE B
DIGITAL
OUTPUT
GATE A GATE B
1. X = don't care.
output < 255 −2.5 µA
1
output > 255 130 µA
1
−
0 µA
2
+2.5 µA
OF
output < 0
2
−2.5 µA
0
active, two’s complement
output > 0
2
1
high impedance
circuit(1)
active, binary
Table 4 OF input coding
open
Notes
1. Mode 2 can only be initialized with successive pulses
on GATE A and GATE B (see Fig.5).
D0 TO D7
Note
1. Use C ≥ 10 pF to DGND.
2. X = don’t care.
Table 5 Output coding and input voltage (typical values)
BINARY OUTPUTS
STEP
VADCIN
TWO’S COMPLEMENT
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Underflow
−
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
VCCA − 2.41 V
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
−
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
.
−
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
−
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
254
−
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
255
VCCA − 1.41 V
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Overflow
−
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1996 Nov 26
10
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
handbook, full pagewidth
0.25 V
5 MHz sine wave
1.0 V
0.25 V
64 µs
MBB959
Fig.3 Test signal on the ADCIN pin for differential gain and phase measurements.
k, full pagewidthdigital
MBB969
output
level
peak-level gain control
255
black-level
clamping
sync-level gain control
0
time
GATE A
GATE B
MODE 1
Fig.4 Control mode 1.
1996 Nov 26
11
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
handbook, full pagewidth
digital
MSA674
output
level
255
black-level
clamping
64
sync-level control
0
tW
GATE A
time
tW
GATE B
MODE 2
Fig.5 Control mode 2.
handbook, full pagewidth
clock input
reference level
(1.5 V)
CLK
input
t ds
sample
N 1
sample
N 2
sample
N
sample
N 1
analog
input
(ADCIN)
th
2.4 V
data
outputs data N 3
D0 to D7)
data N 2
data N 1
data N
data N 1
0.4 V
td
Fig.6 Timing diagram for data output.
1996 Nov 26
12
MBB958
Philips Semiconductors
Product specification
Video analog input interface
handbook, full pagewidth
TDA8708B
open
OF
input
data
outputs
(D0 to D7)
2.4 V
high impedance
binary
two's complement
0.4 V
t dDZ
t dEZ
MBB968
Fig.7 Output format timing diagram.
V CCO
handbook, halfpage
2 kΩ
D0 to D7
15 pF
IN916
or
IN3064
MBD865
DGND
Fig.8 Load circuit for timing measurement; data outputs (OF = LOW or open-circuit).
1996 Nov 26
13
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
V CCO
handbook, halfpage
2 kΩ
S1
D0 to D7
C
5
kΩ
IN916
or
IN3064
S2
MBB955
DGND
Fig.9 Load circuit for timing measurement; 3-state outputs (OF: fi = 1 MHz; VOF = 3 V).
MSA676
12
G
(dB)
8
5%
4
0
(1)
(2)
4
8
2.6
3
3.4
3.8
4.2
4.6
V 25 (V)
(1) Typical value (VCCA = VCCD = 5 V; Tamb = 25 °C).
(2) Minimum and maximum values (temperature and supply).
Fig.10 Gain control curve.
1996 Nov 26
14
VCCD
VCCD
VCCA
pins 1 to 4
and 10 to 13
data outputs
pin 6
VCCD
DGND
pin 7
VCCO
DGND
AGND
VCCD
DGND
DGND
pin 5
clock input
pin 22
VCCA
pin 24
CLAMP
VCCA
1.5 V
DGND
TDA8708B
15
4 V BE
chip enable
pin 9
OF
I1
I1
VCCD
pin 8
DGND
I2
pin 23
AGND
AGND
binary/
two's complement
VCCA
VCCA
VREF
Philips Semiconductors
VCCD
Video analog input interface
VCCO
pin 25
AGC
pins 26 or 27
GATE A or GATE B
INTERNAL PIN CIRCUITRY
1996 Nov 26
pin 28
IR
VCCA
VCCA
V top
DGND
VCCA
Vmid
20
kΩ
pins 14 or 15
I 0 ,I 1
AGND
AGND
Vbottom
AGND
Fig.11 Internal pin configuration.
pin 20
ADCIN
AGND
pin 21
DEC
MSA675
Product specification
pin 19
ANOUT
AGND
VREF
TDA8708B
pins 16 to 18
VIN0, VIN1 and VIN2
handbook, full pagewidth
2.5
mA
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
APPLICATION INFORMATION
Additional information can be found in the laboratory report of TDA8708A “FBL/AN9308”.
handbook, full pagewidth
1
28
(2)
2
27
horizontal sync
3
26
horizontal clamp
4
25
5
24
6
23
7
22
data outputs
220 nF
100 Ω
33 pF
clock
18 nF
22 nF
1 µF
(1)
5V
22 Ω
22 nF
10 nF
8
5V
1µH
TDA8708B
5V
21
1 µF
9
20
10 pF
LOW PASS
FILTER
10
19
11
18
12
17
13
16
14
15
(3)
4.7 µF
data outputs
4.7 µF
4.7 µF
75 Ω
75 Ω
75 Ω
MSA673
(1) It is recommended to decouple VCCO through a 22 Ω resistor especially when the output data of TDA8708B interfaces with a capacitive CMOS load
device.
(2) When IR is not used, it must be connected to ground via a 47 pF capacitor.
(3) See Figs 13 and 15 for examples of the low-pass filters.
Fig.12 Application diagram.
1996 Nov 26
16
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
22 µH
22 µH
dbook, full pagewidth
12 pF
680 Ω
ANOUT
(pin 19)
12 pF
ADCIN
(pin 20)
2.2 kΩ
Vi
27 pF
68 pF
27 pF
Vo
MBB966 - 1
VCCA
(pin 22)
This filter can be adapted to various applications with respect to performance requirements. An input and output impedance of at least 680 Ω and 2.2 kΩ
must in any event be applied.
Fig.13 Example of a low-pass filter for CVBS and Y signals.
Characteristics of Fig.14:
• Order 5; adapted CHEBYSHEV
• Ripple ρ ≤ 0.4 dB
MSA682
0
• f = 6.5 MHz at −3 dB
handbook, halfpage
α
(dB)
• fnotch = 9.75 MHz.
40
80
120
160
0
10
20
f (MHz)
30
Fig.14 Frequency response for filter shown in
Fig.13.
1996 Nov 26
17
Philips Semiconductors
Product specification
Video analog input interface
680 Ω
ADOUT
(pin 19)
handbook, full pagewidth
TDA8708B
82 µH
ADCIN
(pin 20)
2.2 kΩ
Vi
15 pF
15 pF
Vo
MSA678
VCCA
(pin 22)
This filter can be adapted to various applications with respect to performance requirements. An input and output impedance of at least 680 Ω and 2.2 kΩ
must in any event be applied.
Fig.15 Example of an economical low-pass filter for CVBS and Y signals.
Characteristics of Fig.16:
• Order 5; adapted CHEBYSHEV
• Ripple ρ ≤ 0.4 dB
MSA681
0
handbook, halfpage
• f = 6.5 MHz at −3 dB.
α
(dB)
10
20
30
40
0
10
20
f (MHz)
30
Fig.16 Frequency response for filter shown in
Fig.15.
1996 Nov 26
18
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
bp
0
detail X
w M
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013AE
1996 Nov 26
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
19
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Nov 26
20
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Nov 26
21
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
NOTES
1996 Nov 26
22
Philips Semiconductors
Product specification
Video analog input interface
TDA8708B
NOTES
1996 Nov 26
23
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© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/04/pp24
Date of release: 1996 Nov 26
Document order number:
9397 750 01456