SM5330A 3-channel Video Filter with Built-in 4-system Switch OVERVIEW The SM5330A is a 4-system input switching 3-channel video filter with 5th-order lowpass filter built-in. The lowpass filter cutoff frequency range is 5MHz to 13MHz (SD mode) or 16MHz to 40MHz (HD mode), controlled using an I2C BUS*1. The lowpass filter enables the device to be utilized in the analog input stage of video signal equipment, functioning as an ADC system anti-aliasing filter for 480i to 1080i signal systems. The signal input type and input system switching, in addition to the cutoff frequency, can be controlled using the I2C BUS. The I2C BUS slave address is set using the ADS pin (3-state input), allowing a maximum of three SM5330A devices to be controlled simultaneously. *1. I2C BUS is a registered trademark of Philips Electronics N.V. FEATURES IN1_3 IN1_2 IN1_1 GND VREF IREF GND VDD SDA SCL ADS I/O_1 36 35 34 33 32 31 30 29 28 27 26 25 17 GND IN2_L1 45 16 VCC IN2_L2 46 15 OUT_3 IN2_L3 47 14 GND IN2_SW 48 13 YOUT PACKAGE DIMENSION (Unit: mm) Weight: 0.18g 0.35MAX ■ ■ HDTVs LCD TVs PDPs Projectors 0.17 ± 0.05 7.00 ± 0.20 9.00 ± 0.20 + 0.20 1.50 − 0.10 ■ 7.00 ± 0.20 APPLICATIONS ■ GND 12 44 DAC_1 11 VCC VCC TEST 10 18 9 43 DAC_0 OUT_2 IN2_3 8 19 GND 42 7 GND IN2_2 IN4_3 20 6 41 IN4_2 OUT_1 IN2_1 5 21 IN4_1 40 4 VCC IN1_SW ORDERING INFORMATION Device Package SM5330AF 48-pin LQFP 0.50 1.00TYP 0.339TYP 0 to 10 ° ■ 22 9.00 ± 0.20 ■ 39 0.10 ± 0.07 ■ VCCD IIN1_L3 GND ■ I/O_0 23 3 ■ 24 38 IN3_3 ■ 37 IN1_L2 2 ■ IN1_L1 1 ■ (Top view) IN3_2 ■ Supply voltages • Analog : 4.75 to 5.25V • Digital : 3.0 to 5.5V 4-system input switch function (3 channels) Lowpass filter function with 64-level cutoff frequency setting for each of SD/HD modes • Cutoff frequency range SD : 5MHz to 13MHz HD: 16MHz to 40MHz Video input pins can be independently set to synctip clamp/bias/direct inputs Output muting function 2 × 8-bit D/A converters built-in for control of arbitrary external circuits I2C BUS interface control • Slave address: 48h, 49h, 4Ah select (up to three devices can be used simultaneously, selected by ADS input) • Data transfer rate: fast mode (400kbit/s) compatible • Control register write function, status register read function Output gain: 6dB Operating ambient temperature range: –20 to 70°C Package: 48-pin LQFP IN3_1 ■ PINOUT 0.10 0.19 ± 0.05 0.08 M 0.50 ± 0.10 SEIKO NPC CORPORATION —1 SM5330A BLOCK DIAGRAM SDA SCL VDD VCCD ADS I C BUS I/F Control Logic 2 I/O_1 I/O_0 VCC VREF IREF DAC_1 DAC_0 DAC DAC DGND Reference IN1_L1 IN1_L2 IN1_L3 IN1_SW Comparator Bias /off Bias /off Clamp /Bias /off IN1_1 IN1_2 IN1_3 IN2_L1 IN2_L2 IN2_L3 IN2_SW 6dB 5th order LPF OUT_1 CH-1 Bias /off Bias /off Clamp /Bias /off 6dB 5th order LPF IN2_1 IN2_2 IN2_3 Bias /off Bias /off Clamp /Bias /off Bias /off Bias /off Clamp /Bias /off OUT_2 CH-2 IN3_1 IN3_2 IN3_3 6dB 5th order LPF IN4_1 IN4_2 IN4_3 OUT_3 0dB YOUT CH-3 TEST GND SEIKO NPC CORPORATION —2 SM5330A PIN DESCRIPTION Number Name I/O*1 A/D*2 1 IN3_1 I A System 3 channel 1 video signal input pin 2 IN3_2 I A System 3 channel 2 video signal input pin 3 IN3_3 I A System 3 channel 3 video signal input pin 4 GND GND A Analog ground pin 5 IN4_1 I A System 4 channel 1 video signal input pin 6 IN4_2 I A System 4 channel 2 video signal input pin 7 IN4_3 I A System 4 channel 3 video signal input pin 8 GND GND A Analog ground pin 9 DAC_0 O A DAC voltage output pin. Output voltage set using the I2C BUS. 10 TEST I D Test pin. Connect to ground for normal operation. 11 DAC_1 O A DAC voltage output pin. Output voltage set using the I2C BUS. 12 GND GND A Analog ground pin 13 YOUT O A Y signal output pin. The channel 3 video signal is output without filtering. 14 GND GND A Analog ground pin 15 OUT_3 O A Channel 3 video signal output pin. The output system is selected using the I2C BUS. 16 VCC P A Analog supply pin 17 GND GND A Analog ground pin 18 VCC P A Analog supply pin 19 OUT_2 O A Channel 2 video signal output pin. The output system is selected using the I2C BUS. 20 GND GND A Analog ground pin 21 OUT_1 O A Channel 1 video signal output pin. The output system is selected using the I2C BUS. 22 VCC P A Analog supply pin 23 VCCD P D Logic supply pin. Connect to the same potential as VCC. 24 I/O_0 I/O D 25 I/O_1 I/O D Logic I/O pins. Outputs are open-drain. Connect pull-up to VCCD. The open-drain outputs are turned ON/OFF using I2C BUS settings. The input state can be read out via the I2C BUS. 26 ADS I D Address select pin. 3-state input Select the I2C BUS slave address. (L: 48h, H: 49h, Z: 4Ah) 27 SCL I D I2C BUS clock signal pin. Connect pull-up to VDD. 28 SDA I/O D I2C BUS data signal pin. Connect pull-up to VDD. The output is open-drain. 29 VDD P D I2C BUS interface-stage supply pin. 3.0V to 5.5V 30 DGND GND D Logic ground pin 31 IREF O A Cutoff frequency control pin. Connect a 1.8kΩ ±1% resistor between this pin and GND. The current that flows in the resistor sets the internal filter reference current. 32 VREF O A Internal reference voltage pin 33 GND GND A Analog ground pin 34 IN1_1 I A System 1 channel 1 video signal input pin 35 IN1_2 I A System 1 channel 2 video signal input pin 36 IN1_3 I A System 1 channel 3 video signal input pin Description SEIKO NPC CORPORATION —3 SM5330A Number Name I/O*1 A/D*2 37 IN1_L1 I D System 1 D-terminal signal discriminator input pin. 3-state input 38 IN1_L2 I D System 1 D-terminal signal discriminator input pin 39 IN1_L3 I D System 1 D-terminal signal discriminator input pin. 3-state input 40 IN1_SW I D System 1 D-terminal signal discriminator input pin 41 IN2_1 I A System 2 channel 1 video signal input pin 42 IN2_2 I A System 2 channel 2 video signal input pin 43 IN2_3 I A System 2 channel 3 video signal input pin 44 VCC P A Analog supply pin 45 IN2_L1 I D System 2 D-terminal signal discriminator input pin. 3-state input 46 IN2_L2 I D System 2 D-terminal signal discriminator input pin 47 IN2_L3 I D System 2 D-terminal signal discriminator input pin. 3-state input 48 IN2_SW I D System 2 D-terminal signal discriminator input pin Description *1. I: input, O: output, P: Power supply, GND: Ground *2. A: analog, D: digital SEIKO NPC CORPORATION —4 SM5330A PIN EQUIVALENT CIRCUITS Number Name 34 35 36 41 42 43 1 2 3 5 6 7 IN1_1 IN1_2 IN1_3 IN2_1 IN2_2 IN2_3 IN3_1 IN3_2 IN3_3 IN4_1 IN4_2 IN4_3 I/O*1 Equivalent circuit VCC I 45Ω INn_n 20kΩ GND VCC 9 11 DAC_0 DAC_1 O 5kΩ 5kΩ DAC_n GND VCCD 10 TEST I 180Ω TEST GND VCC 13 YOUT O 200Ω YOUT GND SEIKO NPC CORPORATION —5 SM5330A Number Name I/O*1 Equivalent circuit VCC OUT_n 15 19 21 OUT_3 OUT_2 OUT_1 O GND 671Ω 500Ω VCCD 24 25 I/O_0 I/O_1 I/O 180Ω I/O_n DGND VCCD 100kΩ 26 ADS I 180Ω ADS 100kΩ DGND VDD 27 SCL I 180Ω SCL DGND SEIKO NPC CORPORATION —6 SM5330A Number Name I/O*1 Equivalent circuit VDD 28 SDA 180Ω I/O SDA DGND VCC 31 IREF O 70Ω 200Ω IREF GND VCC 32 VREF O VREF GND VCC 37 38 39 40 45 46 47 48 IN1_L1 IN1_L2 IN1_L3 IN1_SW IN2_L1 IN2_L2 IN2_L3 IN2_SW I 180Ω INn_Ln GND *1. I: input, O: output SEIKO NPC CORPORATION —7 SM5330A SPECIFICATIONS Absolute Maximum Ratings GND = 0V, VCC = VDD = VCCD Parameter Symbol Condition Rating Unit Supply voltage VCC −0.3 to 7.0 V Input voltage VIN GND – 0.3 to VCC + 0.3 V TSTG −55 to +125 °C 0.91 W 125 °C Rating Unit Storage temperature range Power dissipation PD Junction temperature TJ VCC, VDD, VCCD θja = 60°C/W (at Ta = 25°C, PCB wiring density: 100%, 0.5m/s air flow) Recommended Operating Conditions Parameter Symbol Condition Supply voltage 1 VCC VCC, VCCD 4.75 to 5.25 V Supply voltage 2 VDD VDD 3.0 to 5.5 V Wiring density: 100%, air flow: 0.5m/s –20 to 70 °C Operating ambient temperature Ta Electrical Characteristics DC Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75kΩ, CH-1 and CH-2 bias inputs, CH-3 clamp input, FCM = H, FCSET = 3Fh, unless otherwise noted. Parameter Symbol Current consumption ICC1 HIGH-level input voltage 1 VIH1 LOW-level Input voltage 1 VIL1 HIGH-level input voltage 2 Middle-level input voltage 2 Condition VCC = 5.25V, VIN = 0.0VP–P Rating Unit Test level 154 mA I min typ max – 112 0.7 VDD – – V I – – 0.3 VDD V I VIH2 0.8 VCC – – V I VIM2 VCC/2 − 0.2 – VCC/2 + 0.2 V I SDA, SCL ADS LOW-level input voltage 2 VIL2 – – 0.2 VCC V I HIGH-level input voltage 3 VIH3 3.5 – – V I Middle-level input voltage 3 VIM3 1.4 – 2.4 V I LOW-level input voltage 3 VIL3 – – 0.8 V I 3.5 – – V I – – 2.4 V I 3.2 – – V I – – 1.8 V I 3.0 – – V I – – 1.5 V I HIGH-level input voltage 4 VIH4 LOW-level Input voltage 4 VIL4 HIGH-level input voltage 5 VIH5 LOW-level Input voltage 5 VIL5 HIGH-level input voltage 6 VIH6 LOW-level Input voltage 6 VIL6 IN1_L1, IN1_L3, IN2_L1, IN2_L3 IN1_L2, IN2_L2 IN1_SW, IN2_SW I/O_0, I/O_1 HIGH-level input leakage current 1 ILH1 SDA, SCL at input voltage = VDD – – ± 1.0 µA I LOW-level input leakage current 1 ILL1 SDA, SCL at input voltage = 0V – – ± 1.0 µA I HIGH-level input leakage current 2 ILH2 I/O_0, I/O_1 at input voltage = VCC – – ± 1.0 µA I LOW-level input leakage current 2 ILL2 I/O_0, I/O_1 at input voltage = 0V – – ± 1.0 µA I LOW-level output voltage VOL SDA, I/O_0, I/O_1 at output current = 3mA 0.0 – 0.4 V I SEIKO NPC CORPORATION —8 SM5330A I2C BUS AC Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, unless otherwise noted. Rating Unit Test level 400 kHz II – – µs II 1.3 – – µs II tHIGH 0.6 – – µs II SCL setup time (start condition) tSU;STA 0.6 – – µs II SDA data hold time tHD;DAT 0 – 0.9 µs II SDA data setup time tSU;DAT 100 – – ns II SDA, SCL rise time tr − – 300 ns II SDA, SCL fall time tf − – 300 ns II SCL setup time (stop condition) tSU;STO 0.6 – – µs II Bus free time (stop condition to start condition) tBUF 1.3 – – µs II Ci – – 10 pF II Parameter Symbol Condition min typ max fSCL 0 – tHD;STA 0.6 SCL LOW-level clock pulsewidth tLOW SCL HIGH-level clock pulsewidth SCL clock frequency SCL hold time (start condition) SDA, SCL input capacitance SDA tf tLOW tr tBUF tr tSU;DAT tf tHD;STA SCL tHD;DAT tHD;STA tSU;STA tHIGH S tSU;STO Sr P Note. S, Sr: start condition, P: stop condition Analog Input Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75kΩ, FCM = H, FCSET = 3Fh, unless otherwise noted. Rating Parameter Clamp voltage Symbol VCLAMP Unit Test level 2.05 V I Condition min typ max Clamp input 1.65 1.85 Bias voltage VBIAS Bias input 2.15 2.35 2.55 V I Input resistance RIBIAS Bias input – 20 – kΩ II Input amplitude 1 VAI1 Clamp input, THD < 1.0% – – 1.2 Vp-p I Input amplitude 2 VAI2 Bias input, THD < 1.0% – – 1.2 Vp-p I Input DC voltage range VIDC Direct input 1.5 – 3.0 V I SEIKO NPC CORPORATION —9 SM5330A Analog Output Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75Ω, FCM = H, FCSET = 3Fh, unless otherwise noted. Rating Parameter Symbol Unit Test level 6.5 dB I Condition min typ max 5.5 6.0 Output gain AV OUT_1, OUT_2, OUT_3 Gain error between channels dAV Between OUT_1, OUT_2, and OUT_3 – – ± 0.2 dB I Output amplitude 1 VOUT1 Clamp input, THD < 1.0% – – 2.4 Vp-p I Output amplitude 2 VOUT2 Bias input, THD < 1.0% – – 2.4 Vp-p I Crosstalk between channels XTLKCH 0.5Vp-p input, fin = 1MHz, between 2 channels – −70 – dB II Crosstalk between input systems XTLKMUX 0.5Vp-p input, fin = 1MHz, between each input system – −70 – dB II Drive load resistance RL OUT_1, OUT_2, OUT_3 75 – – Ω I I2C response time tIIC Response time from ACK bit output when changing settings using I2C BUS – – 1 µs II Filter Frequency Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, fin = 100kHz, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75kΩ, CH-1 and CH-2 bias inputs, CH-3 clamp input, unless otherwise noted. Rating Parameter Cutoff frequency 4fc attenuation Symbol Condition min typ max Unit Test level fC1 FCM = 0, FCSET = 00h 4.50 5.11 5.72 MHz I fC2 FCM = 0, FCSET = 3Fh 11.71 13.30 14.89 MHz I fC3 FCM = 1, FCSET = 00h 13.74 15.61 17.48 MHz I fC4 FCM = 1, FCSET = 32h 30.96 35.18 39.40 MHz I fC5 FCM = 1, FCSET = 3Fh – 40.27 – MHz II ASB fin = 4fc, attenuation from fin = 100kHz − 60 − dB II SEIKO NPC CORPORATION —10 SM5330A DAC Characteristics VCC = 5.0V, VDD = 3.0 to 5.5V, Ta = 25°C, unless otherwise noted. Rating Parameter Symbol Differential linearity DLE Unit Test level +1 LSB I Condition DAC_0, DAC_1, Vn – Vn–1 min typ max −1 0 – 1, n = 1 to 255 (V191 – V63)/128 Vn: output voltage at resister value set “n” DAC HIGH-level output voltage VOH–DAC DAC_0, DAC_1, DAC0 = DAC1 = FFh 4.30 4.45 4.60 V I DAC LOW-level output voltage VOL–DAC DAC_0, DAC_1, DAC0 = DAC1 = 00h 0.25 0.35 0.45 V I DAC0 = DAC1 = FFh –0.5 − +0.5 mA I DAC output current IO–DAC Test Level The definition of “Test Level” shown in the electric characteristic table is as follows. I : 100% of products tested at Ta = + 25°C. II : Guaranteed as result of design and characteristics evaluation. Measurement Circuit SDA 1µF IN1_PB SCL I/O_1 SCL ADS SDA VDD I/O_0 IN1_L1 IN1_L2 IN1_L2 IN1_L3 IIN1_L3 VCC IN1_SW IN1_SW OUT_1 IN2_PB 75Ω/50Ω 75Ω/50Ω 75Ω/50Ω 1µF IN2_1 GND IN2_2 OUT_2 IN2_3 VCC VCC GND OUT_PR OUT_PB 1000µF 0Ω OUT_Y GND DAC_1 0Ω YOUT 1µF IN3_PB DAC_1 75Ω/50Ω 75Ω/50Ω 75Ω/50Ω 1µF DAC_0 1µF IN4_PR 1µF IN4_PB 75Ω/50Ω 75Ω/50Ω 1µF 75Ω/50Ω IN4_Y 1000µF 1µF IN3_PR IN3_Y TEST YOUT DAC_0 IN2_SW GND IN2_L3 IN2_SW IN4_3 GND IN4_2 IN2_L3 IN4_1 IN2_L2 GND OUT_3 IN3_3 IN2_L2 IN3_2 VCC IN2_L1 IN3_1 IN2_L1 0Ω 75Ω 1µF 1000µF 75Ω IN2_PR I/O_0 VCCD 75Ω 1µF 10kΩ 10kΩ 1.8kΩ±1% I/O_1 GND IREF GND VREF IN1_1 IN1_2 IN1_3 1µF 75Ω/50Ω 75Ω/50Ω 75Ω/50Ω 1µF IN1_L1 IN2_Y 2.2kΩ 1µF IN1_PR IN1_Y 2.2kΩ VDD VCC Note. This is a circuit only for the evaluation board of an electric characteristics. (It is not a recommended application circuit.) SEIKO NPC CORPORATION —11 SM5330A FUNCTIONAL DESCRIPTION I2C BUS Control The SM5330A uses the I2C BUS interface to control the following functions: 1) Cutoff frequency setting 2) Input type switching (synctip clamp, bias, or direct mode) 3) Mute setting 4) Input switch select 5) I/O output settings 6) DAC output settings In addition, the interface is used to read the following status parameters: 7) I/O input state 8) D-terminal signal discrimination result The transfer rate is compatible with fast mode (400kbit/s). Basic Cycle The write sequence is: SM5330A slave address → specific control register sub-address → write data. Data can be written to the SM5330A in successive bytes, as the sub-address for the register is incremented automatically after each byte. However, if the sub-address exceeds the address of the last register (04h), data write operation to the SM5330A register stops and the acknowledge signal is not returned. Single byte access S Slave address Sub address A A Data A P Multi byte access (address auto increment) S Slave address Sub address A A Data A Data ... A A Data A P S: START condition, P: STOP condition, A: acknowledge : drive master device : drive SM5330A Figure 1. Write sequence The read sequence is: SM5330A slave address → sub-address 0 status register value → sub-address 1 status register value → sub-address 2 status register value. Each read cycle comprises 3 bytes of read data. A specific status register sub-address cannot be assigned for a read operation. S Slave address A Data #0 A Data #1 A Data #2 A P S: START condition, P: STOP condition, A: acknowledge : drive master device : drive SM5330A Figure 2. Read sequence SEIKO NPC CORPORATION —12 SM5330A Slave Address The 7-bit slave address is selected using the ADS pin. When ADS = “L” the address is 48h, when ADS = “H” the address is 49h, and when ADS = “Z” (open) the address is 4Ah. A maximum of three SM5330A devices can be connected to one I2C BUS simultaneously, and controlled independently by setting the slave address of each using the ADS pin. SLAVE ADDRESS for control register write bit7 bit6 bit5 Name Value bit4 bit3 bit2 bit1 bit0 SLAVE ADDRESS (Hex) Description R/W 1 0 0 1 0 0 0 0 90h Indicate to write when device's slave address is 48h (ADS = "L") 1 0 0 1 0 0 1 0 92h Indicate to write when device's slave address is 49h (ADS = "H") 1 0 0 1 0 1 0 0 94h Indicate to write when device's slave address is 4Ah (ADS = "Z") bit3 bit2 bit1 bit0 (Hex) SLAVE ADDRESS for status register read bit7 bit6 bit5 Name Value bit4 SLAVE ADDRESS Description R/W 1 0 0 1 0 0 0 1 91h Indicate to read when device's slave address is 48h (ADS = "L") 1 0 0 1 0 0 1 1 93h Indicate to read when device's slave address is 49h (ADS = "H") 1 0 0 1 0 1 0 1 95h Indicate to read when device's slave address is 4Ah (ADS = "Z") bit2 bit1 bit0 Control Register The SM5330A has a 5-byte control register. CONTROL REGISTER MAP Addr. bit7 bit6 00h FCM − 01h 02h bit5 bit4 bit3 FCSET IM1 IM2 − IM3 IM4 − INSEL Description Filter fc setting − I/O1 Input mode setting I/O0 Input switch select, I/O output control 03h DAC0 DAC_0 output control 04h DAC1 DAC_1 output control The function of each byte in the control register is described in the following tables. SUB ADDRESS: 00h − Filter fc setting bit7 bit6 Name FCM − default 0 0 Value bit5 bit4 bit3 bit2 bit1 bit0 (Hex) 0 0 00h Description FCSET 0 0 0 0 0 Set filter to SD mode (default) 1 Set filter to HD mode 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 3Fh fc = 13.30MHz 1 0 0 0 0 0 0 0 80h fc = 15.61MHz 1 0 1 0 1 1 1 1 1 1 BFh : 00h : : : fc = 5.11MHz (default) : : fc = 40.27MHz Sets the cutoff frequency. When FCM = “0” the filter is set to SD mode, and when FCM = “1” the filter is set to HD mode. The relationship between the register value and the cutoff frequency is described in section “Lowpass Filter”. SEIKO NPC CORPORATION —13 SM5330A SUB ADDRESS: 01h − Input mode setting bit7 Name default bit6 bit5 IM1 bit4 bit3 IM2 bit1 0 0 bit0 (Hex) 0 00h Description IM4 0 0 0 0 IN1_3: synctip clamp input, IN1_2 and IN1_1: bias input (default) 0 1 IN1_3, IN1_2 and IN1_1: bias input 1 0 IN1_3, IN1_2 and IN1_1: synctip clamp input 1 1 IN1_3, IN1_2 and IN1_1: direct (DC) input Value 0 bit2 IM3 0 0 0 0 IN2_3: synctip clamp input, IN2_2 and IN2_1: bias input (default) 0 1 IN2_3, IN2_2 and IN2_1: bias input 1 0 IN2_3, IN2_2 and IN2_1: synctip clamp input 1 1 IN2_3, IN2_2 and IN2_1: direct (DC) input 0 0 IN3_3: synctip clamp input, IN3_2 and IN3_1: bias input (default) 0 1 IN3_3, IN3_2 and IN3_1: bias input 1 0 IN3_3, IN3_2 and IN3_1: synctip clamp input 1 1 IN3_3, IN3_2 and IN3_1: direct (DC) input 0 0 IN4_3: synctip clamp input, IN4_2 and IN4_1: bias input (default) 0 1 IN4_3, IN4_2 and IN4_1: bias input 1 0 IN4_3, IN4_2 and IN4_1: synctip clamp input 1 1 IN4_3, IN4_2 and IN4_1: direct (DC) input Sets the video signal input pin operating mode. SUB ADDRESS: 02h − Input switch select, I/O output control bit7 bit6 bit5 bit3 bit2 bit1 bit0 − − I/O1 I/O0 0 0 0 1 1 × 0 0 Mute 0 0 0 IN1_n select (default) 1 0 0 IN2_n select 1 0 0 0 IN3_n select 1 1 0 0 IN4_n select 0 0 0 0 I/O_1 output "L" 0 0 0 1 I/O_1 output off (input available) (default) 0 0 0 0 I/O_0 output "L" 0 0 0 1 I/O_0 output off (input available) (default) Name − default 0 1 0 0 0 × 0 1 0 0 1 0 0 1 0 1 Value bit4 INSEL (Hex) Description 43h Sets the video signal input switching and logic I/O pin output settings. The input can be switched between 4 systems (3-channels). This setting also determines the system that performs status register D-terminal discrimination. The I/O_0 and I/O_1 pins are n-channel MOS open-drain outputs. When the I/O pins are used as inputs, these bits are set to “1” so that the output is high impedance. SEIKO NPC CORPORATION —14 SM5330A SUB ADDRESS: 03h − DAC_0 output control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) Description Name default DAC0 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h Value : 1 1 1 1 : 1 1 1 1 FFh bit2 bit1 bit0 (Hex) DAC_0 output 0.35V (default) : DAC_0 output 4.45V SUB ADDRESS: 04h − DAC_1 output control bit7 bit6 bit5 bit4 bit3 Description Name default DAC1 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h Value : 1 1 1 1 : 1 1 1 1 FFh DAC_1 output 0.35V (default) : DAC_1 output 4.45V Sets the DAC_0 and DAC_1 pins output voltage, respectively. Status Register The SM5330A has a 3-byte status register. STATUS REGISTER MAP Addr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h − − − − − − IN1 IN0 01h 02h L1 − − L2 − − L3 − − SW1 Description I/O input status D-terminal input status SW2 D-terminal connection status The function of each byte in the status register is described in the following tables. SUB ADDRESS: 00h − I/O input status Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 − − − − − − IN1 IN0 0 0 0 0 0 0 0 I/O_1 input "L" (< 1.5V) 0 0 0 0 0 0 1 I/O_1 input "H" (> 3.0V) 0 0 0 0 0 0 0 I/O_0 input "L" (< 1.5V) 0 0 0 0 0 0 1 I/O_0 input "H" (> 3.0V) Description Value Returns the input state of the logic I/O pins. The I/O_0 and I/O_1 pins are n-channel MOS open-drain outputs. When the I/O pins are used as inputs, set the outputs “1” (high impedance) in the control register. SEIKO NPC CORPORATION —15 SM5330A SUB ADDRESS: 01h − D-terminal input status bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Description Name L1 L2 L3 Decode INn_Ln input selected series via INSEL register (L1: screen ruling) 0 0 1 INn_L1 input "L" (< 0.8V) means "480" 0 1 0 INn_L1 input "M" (1.4 to 2.4V) means "720" 1 0 0 INn_L1 input "H" (> 3.5V) means "1080" (L2: I/P) Value 0 1 INn_L2 input "L" (< 2.4V) means "60i" 1 0 INn_L2 input "H" (> 3.5V) means "60p" (L3: aspect ratio) 0 0 1 INn_L3 input "L" (< 0.8V) means "4 : 3" 0 1 0 INn_L3 input "M" (1.4 to 2.4V) means "Letter Box" 1 0 0 INn_L3 input "H" (> 3.5V) means "16 : 9" Returns the D-terminal discrimination result for the system determined by the INSEL register. SUB ADDRESS: 02h − D-terminal connection status bit7 bit6 bit5 bit4 bit3 bit2 bit0 SW1 SW2 Description − Name bit1 0 0 0 0 0 0 0 IN1_SW input "L" (< 1.8V) means "connected" 0 0 0 0 0 0 1 IN1_SW input "H" (> 3.2V) means "unconnected" 0 0 0 0 0 0 0 IN2_SW input "L" (< 1.8V) means "connected" 0 0 0 0 0 0 1 IN2_SW input "H" (> 3.2V) means "unconnected" Value Returns the D-terminal connection status information. SEIKO NPC CORPORATION —16 SM5330A Input Circuit The SM5330A video input pin operating mode can be switched between synctip clamp, bias, and direct (without DC restore) modes for each channel. The possible combinations are described below (set independently for each system). Table 1. Input mode combination Control register Input mode IMn value INn_1 INn_2 INn_3 00 b Bias Bias Clamp 01 b Bias Bias Bias 10 b Clamp Clamp Clamp 11 b Direct Direct Direct The SM5330A has a 4-system input switch built-in, and the system selected by the control register INSEL bits is input to the lowpass filter. When muting is selected (INSEL = 000b), the signal is not input to the lowpass filter and the output pins are DC level. SEIKO NPC CORPORATION —17 SM5330A Lowpass Filter The SM5330A has a 5th-order lowpass filter built-in, with a cutoff frequency selectable from 64 levels each for SD/HD mode controlled using the I2C BUS. The cutoff frequency settings are displayed graphically in figure 3, and shown in table 2. 50 45 40 fc [MHz] 35 30 25 20 15 10 5 0 0 32 64 96 128 160 192 Frequency [MHz] Figure 3. FCSET setting vs. Cutoff frequency Table 2. Cutoff frequency vs. FCDATA (RISET = 1.8kΩ) FCDATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FCDATA 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 FCSET (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F FCSET (hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F fc [MHz] FCDATA 5.11 5.24 5.37 5.50 5.63 5.76 5.89 6.02 6.15 6.28 6.41 6.54 6.67 6.80 6.93 7.06 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fc [MHz] FCDATA 15.61 16.01 16.40 16.79 17.18 17.57 17.96 18.35 18.75 19.14 19.53 19.92 20.31 20.70 21.09 21.48 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 FCSET (hex) 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F FCSET (hex) 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F fc [MHz] FCDATA 7.19 7.32 7.45 7.58 7.71 7.84 7.97 8.10 8.23 8.36 8.49 8.62 8.75 8.88 9.01 9.14 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 fc [MHz] FCDATA 21.88 22.27 22.66 23.05 23.44 23.83 24.22 24.62 25.01 25.40 25.79 26.18 26.57 26.96 27.36 27.75 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 FCSET (hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F FCSET (hex) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF fc [MHz] FCDATA 9.27 9.40 9.53 9.66 9.79 9.92 10.05 10.18 10.31 10.44 10.57 10.70 10.83 10.96 11.09 11.22 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 fc [MHz] FCDATA 28.14 28.53 28.92 29.31 29.70 30.10 30.49 30.88 31.27 31.66 32.05 32.44 32.84 33.23 33.62 34.01 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 FCSET (hex) 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F FCSET (hex) B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF fc [MHz] 11.35 11.48 11.61 11.74 11.87 12.00 12.13 12.26 12.39 12.52 12.65 12.78 12.91 13.04 13.17 13.30 fc [MHz] 34.40 34.79 35.18 35.58 35.97 36.36 36.75 37.14 37.53 37.92 38.32 38.71 39.10 39.49 39.88 40.27 SEIKO NPC CORPORATION —18 SM5330A YOUT Pin The YOUT pin is the unfiltered output of the selected system input pin (IN1_3, IN2_3, IN3_3, or IN4_3). The output gain is approximately 0dB. IREF Pin The IREF pin controls the built-in lowpass filter reference current, using a 1.8kΩ ± 1% control resistor that must be connected. The current flows into the IREF pin in normal operating mode and during output muting. VREF Pin The VREF pin is the internal reference voltage output. It is recommended that a capacitor be connected between VREF and GND to ensure SM5330A operating stability. The recommended value is 1µF. The voltage on VREF is output in normal operating mode and during output muting. D-Terminal Discrimination Function The D-terminal signal discrimination result can be read using the I2C BUS. The status register SW1 bit returns the state of IN1_SW, and the SW2 bit returns the state of IN2_SW. When IN1_n is selected by control register settings (INSEL = 100b), the status register L1, L2, L3 bits return the IN1_L1, IN1_L2, IN1_L3 pin states, respectively. Similarly, when IN2_n is selected (INSEL = 101b), the status register bits return the IN2_L1, IN2_L2, IN2_L3 pin states, respectively. DAC The SM5330A has two D/A converters controlled using the I2C BUS. The control register DAC0 bit controls the DAC_0 pin output voltage, and the DAC1 bit controls the DAC_1 output voltage. I/O The I/O_0 and I/O_1 I/O pins in output mode are n-channel MOS open-drain outputs. Connect pull-up resistance between respective pins and the VCCD pin. Recommendation value of pull-up resistance is 10kΩ. When these pins are used as inputs, set the outputs “1” (high impedance) in the control register. When these pins are not used, they should have pull-up connections to VCCD or be connected to DGND. Power-ON Reset When power is applied, an internal power-ON reset circuit operates, initializing all internal register settings to their default settings. Power should be applied simultaneously on all supply pins. SEIKO NPC CORPORATION —19 SM5330A RECOMMENDED APPLICATION CIRCUIT 1µF IN1_PR 2.2kΩ 2.2kΩ VDD VCC SDA 1µF IN1_PB SCL 1µF 75Ω 75Ω 75Ω IN2_Y 1.8kΩ±1% I/O_1 SCL ADS SDA VDD GND IREF GND VREF I/O_0 VCCD IIN1_L3 VCC IN1_SW OUT_1 IN2_1 GND IN2_2 OUT_2 IN2_3 VCC VCC GND GND DAC_1 TEST YOUT DAC_0 IN2_SW GND IN2_L3 IN2_SW IN4_3 GND IN4_2 IN2_L3 IN4_1 IN2_L2 GND OUT_3 IN3_3 IN2_L2 IN3_2 VCC IN2_L1 IN3_1 IN2_L1 1000µF 75Ω OUT_PR 1000µF 75Ω OUT_PB 1000µF 75Ω OUT_Y 75Ω 1µF IN2_PB I/O_0 75Ω IN2_PR I/O_1 75Ω 1µF IN1_1 1µF IN1_L3 IN1_SW IN1_2 IN1_L2 IN1_3 IN1_L1 IN1_L2 10kΩ 75Ω 75Ω 75Ω IN1_L1 10kΩ 1µF IN1_Y YOUT 1µF IN3_PR 1µF IN3_PB 1µF DAC_1 75Ω 75Ω 75Ω IN3_Y DAC_0 1µF IN4_PR 1µF IN4_PB 1µF 75Ω 75Ω 75Ω IN4_Y USAGE PRECAUTIONS Supply Connections Ensure that the VCC and VCCD have the same potential. VDD is the I2C BUS supply. The SCL and SDA signals should have a pull-up connection to VDD. Setting the Slave Address to 49h When the ADS pin is open-circuit, the slave address is set to 49h. When open, however, a large external spike noise or other interference can cause a malfunction. An external resistor should be connected to ADS as shown in figure 4 for protection. 29 VDD 10kΩ 26 ADS 10kΩ 30 VSS Figure 4. Slave address 49h setting SEIKO NPC CORPORATION —20 SM5330A TYPICAL PERFORMANCE VCC = 5.0V, VDD = 5.0V, Ta = 25°C, VIN = 1.0Vp-p, RISET = 1.8kΩ, RL = 75Ω, unless otherwise noted. 12 180 150 –12 120 –24 90 –36 60 –48 180 Gain 0 Gain [dB] 0 Group delay [ns] Gain [dB] Gain 150 –12 120 –24 90 –36 60 30 –48 0 –60 Group delay Group delay [ns] 12 30 Group delay –60 10 20 30 40 0 0 50 10 20 40 50 Frequency [MHz] Frequency [MHz] Figure 5. Gain and Group delay characteristics (FCDATA = 0) 12 Figure 6. Gain and Group delay characteristics (FCDATA = 63) 12 180 180 Gain 0 150 –12 120 –24 90 –36 60 –48 Gain [dB] Gain Group delay [ns] Gain [dB] 30 0 150 –12 120 –24 90 –36 60 30 –48 0 –60 Group delay [ns] 0 30 Group delay Group delay –60 0 10 20 30 40 0 50 20 60 0 100 80 Frequency [MHz] Frequency [MHz] Figure 7. Gain and Group delay characteristics (FCDATA = 128) Figure 8. Gain and Group delay characteristics (FCDATA = 191) 12 160 140 0 120 Group delay [ns] FCDATA = 191 –12 Gain [dB] 40 FCDATA = 128 –24 FCDATA = 63 FCDATA = 0 –36 100 FCDATA = 0 80 FCDATA = 63 60 FCDATA = 128 40 FCDATA = 191 –48 20 –60 0 1.0 10.0 Frequency [MHz] Figure 9. Gain vs. FCDATA 100.0 0 0 20 40 60 80 100 Frequency [MHz] Figure 10. Group delay vs. FCDATA SEIKO NPC CORPORATION —21 SM5330A Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: [email protected] NC0501AE 2006.06 SEIKO NPC CORPORATION —22