SONY CXA2134Q

CXA2134Q
US Audio Multiplexing Decoder
Description
The CXA2134Q is an IC designed as a decoder for
the Zenith TV Multi-channel System and also
corresponds with I2C bus. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in this IC.
Adjustment, mode control and sound processor
control are all executed through I2C bus.
Features
• Alignment-free VCO and filter
• Audio multiplexing decoder
dbx noise reduction decoder
sound processor
— Two external inputs
— Quasi-surround
— Bass control
— Treble control
— Volume control
are all included in a single chip. Almost any soft of
signal processing is possible through this IC.
• Input level, separation adjustments and each mode
control are possible through I2C bus.
48 pin QFP (Plastic)
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
11
• Operating temperature Topr –20 to +75
• Storage temperature
Tstg –65 to +150
• Allowable power dissipation
PD
0.6
V
°C
°C
W
Range of Operating Supply Voltage
9 ± 0.5
V
∗ A license of the dbx-TV noise reduction system is required for the use of this device.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99832-PS
3
4
48
1
32 31
30
29
27 28
26
22
25
24
SAPOUT
5
SDA
6
SCL
7
RMSDET
SAPIN
DGND
15
LPF
STIN
IREF
14
SW
LPF
SPECTRAL
RMSDET
VCA
VE
I2C BUS I/F
AMP
(+4dB)
HPF
VE
VEWGT
IREF
"PONRES"
"SAP"
DeEm
LOGIC
SURROUND
VETC
VGR
SAPIND
"NOISE"
LPF
NRSW/FOMO/SAPC
VEOUT
SAPTC 18
NOISE
DET
SAPVCO
(+6dB)
LPF
WIDEBAND
VCA
VCAIN
NOISETC 23
BPF
STIND
DeEm
LPF
TVSW
33
34
VCATC
VCAWGT
GND 17
FLT
MATRIX
9
TOUT-L
VCC 19
PCINT1
LPF
1/2
8
MAINOUT
VOLIN-L
ATT/ATTSW
VCA
1/4
PLINT
"STEREO"
VCO
21
MAININ
LSOUT-L
COMPIN 13
PCINT2
LFLT
SUBOUT
12
TREBLE
VOL-L
11
FEXT1
EXT1/EXT2/M1
SURR M2
AUX1-L
BASS
TREB
BASS
AUX1-R
VOL-L
BASS
TREB
LSOUT-R
–2–
VOL-R
10
FEXT2
VOL-R
Block Diagram
BASS-L
TOUT-R
43 VOLIN-R
44
41 TRE-R
47 TRE-L
45 BASS-R
2
40 SURRTC
38 TVOUT-R
39 TVOUT-L
36 AUX2-R
37 AUX2-L
CXA2134Q
CXA2134Q
36 35 34
33 32
31 30
SAPIN
VE
VEWGT
VETC
VEOUT
VCAIN
VCATC
VCAWGT
AUX1-R
AUX1-L
NC
AUX2-R
Pin Configuration (Top View)
29 28 27 26 25
24 SAPOUT
AUX2-L 37
TVOUT-R 38
23 NOISETC
TVOUT-L 39
22 STIN
SURRTC 40
21 SUBOUT
TRE-R 41
20 NC
NC 42
19 VCC
VOLIN-R 43
18 SAPTC
TOUT-R 44
17 GND
BASS-R 45
16 NC
NC 46
15 IREF
TRE-L 47
14 VGR
VOLIN-L 48
LSOUT-L
SDA
8
9
10
–3–
11 12
PLINT
LSOUT-R
7
PCINT2
BASS-L
6
PCINT1
5
MAINOUT
4
MAININ
3
DGND
2
SCL
1
TOUT-L
13 COMPIN
CXA2134Q
Pin Description
(Ta = 25°C, Vcc = 9V)
Pin No.
Symbol
Pin
voltage
1
TOUT-L
4.0V
Equivalent circuit
Description
VCC
Treble output pin.
(Left channel)
580
147
1
580
44
44
TOUT-R
Treble output pin.
(Right channel)
4.0V
Vcc
1.2k
2
BASS-L
1.2k
Bass filter pin.
(Left channel)
4.0V
147
5.4k
2
BASS-R
45
11k
11k
45
4.0V
Bass filter pin.
(Right channel)
4V
VCC
3k
3
LSOUT-R
LSOUT right channel output
pin.
4.0V
580
3
580
4
4
LSOUT-L
LSOUT left channel output
pin.
4.0V
VCC
7.5k
↓ 35µ
2.1V
4k
×2
5
SDA
—
7.5k
×5
4.5k
3k
5
–4–
Serial data I/O pin.
VIH > 3.0V
VIL < 1.5V
CXA2134Q
Pin No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
7.5k
↓ 35µ
2.1V
4k
6
SCL
—
×4
10.5k
3k
Serial clock input pin.
VIH > 3.0V
VIL < 1.5V
6
7
DGND
7
—
Digital block GND.
VCC
10k
VCC
8
MAININ
Input pin of (L + R) signal
from MAINOUT (Pin 9).
4.0V
147
8
53k
4V
VCC
15k
×4
9
MAINOUT
4.0V
147
(L + R) signal output pin.
9
↓
200µ
–5–
1k
CXA2134Q
Pin No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
147
10
10
PCINT1
30k
4.0V
22k
Stereo block PLL loop filter
integrating pin.
VCC
147
11
11
PCINT2
4.0V
10k
10k
2k
×2
4k
VCC
20k
20k
Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)
147
12
PLINT
12
5.1V
20k
20k
20k
10k
VCC
50k
147
13
13
COMPIN
4.0V
Audio multiplexing signal
input pin.
20k
22k
3k
3V
4k
4k
4k
16k
–6–
24k
CXA2134Q
Pin No.
Symbol
Pin
voltage
Equivalent circuit
3k
14
VGR
1.3V
9.7k
11k
19.4k
×4
Description
147
VCC
11k
11k
Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)
14
2.06k
VCC
40k
40k
30k
30k
15k
×2
VCC
15
IREF
1.3V
30p 1.8k
15
147
6.3k
17
GND
30k
Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based
on the current which flows to
this pin.
(Connect a 62kΩ (±1%)
resistor between this pin and
GND.)
16k
17
—
Analog block GND.
VCC
8k
10k
1k
3k
18
SAPTC
4.5V
VCC
4k
↓ 50µ
Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
18
19
Vcc
—
19
Supply voltage pin.
–7–
CXA2134Q
Pin No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
2k
2k
10P
4k
580
21
SUBOUT
4.0V
(L – R) signal output pin.
21
14.4k
2k
580 147
2k
4k
2k
1k
VCC
22
STIN
23k
23k
4.0V
Input pin of (L – R) signal
from SUBOUT (Pin 21).
11.7k
147
147
25
22
25
SAPIN
4.0V
18k
18k
4V
Input pin of (SAP) signal from
SUPOUT (Pin 24).
4V
20k
Vcc
8k
3.3k
10k
1k
23
NOISETC 3.0V
2k
4k
×2
4V
3k
Vcc
Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
3k
200k
23
Vcc
5P
580
24
SAPOUT
4.0V
580
147
24k
↓ 10µ
4k
↓ 50µ
–8–
SAP FM detector output pin.
10k
24
CXA2134Q
Pin No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
7.5k
26
VE
Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3kΩ resistor in series
between this pin and GND.)
147
4.0V
26
Vcc
2.9V
580
27
VEWGT
4.0V
4V
27
147
580
36k
8k
30k
↓ 8µ
Weight the variable
de-emphasis control
effective value detection
circuit.
(Connect a 0.047µF
capacitor and a 3kΩ resistor
in series between this pin
and GND.)
4k
↓ 50µ
Vcc
28
VETC
1.7V
×4
28
×4
20k
↓ 7.5µ
4k
↓ 50µ
Determine the restoration
time constant of the variable
de-emphasis control
effective value detection
circuit.
(The specified restoration
time constant can be
obtained by connecting a
3.3µF capacitor between this
pin and GND.)
Vcc
5P
580
29
VEOUT
4.0V
29
580
–9–
10k
Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 29
and 30.)
CXA2134Q
Pin No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
47k
30
VCAIN
20k
4.0V
47k
VCA input pin.
Input the variable
de-emphasis output signal
from Pin 29 via a coupling
capacitor.
VCC
30
VCC
×4
31
VCATC
Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(The specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)
31
×4
1.7V
↓
50µ
4k
↓
7.5µ
20k
VCC
40k
40k 3p
580
32
VCAWGT
4.0V
32
580 147
2.9V
36k
↓
50µ
33
AUX1-R
4k ↓
8µ
30k
Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)
8k
4.0V
VCC
Right channel external input
1 pin.
10k
34
AUX1-L
4.0V
147
33
27.5k
36
AUX2-R
4.0V
37
AUX2-L
4.0V
34
36
27.5k
4V
– 10 –
37
Left channel external input
1 pin.
Right channel external input
2 pin.
Left channel external input
2 pin.
CXA2134Q
Pin No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
3k
38
TVOUT right channel output
pin.
TVOUT-R 4.0V
580
147
38
580
39
39
TVOUT-L
TVOUT left channel output
pin.
4.0V
VCC
10k
40
SURRTC
580 40k
4.0V
20k
20k
24k
580
40
Set the center frequency of
the Surround circuit phase
shifter.
The frequency is determined
by the built-in resistor and
the external capacitor.
(Connect a 0.022µF
capacitor between this pin
and GND.)
Vcc
41
TRE-R
1.2k
4.0V
1.2k
Treble filter pin.
(Right channel)
5.7k
147
5.7k
6k
41
47
TRE-L
4.0V
43
VOLIN-R
4.0V
47
VCC
10k
Treble filter pin.
(Left channel)
Volume right channel input
pin.
147
43
48
48
VOLIN-L
4.0V
66k
4V
16
20
35
42
46
NC
—
– 11 –
Volume left channel input pin.
FCdeem
FCmain
Main de-emphasis
frequency response
Main LPF frequency
response
Main distortion
Main overload distortion
3
4
5
6
– 12 –
FCsub
SNsub
CTst
THst
HYst
Sub output level
Sub LPF frequency
response
Sub distortion
Sub overload distortion
Sub S/N
Crosstalk
Stereo → SAP
Sub pilot leak
Stereo ON level
Stereo ON/OFF
hysteresis
8
9
10
11
12
13
14
15
16
PCsub
THDsmax
THDsub
Vsub
Main S/N
7
SNmain
THDmmax
THDm
Vmain
Main output level
2
Icc
Signal
Current consumption
Item
ST
ST
SAP
ST
ST
ST
ST
ST
MONO
MONO
MONO
MONO
MONO
MONO
Mode
13
13
13
13
13
13
13
13
13
13
13
13
13
13
—
Input pin
Change
PILOT (fH) Level
20 log (‘on
level'/'off level')
0dB = 49mVrms
0dB = 49mVrms
fH BPF
1kBPF
20 log
('NRSW = 0'/
'NRSW = 1')
ST-L (R), 1kHz,
100% mod., NR ON,
SAP Carrier (5fH)
PILOT (fH) 0dB
15kLPF
20 log
('100%'/'0%')
15kLPF
SUB (L-R), 1kHz,
200% mod., NR OFF
SUB (L-R) 1kHz,
NR OFF
15kLPF
20 log
('12k'/'1k')
15kLPF
SUB (L-R) 1kHz,
100% mod., NR OFF
SUB (L-R) 12kHz,
30% mod., NR OFF
SUB (L-R), 1kHz,
100% mod., NR OFF
Mono 1kHz,
Pre-em. ON
20 log
('100%'/'0%')
15kLPF
Mono 1kHz 200% mod.
Pre-em. ON
BUS
RETURN
21
39
21
21
21
21
21
38/39
38/39
38/39
15kLPF
Mono 1kHz 100% mod.
Pre-em. ON
Mono 5kHz 30% mod.
Pre-em. ON
38/39
38/39
19
Output
pin
Mono 12kHz 30% mod. 20 log
Pre-em. ON
('12k'/'1k')
Filter
38/39
Measurement
conditions
20 log
('5k'/'1k')
Mono 1kHz 100% mod.
Pre-em. ON
No signal
Input signal
Main (L + R) (Pre-Emphasis: OFF) = 245mVrms
SUB (L – R) (dbx-TV: OFF) = 490mVrms
Pilot = 49mVrms
SAP Carrier = 147mVrms
fH = 15.734kHz
1
No.
Electrical Characteristics
COMPIN input level
(100% modulation level)
3.5
–9.0
—
60
56
—
—
–3.0
150
61
—
—
–3.0
–1.2
440
37
Min.
6.0
–6.0
–38
70
64
0.2
0.1
–0.5
190
69
0.15
0.1
–1.0
0
490
47
Typ.
8.5
–3.0
–27
—
—
2.0
1.0
1.0
230
—
0.5
0.5
1.0
1.0
540
57
Max.
dB
dB
dB
dB
dB
%
%
dB
mVrms
dB
%
%
dB
dB
mVrms
mA
Unit
(Ta = 25°C, VCC = 9V)
CXA2134Q
– 13 –
CTsap
HYsap
STLsep1
STRsep1
STLsep2
STRsep2
SAP S/N
Cross talk
SAP → Stereo
SAP ON level
SAP ON/OFF hysteresis
ST separation 1 L → R
ST separation 1 R → L
ST separation 2 L → R
ST separation 2 R → L
TVOUT output level
20
21
22
23
24
25
26
27
28
LSOUT cross talk
EXT → INT
LSOUT cross talk
INT → EXT
34
LSOUT output level
33
32
31
30
TVOUT
mute amount
SNsap
SAP distortion
19
29
FCsap
SAP LPF frequency
response
18
CTls
Vls
MUtv2
MUtv1
Vtv
THsap
THDsap
Vsap
Symbol
SAP output level
Item
17
No.
EXT
INT
EXT
INT
EXT
INT
EXT
ST
ST
ST
ST
SAP
ST
SAP
SAP
SAP
SAP
Mode
15kLPF
20 log
('Lch'/'Rch')
20 log
('Rch'/'Lch')
ST-L 3kHz 30% mod.
NR ON
ST-R 3kHz 30% mod.
NR ON
Mono 1kHz 100% mod.
Pre-em. ON
Sine wave 1kHz,
490mVrms
33/34
36/37
13
Sine wave 1kHz,
490mVrms
Mono 1kHz 100% mod.
Pre-em. ON
Sine wave 1kHz,
490mVrms
20 log (M1 =
"0"/M1 = "1")
Mono 1kHz 100% mod. 20 log (M1 =
"0"/M1 = "1")
Pre-em. ON
Sine wave 1kHz,
490mVrms
15kLPF
ST-R 300Hz 30% mod. 20 log
NR ON
('Rch'/'Lch')
1kBPF
1kBPF
1kBPF
15kLPF
15kLPF
20 log (‘on
level’/’off level’)
0dB = 147mVrms
1kBPF
15kLPF
ST-L 300Hz 30% mod. 20 log
('Lch'/'Rch')
NR ON
Change
SAP Carrier (5fH)
Level
SAP 1kHz 100% mod. 20 log ('NRSW
= 1'/'NRSW = 0')
NR ON, Pilot (fH)
33/34
36/37
13
33/34
36/37
13
33/34
36/37
13
13
13
13
13
13
SAP 1kHz, NR OFF
13
3/4
3/4
3/4
38/39
38/39
38/39
38/39
38/39
38/39
BUS
RETURN
39
24
24
SAP 1kHz 100% mod.
NR OFF
13
20 log
('100%'/'0%')
24
SAP 10kHz, 30% mod. 20 log
('10k'/'1k')
NR OFF
13
15kLPF
24
Output
pin
SAP 1kHz 100% mod.
NR OFF
Filter
13
Measurement
conditions
Input signal
Input pin
—
—
440
440
—
—
440
23
23
23
23
–90
–75
490
490
–95
–95
490
35
35
35
35
4.0
–9.0
–12.0
2.0
70
55
2.5
0
160
Typ.
60
46
—
–3.0
130
Min.
–80
–60
540
540
–80
–80
540
—
—
—
—
6.0
–6.5
—
—
6.0
2.5
190
Max.
dB
dB
mVrms
mVrms
dB
dB
mVrms
dB
dB
dB
dB
dB
dB
dB
dB
%
dB
mVrms
Unit
CXA2134Q
THDls
SNls
THDlsmax
TBmax
TBmin
TTmax
TTmin
VOLmin
Sr1
Sr2
LSOUT distortion
LSOUT S/N
LSOUT overload distortion
Bass maximum value
Bass minimum value
Treble maximum value
Treble minimum value
Volume minimum value
SURROUND
frequency response 1
SURROUND
frequency response 2
37
38
39
40
41
42
43
44
45
46
MUls
Symbol
OSls
LSOUT mute amount
Item
LSOUT DC offset
36
35
No.
– 14 –
15kLPF
BASS = "3F"
BASS = "0"
TREBLE = "3F"
TREBLE = "0"
VOL-L = "0",
VOL-R = "0"
Sine wave 1kHz,
2Vrms
Sine wave 100Hz,
490mVrms
Sine wave 100Hz,
490mVrms
Sine wave 10kHz,
490mVrms
Sine wave 10kHz,
490mVrms
Sine wave 1kHz,
490mVrms
33/34
36/37
33/34
36/37
33/34
36/37
33/34
36/37
33/34
36/37
33/34
36/37
EXT
EXT
EXT
EXT
EXT
EXT
EXT
34/37
34/37
15kLPF
Sine wave 1kHz,
490mVrms
33/34
36/37
EXT
EXT
15kLPF
Sine wave 1kHz,
490mVrms
33/34
36/37
4
4
Sine wave 10kHz,
490mVrms
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
Output
pin
Sine wave 330Hz,
490mVrms
1kBPF
1kBPF
EXT
No signal
Mute (M2 = "0")/
DC difference
when there is
no signal
20 log (M2 =
"0"/M2 = "1")
—
Sine wave 1kHz,
490mVrms
INT
EXT
Filter
33/34
36/37
Measurement
conditions
EXT
Input signal
Input pin
Mode
4.5
1.5
—
–13
9
–13
9
—
67
—
–25
—
Min.
6.0
3.0
–90
–11
11
–11
11
0.03
77
0.01
0
–90
Typ.
7.5
4.8
–80
–9
13
–9
13
0.5
—
0.5
25
–80
Max.
dB
dB
dB
dB
dB
dB
dB
%
dB
%
mV
dB
Unit
CXA2134Q
CXA2134Q
Electrical Characteristics Measurement Circuit
S6
S5
S4
S3
S2
S1
C26
4.7µ
C27
4.7µ
C28
0.022µ
C29
4700p
C21
1µ
C19
4.7µ
R6
3.3k
36
35
34
33
32
31
30
29
28
27
26
VCAWGT
VCATC
VCAIN
VEOUT
VETC
VEWGT
VE
C17
C16
0.047µ 2700p
AUX1-R
C20
10µ
R7
3k
AUX1-L
37
C22
4.7µ
C18
3.3µ
NC
C25
4.7µ
C23
4.7µ
R8
3.9k
AUX2-R
C24
4.7µ
V4
AC
AUX2-L
25
C15
4.7µ
SAPIN
V3
AC
V2
AC
MEASURES
15kHz LPF
fH BPF
1kHz BPF
TANTALUM
V1
AC
FILTER
SIGNAL SIGNAL
GENE- GENERATOR RATOR
SIGNAL
GENERATOR
TANTALUM
SIGNAL
GENERATOR
BUF
24
SAPOUT
38
TVOUT-R
NOISETC 23
39
TVOUT-L
STIN 22
40 SURRTC
SUBOUT 21
41 TRE-R
42
C14
4.7µ
C13
4.7µ
NC 20
VCC 19
NC
C12
100µ
SAPTC 18
43 VOLIN-R
C11
4.7µ
GND
45
NC 16
BASS-R
46 NC
IREF 15
47
VGR 14
TRE-L
C1
4.7µ
SCL
DGND
MAININ
MAINOUT
PCINT1
PCINT2
1
2
3
4
5
6
7
8
9
10
11
C2
0.1µ
C3
4.7µ
C4
4.7µ
R1
220
R2
220
C5
4.7µ
12
R3
1MEG
R4
C7
100k 0.012µ
I2C BUS DATA
DGND
– 15 –
C6
5600P
COMPIN
R5
62k ± 1% METAL
C10
10µ
SIGNAL
GENERATOR
C9
4.7µ
V6
AC
13
PLINT
SDA
48
LSOUT-L
VOLIN-L
LSOUT-R
C32
4700p
GND 17
TOUT-R
BASS-L
C31
0.1µ
44
TOUT-L
C30
4.7µ
VCC
V5
9V
GND
GND
C8
1µ
CXA2134Q
Adjustment Method
The resister data is set to the standard value.
1. ATT adjustment
1) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value
(490mVrms).
2) Adjustment range: ±20%
Adjustment bits:
4 bits
2.Separation adjustment
1) Input ST-L signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the
“WIDEBAND” adjustment data to reduce TVOUT-R output to the minimum.
2) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce TVOUT-R output to the minimum.
3) The adjustments in 1 and 2 above are performed to optimize the separation.
4) “WIDEBAND”
“SPECTRAL”
Adjustment range: ±30%
Adjustment range: ±15%
Adjustment bits:
6 bits
Adjustment bits: 6 bits
Note) Adjust this IC through tuner and IF when this IC is mounted on the set.
– 16 –
CXA2134Q
Register Specifications
Slave address
Slave receiver
Slave transmitter
84H (1000 0100)
85H (1000 0101)
Register table
Data
Sub address
MSB
LSB
BIT7
BIT5
BIT4
TEST-DA
TEST1
BIT6
BIT3
BIT2
∗∗∗∗0000
∗
∗∗∗∗0001
∗
SPECTRAL
∗∗∗∗0010
∗
WIDEBAND
∗
∗∗∗∗0011
M2
EXT1
∗
∗∗∗∗0100
BIT1
BIT0
ATT
EXT2
NRSW
FOMO
SAPC
M1
SURR
ATTSW
∗
FEXT1
FEXT2
∗∗∗∗0101
∗
BASS
∗∗∗∗0110
∗
TREBLE
∗∗∗∗0111
∗
VOL-L
∗∗∗∗1000
∗
VOL-R
∗: Don't care
Status registers
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SAP
NOISE
—
—
—
—
POWER
STEREO
ON RESET
Note) The microcomputer reads both SAP and NOISE status and judges SAP discrimination.
– 17 –
CXA2134Q
Description of Registers
Control registers
Register
Number
Classification∗1
of bits
Standard
setting
Contents
ATT
4
A
9
SPECTRAL
6
A
1F
Adjustment of stereo separation (3kHz)
WIDEBAND
6
A
1F
Adjustment of stereo separation (300Hz)
TEST-DA
1
T
0
DAC test mode
TEST1
1
T
0
Test mode
VOL-L
6
U
3F
Left channel volume control
VOL-R
6
U
3F
Right channel volume control
BASS
6
U
1F
Bass control
TREBLE
6
U
1F
Treble control
SURR
1
U
0
Quasi-surround function ON/OFF
NRSW
1
U
0
Selection of the output signal (Stereo mode, SAP mode)
FOMO
1
U
0
Forced MONO.
(Left channel only is MONO during SAP output.)
EXT1
1
U
0
Selection of TV mode or external input mode
EXT2
1
U
0
Selection of external input 1 mode or external input 2
mode (EXT1 = 1)
FEXT1
1
U
0
External input 1 forced MONO
FEXT2
1
U
0
External input 2 forced MONO
M1
1
U
1
Selection of TVOUT mute function ON/OFF
M2
1
U
1
Selection of LSOUT mute function ON/OFF
ATTSW
1
S
0
Main VCA ON/OFF
SAPC
1
S
0
Selection of SAP mode or L + R mode according to the
presence of SAP broadcasting
Input level adjustment
∗1 Classification U: User control
A: Adjustment
S: Proper to set
T: Test
Status registers
Register
Number of bits
Contents
PONRES
1
POWER ON RESET detection;
1: RESET
STEREO
1
Stereo discrimination of the COMPIN input signal;
1: Stereo
SAP
1
SAP discrimination of the COMPIN input signal;
1: SAP
NOISE
1
Noise level discrimination of the SAP input signal;
1: Noise
– 18 –
CXA2134Q
Description of Control Registers
ATT (4):
Perform input level adjustment.
0 = Level Min.
F = Level Max.
SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.
0 = Level Max.
3F = Level Min.
WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment.
0 = Level Min.
3F = Level Max.
TEST-DA (1): Set DAC output test mode.
0 = Normal mode
1 = DAC output test mode
In addition, the following outputs are present at Pin 39.
TVOUT-L (Pin 39): DA control DC level
TEST1 (1):
Monitor SAPBPF and NRBPF outputs.
0 = Normal mode
1 = SAPBPF, NRBPF outputs
In addition, the following outputs are present at Pins 39 and 38.
TVOUT-L (Pin 39): SAP BPF OUT
TVOUT-R (Pin 38): NR BPF OUT
VOL-L (6):
LSOUT-L output signal level control
0 = Volume Min.
3F= Volume Max.
–1.25 dB/STEP
VOL-R (6):
LSOUT-R output signal level control
0 = Volume Min.
3F= Volume Max.
–1.25 dB/STEP
BASS (6):
LSOUT output bass control
0 = Bass Min.
1F = Bass Center
3F = Bass Max.
TREBLE (6): LSOUT output treble control
0 = Treble Min.
1F = Treble Center
3F = Treble Max.
– 19 –
CXA2134Q
SURR (1):
Surround function selection
0 = Surround OFF
1 = Surround ON
NRSW (1):
Select stereo mode or SAP mode
0 = Stereo mode
1 = SAP mode
FOMO (1):
Select forced MONO mode
0 = Normal mode
1 = Forced MONO mode
EXT1 (1):
Select TV mode or external input mode for TVOUT output.
0 = TV mode
1 = External input mode
EXT2 (1):
Select external input [1] mode or external input [2] mode for TVOUT output. (EXT1 = 1)
0 = External input [1] mode
1 = External input [2] mode
FEXT1 (1):
Turn external input [1] to forced MONO.
0 = Normal mode
1 = External input [1] is forced MONO.
Input the same signal to both AUX1-L and AUX1-R.
FEXT2 (1):
Turn external input [2] to forced MONO
0 = Normal mode
1 = External input [2] is forced MONO
Input the same signal to both AUX2-L and AUX2-R.
M1 (1):
Mute the TVOUT-L and TVOUT-R output.
0 = Mute ON
1 = Mute OFF
M2 (1):
Mute the LSOUT-L and LSOUT-R output.
0 = Mute ON
1 = Mute OFF
ATTSW (1)
Select BYPASS SW of MVCA
0 = Normal mode
1 = MVCA is passed
SAPC (1):
Select the SAP signal output mode
When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC.
0 = L + R output is selected
1 = SAP output is selected
– 20 –
CXA2134Q
Description of Mode Control
SAPC = 0
NRSW
SAPC = 1
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
• During ST input:
left channel: L,
right channel: R
• During other input: left channel: L + R,
right channel: L + R
As on the left
NRSW = 1 (SAP output)
• When there is “SAP” during SAP
discrimination
– left channel: SAP, right channel: SAP
• When there is “No SAP”, output is the
same as when NRSW = 0.
NRSW = 1 (SAP output)
• Regardless of the presence of SAP
discrimination,
dbx input: “SAP”
left channel: SAP, right channel: SAP
However, when there is no SAP, SAPOUT
output is soft muted (–7dB)
“Forced MONO”
FOMO
SAPC
FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC = 0: Switch to SAP output when there is SAP discrimination.
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.
– 21 –
CXA2134Q
Decoder Output and Mode Control Table 1 (SAPC = 1)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
0
0
∗
1
MUTE
L+R
L+R
0
0
0
1
0
1
SAP
SAP
SAP
0
0
0
1
1
1
SAP
L+R
SAP
0
∗
1
0
∗
1
MUTE
L+R
L+R
0
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
0
∗
1
1
1
1
(SAP)
L+R
(SAP)
1
0
∗
0
0
1
L–R
L
R
1
0
∗
0
1
1
MUTE
L+R
L+R
1
1
1
0
0
1
L–R
L
R
1
1
1
0
1
1
MUTE
L+R
L+R
1
0
0
1
0
1
SAP
SAP
SAP
1
0
0
1
1
1
SAP
L+R
SAP
1
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
1
∗
1
1
1
1
(SAP)
L+R
(SAP)
0
1
∗
0
0
1
MUTE
L+R
L+R
0
1
∗
0
1
1
MUTE
L+R
L+R
0
1
0
1
0
1
SAP
SAP
SAP
0
1
0
1
1
1
SAP
L+R
SAP
0
1
1
1
0
1
(SAP)
(SAP)
(SAP)
0
1
1
1
1
1
(SAP)
L+R
(SAP)
1
1
∗
0
0
1
L–R
L
R
1
1
∗
0
1
1
MUTE
L+R
L+R
1
1
0
1
0
1
SAP
SAP
SAP
1
1
0
1
1
1
SAP
L+R
SAP
1
1
1
1
0
1
(SAP)
(SAP)
(SAP)
1
1
1
1
1
1
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
input in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is output.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 22 –
CXA2134Q
Decoder Output and Mode Control Table 2 (SAPC = 0)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
∗
∗
∗
0
MUTE
L+R
L+R
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
0
∗
0
0
0
L–R
L
R
1
0
∗
0
1
0
MUTE
L+R
L+R
1
0
∗
1
0
0
L–R
L
R
1
0
∗
1
1
0
MUTE
L+R
L+R
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
0
1
0
0
0
0
MUTE
L+R
L+R
0
1
0
0
1
0
MUTE
L+R
L+R
0
1
0
1
0
0
SAP
SAP
SAP
0
1
0
1
1
0
SAP
L+R
SAP
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
1
0
0
0
0
L–R
L
R
1
1
0
0
1
0
MUTE
L+R
L+R
1
1
0
1
0
0
SAP
SAP
SAP
1
1
0
1
1
0
SAP
L+R
SAP
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
input in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is output.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 23 –
CXA2134Q
Mode Control Table 3
M1
EXT1
EXT2
FEXT1
FEXT2
TVOUT-L
TVOUT-R
1
0
–
–
–
–
MUTE
MUTE
2
1
0
–
–
–
TV (L)
TV (R)
3
1
1
0
0
–
AUX1-L
AUX1-R
4
1
1
0
1
–
AUX1-L
AUX1-L
5
1
1
1
–
0
AUX2-L
AUX2-R
6
1
1
1
–
1
AUX2-L
AUX2-L
TV (L) / TV (R) are selected in MATRIX
TV (L): MONO, ST-L, SAP
TV (R): MONO, ST-R, SAP
– 24 –
CXA2134Q
Description of Operation
The US audio multiplexing system possesses the base-band spectrum shown in Fig. 1.
PEAK DEV
kHz
50
AM-DSB-SC
50
L-R
dbx-TV
NR
25
PILOT
25
15
SAP
dbx-TV NR
FM 10kHz
50 – 10kHz
L+R
5
50 – 15kHz
2fH
fH
3fH
4fH
TELEMETRY
FM 3kHz
3
5fH
6fH
6.5fH
f
fH = 15.734kHz
Fig. 1. Base-band spectrum
2fHL0°
fHL90°
fHL0°
PLL
(VCO 8fH)
13
PILOT
DET
MAIN LPF DE.EM
STEREO LPF
(COMPIN)
I2C BUS
DECODER
MODE
CONTROL
(MAIN OUT)
PILOT
CANCEL
MVCA
8
4.7µ
L+R
SUB LPF
L-R (DSB)
DET
WIDEBAND
(SUBOUT) (ST IN)
SUBVCA
21
L–R
SAP BPF
(MAIN IN)
9
SAP(FM)
DET
MATRIX
(Lch)
22
4.7µ
NR SW
A
SAP LPF
INJ.
LOCK
(SAP OUT)
dbx-TV
BLOCK
B
24
(SAP IN)
NOISE
DET
I2C
BUS
DECODER 4.7µ
25
MODE
CONTROL
I2C BUS
DECODER
MODE
CONTROL
SAP
DET
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(ST IN)
22
FIXED
VARIABLE
DEEMPHASIS DEEMPHASIS
NR SW
A
(VE OUT) (VCA IN)
30
29
(SAP IN)
4.7µ
25
HPF
RMS
DET
LPF
LPF
RMS
DET
Fig 3. dbx-TV block
– 25 –
B
VCA
to
MATRIX
(Rch)
to
TVSW
CXA2134Q
4.7µ
(AUX2-L) (AUX2-R)
37
36
(TOUT-L)
(TVOUT-L) (TVOUT-R)
39
(AUX1-L)
34
TVSW
1
48 (VOLIN-L)
(LSOUT-L)
38
BASS
TREBLE
VOL-L
4
SURROUND
33
VOL-R
(AUX1-R)
3
(LSOUT-R)
(Lch)
(TOUT-R) 44
(Rch)
from MATRIX
43 (VOLIN-R)
4.7µ
Fig. 4. Sound processor block
(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 13) passes through MVCA, the SAP signal
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the
L – R signal and SAP signal are removed by MAIN LPF, and the frequency response is flattened (deemphasized) and input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency response flattened using SAP LPF, and the SAP signal is
input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 24 output is soft
muted.
(4) Mode discrimination
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.
– 26 –
CXA2134Q
(5) dbx-TV block
Either the L – R signal or SAP signal input respectively from ST IN (Pin 22) or SAP IN (Pin 25) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.
(6) Matrix, TVSW
The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the BUS data and whether there is ST / SAP discrimination.
“TVSW” switches the “MATRIX” output signal, external input signal (input to AUX1-L, R), external input
signal (input to AUX2-L, R) and external forced MONO.
(7) Sound processor block
The sound processor block contains "SURROUND" (quasi-surround function), “BASS/TREBLE” tone
control functions, and “VOLUME”.
• Surround
At "SURROUND", the L and R differential components are phase-shifted and these components are
added to the left and right channels.
When surround is OFF (SURR = 0)
Inputs are output as is.
Lout = Lin
Rout = Rin
{
When surround is ON (SURR = 1)
{
Lout = Lin –
Rout = Rin +
1 – jωRC
1 + jωRC
1 – jωRC
1 + jωRC
(Lin – Rin)
(Lin – Rin)
(On-chip)
{ RC == 24kΩ
0.022µF (Externally attached to Pin 40)
(Lin, Lout) and Rin, (Rout) indicate the left- and right- channel I/O of the surround circuit.
(8) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 15) with GND become the reference current.
– 27 –
CXA2134Q
Application Circuit
AUX1 input
10µ
TANTALUM
3.9k
28
VCAIN
29
27
26
25
4.7µ
SAPIN
30
VCATC
VCAWGT
AUX1-R
AUX1-L
AUX2-L
24
SAPOUT
38 TVOUT-R
NOISETC 23
39 TVOUT-L
STIN 22
40 SURRTC
SUBOUT 21
4.7µ
4.7µ
4.7µ
4.7µ
0.022µ
41 TRE-R
NC 20
4700p
100µ
VCC 19
42 NC
+9V
SAPTC 18
43 VOLIN-R
4.7µ
4.7µ
44
GND 17
TOUT-R
GND
45
NC 16
BASS-R
62k ± 1%
METAL
0.1µ
46 NC
IREF 15
47 TRE-L
VGR 14
4.7µ
LSOUT-R
LSOUT-L
SDA
SCL
DGND
MAININ
MAINOUT
PCINT1
PCINT2
48
10µ
BASS-L
VOLIN-L
1
2
3
4
5
6
7
8
9
10
11
0.1µ
4.7µ
4.7µ
220
4.7µ
220
COMPIN
13
PLINT
4700p
TOUT-L
TVOUT
output
31
VE
32
33
34
NC
AUX2-R
37
35
3.3k
0.047µ 2700p
4.7µ
1µ
36
3k
3.3µ
TANTALUM
4.7µ
VEWGT
4.7µ
4.7µ
VETC
4.7µ
VEOUT
AUX2 input
4.7µ
Composite
baseband
signal input
12
1MEG
5600P
1µ
100k 0.012µ
DGND
LS output
µ-com
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 28 –
CXA2134Q
I2C Bus Block Items (SDA, SCL)
No.
Item
Symbol
Min.
Typ.
Max.
Unit
1
High level input voltage
VIH
3.0
—
5.0
2
Low level input voltage
VIL
0
—
1.5
3
High level input current
IIH
—
—
10
4
Low level input current
IIL
—
—
10
5
Low level output voltage SDA (Pin 5) during 3mA inflow
VOL
0
—
0.4
V
6
Maximum inflow current
IOL
3
—
—
mA
7
Input capacitance
CI
—
—
10
pF
8
Maximum clock frequency
fSCL
0
—
100
kHz
9
Minimum waiting time for data change
tBUF
4.7
—
—
10
Minimum waiting time for start of data transfer
tHD: STA
4.0
—
—
11
Low level clock pulse width
tLOW
4.7
—
—
12
High level clock pulse width
tHIGH
4.0
—
—
13
Minimum waiting time for start preparation
tSU: STA
4.7
—
—
14
Minimum data hold time
tHD: DAT
0
—
—
15
Minimum data preparation time
tSU: DAT
250
—
—
ns
16
Rise time
tR
—
—
1
µs
17
Fall time
tF
—
—
300
ns
18
Minimum waiting time for stop preparation
tSU: STO
4.7
—
—
µs
V
µA
µs
I2C bus load conditions: Pull-up resistor 4kΩ (Connect to +5V)
Load capacitor 200pF (Connect to GND)
I2C Bus Control Signal
SDA
tHD: STA
tF
tR
tBUF
SCL
P
S tHD: STA
tLOW
tHD: DAT
tHIGH
tSU: DAT
– 29 –
Sr
tSU: STA
tSU: STO
P
CXA2134Q
I2C Bus Signal
There are two I2C bus signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional
signal.
• Accordingly there are 3 values outputs, H, L and Hi-Z.
H
L
Hi-Z
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
– 30 –
CXA2134Q
• I2C data Write (Write from I2C controller to the IC)
Low during Write
MSB
MSB
LSB
Hi-Z
Hi-Z
SDA
1
SCL
2
3
4
5
6
7
8
9
1
8
9
S
Address
MSB
ACK
Sub Address
ACK
LSB
Hi-Z
1
Hi-Z
9
8
DATA (n)
1
ACK
8
DATA (n + 1)
ACK
Hi-Z
8
9
DATA (n + 2)
Hi-Z
9
1
8
∗ Data can be transferred in 8-bit units to be
9
set as required.
Sub address is incremented automatically.
P
DATA
ACK
DATA
ACK
• I2C data Read (Read from the IC to I2C controller)
High during Read
Hi-Z
SDA
SCL
1
6
7
8
9
7
1
8
9
P
S
Address
ACK
DATA
ACK
• Read timing
LSB
MSB
IC output SDA
SCL
Read timing
9
1
2
3
4
DATA
ACK
∗ Data Read is performed during SCL rise.
– 31 –
5
6
7
8
9
ACK
CXA2134Q
Input level vs. Distortion characteristics 2 (Stereo)
Input level vs. Distortion characteristics 1 (MONO)
10
Input signal: Stereo L = –R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF, ST mode
Measurement point: TVOUT-L/R
THD – Distortion [%]
THD – Distortion [%]
1.0
Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF
Measurement point: TVOUT-L/R
1.0
0.1
Standard level (100%)
–10
0
10
Standard level (100%)
Input level [dB]
–10
0
Input level [dB]
Input level vs. Distortion characteristics 3 (SAP)
THD – Distortion [%]
10
Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: TVOUT-L/R
1.0
Standard level (100%)
–10
0
Input level [dB]
10
– 32 –
10
CXA2134Q
Stereo LPF frequency response
10
Gain [dB]
5
0
–5
–10
0
20
40
60
80
100
Frequency [kHz]
Main LPF and Sub LPF frequency response
Gain (FC main and FC sub) [dB]
30
20
10
0
–10
–20
–30
–40
–50
1
2
5
7
10
20
50 70 100
Frequency [kHz]
SAP frequency response and group delay
100
20
90
5fH
70
60
50
0
40
30
–10
20
Group delay
3.8fH
–20
20
40
60
6.2fH
80
Frequency [kHz]
– 33 –
100
10
0
120
Group delay [µs]
10
Gain [dB]
80
Gain
CXA2134Q
Volume characteristics
0
LSOUT output level [dB]
–20
–40
–60
–80
Input:
AUX1, 2
1kHz, 490mVrms
Output: LSOUT
–100
0
F
1F
Control data VOL-L, VOL-R
– 34 –
2F
3F
CXA2134Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
0.15
36
25
24
48
13
13.5
37
12
0.8
+ 0.15
0.3 – 0.1
0.24
M
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-48P-L04
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
QFP048-P-1212
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 35 –