CXA2074Q/S
US Audio Multiplexing Decoder
Description
The CXA2074Q/S is an IC designed as a decoder
for the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in while
adjustment, mode control and sound processor
control are all executed through I2C BUS.
Features
• Audio multiplexing decoder, dbx noise reduction
decoder and sound processor are all included in a
single chip. Almost any sort of signal processing is
possible through this IC.
• All adjustments are possible through I2C BUS to
allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external
parts.
• There are three systems for inputs and two
systems for outputs, and each mode control is
possible.
Standard I/O Level
[( ) is the pin No. for the CXA2074S.]
• Input level
COMPIN (Pin 17)
245mVrms
AUX1-L/R (Pins 36 and 35)
490mVrms
AUX2-L/R (Pins 38 and 37)
490mVrms
• Output level
LPOUT-L/R (Pins 40 and 39)
490mVrms
LSOUT-L/R (Pins 8 and 7)
490mVrms
CXA2074Q
48 pin QFP (Plastic)
CXA2074S
42 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
11
V
• Operating temperature Topr –20 to +75
°C
• Storage temperature
Tstg –65 to +150
°C
• Allowable power dissipation
PD 0.6 (48 pin QFP) W
2.2 (42 pin SDIP) W
Range of Operating Supply Voltage
9 ± 0.5
V
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Structure
Bipolar silicon monolithic IC
∗ A license of the dbx-TV noise reduction system is
required for the use of this device.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96843B86
CXA2074Q/S
Pin Configuration (Top View)
36 35 34
33 32
31 30
SAPIN
VE
VEWGT
VETC
NC
VEOUT
VCAIN
VCATC
VCAWGT
NC
AUX1-R
AUX1-L
CXA2074Q
29 28 27 26 25
AUX2-R 37
24 SAPOUT
AUX2-L 38
23 NOISETC
LPOUT-R 39
22 STIN
LPOUT-L 40
21 SUBOUT
LPIN-R 41
20 NC
LPIN-L 42
19 VCC
NC 43
18 SAPTC
BASSR1 44
17 GND
BASSR2 45
16 IREF
BASSL1 46
15 VGR
BASSL2 47
14 COMPIN
TRER 48
8
9
10
NC
PCINT2
11 12
PCINT1
7
MAINOUT
6
MAININ
5
NC
4
DGND
3
LSOUT-L
TREL
LSOUT-R
2
SCL
1
SDA
13 PLINT
LPIN-L
LPIN-R
LPOUT-L
LPOUT-R
AUX2-L
AUX2-R
AUX1-L
AUX1-R
VCAWGT
VCATC
VCAIN
VEOUT
VETC
VEWGT
VE
SAPIN
SAPOUT
NOISETC
STIN
SUBOUT
VCC
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
BASSR1
BASSR2
BASSL1
BASSL2
TRER
TREL
LSOUT-R
LSOUT-L
SDA
SCL
DGND
MAININ
MAINOUT
PCINT1
PCINT2
PLINT
COMPIN
VGR
IREF
GND
SAPTC
CXA2074S
–2–
2
3
32
33
31
30
27 28
26
22
25
24
4
SDA
5
SCL
6
DGND
16
IREF
15
VGR
RMSDET
SAPOUT
SPECTRAL
SAPIN
"PONRES"
LPF
RMSDET
VCA
STIN
SW
LPF
HPF
VE
PASSSW
VE
I2C BUS I/F
AMP
(+4dB)
DeEm
LOGIC
NRSW/FOMO/SAPC
FEXT2
VEWGT
IREF
VCO FILTER
SAPIND
"SAP"
"NOISE"
LPF
LPF
WIDEBAND
VCA
TVSW
35
36
VEOUT
VETC
SAPTC 18
NOISE
DET
SAPVCO
STIND
DeEm
LPF
MATRIX
8
VCAIN
NOISETC 23
BPF
LPF
"STEREO"
FLT
PCINT1
VCAWGT
GND 17
(+6dB)
1/2
9
MAINOUT
VCATC
VCC 19
ATT
VCA
1/4
13
PCINT2
12
VCO
21
PLINT
LFLT
SUBOUT
11
MAININ
LSOUT-L
COMPIN 14
"FILTER"
STLPF
FEXT1
TVSW/EXT/M1
AUX1-L
VOL-L
BASS
PSW
VOL-L
BASS
M2 TREBLE
AUX1-R
TREB
VOL-R
BASS
TREB
–3–
LSOUT-R
CXA2074Q
VOL-R
Block Diagram
AUX2-L
BASSL1
BASSR1
TREL
TRER
1
48
45 BASSR2
44
47 BASSL2
46
41 LPIN-R
42 LPIN-L
39 LPOUT-R
40 LPOUT-L
37 AUX2-R
38
CXA2074Q/S
30
29
28
24
27
26
9
10
11
19
18
SPECTRAL
RMSDET
VGR
"PONRES"
LPF
HPF
VE
IREF
SW
LPF
DeEm
LOGIC
DGND
I2C BUS I/F
AMP
(+4dB)
NRSW/FOMO/SAPC
SCL
IREF
VCO FILTER
SAPIND
"SAP"
"NOISE"
LPF
WIDEBAND
VCA
SDA
SAPTC 21
NOISE
DET
SAPVCO
(+6dB)
LPF
LPF
1/2
SAPOUT
NOISETC 25
BPF
STIND
DeEm
1/4
SAPIN
GND 20
LPF
FLT
"STEREO"
VCO
STIN
VCC 22
ATT
VCA
PCINT1
VE
COMPIN 17
PCINT2
LFLT
PASSSW
TVSW
FEXT2
7
8
33
34
RMSDET
VCA
MATRIX
35
31 32
VEOUT
PLINT
VETC
36
VCAIN
"FILTER"
23
VCAWGT
STLPF
12
13
SUBOUT
VCATC
16
MAINOUT
LSOUT-L
15
MAININ
VEWGT
FEXT1
TVSW/EXT/M1
AUX1-L
VOL-L
BASS
PSW
VOL-L
BASS
M2 TREBLE
AUX1-R
TREB
VOL-R
BASS
TREB
–4–
LSOUT-R
14
VOL-R
CXA2074S
BASSL1
BASSL2
BASSR1
BASSR2
TREL
TRER
3
4
1
2
6
5
41 LPIN-R
42 LPIN-L
39 LPOUT-R
40 LPOUT-L
37 AUX2-R
38 AUX2-L
CXA2074Q/S
CXA2074Q/S
Pin Description
Pin No.
QFP SDIP
44
1
Symbol
BASSR1
Pin
voltage
VCC
4.0V
3k
(45) 2
45
2
BASSR2
4.0V
Description
Equivalent circuit
190
(47) 4
4.2k
190
3.4k
BASS filter pin. (Right channel)
(Connect a 47nF capacitor
between Pins 1 and 2 (44
and 45).)
The cutoff frequency is
determined by the built-in
resistor and the external
capacitance.
2.7k
2.2k
46
3
BASSL1
4.0V
1.8k
VCC
1.4k
1 (44)
1.2k
3 (46)
4.9k
47
4
BASSL2
4.0V
4V
BASS filter pin. (Left channel)
(Connect a 47nF capacitor
between Pins 3 and 4 (46
and 47).)
The cutoff frequency is
determined by the built-in
resistor and the external
capacitance.
VCC
3k
48
5
TRER
TREBLE filter pin.
(Right channel)
(Connect a 6.8nF capacitor
between this pin and GND.)
4.0V
580
4.2k
580
3.4k
2.7k
2.2k
1.8k
1.4k
VCC
1
6
TREL
TREBLE filter pin.
(Left channel)
(Connect a 6.8nF capacitor
between this pin and GND.)
1.2k
4.0V
4.9k
(48) 5
(1) 6
VCC
3k
2
7
LSOUT-R 4.0V
LSOUT right channel output
pin.
VCC
580
(2) 7
(3) 8
3
8
LSOUT-L
580
LSOUT left channel output
pin.
4.0V
–5–
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin
voltage
Description
Equivalent circuit
VCC
7.5k
↓ 35µ
2.1V
4k
×2
4
9
SDA
Serial data I/O pin.
VIH > 0V
VIL < 1.5V
×5
—
4.5k
7.5k
3k
9
(4)
VCC
7.5k
↓ 35µ
2.1V
4k
5
10
SCL
—
10.5k
×4
Serial clock input pin.
VIH > 3.0V
VIL < 1.5V
3k
10
(5)
6
11
DGND
11
—
Digital block GND.
(6)
VCC
10k
8
12
MAININ
VCC
Input the (L + R) signal from
MAINOUT (Pin 13 (9)).
4.0V
147
12
(8)
53k
4V
VCC
15k
×4
VCC
9
13
MAINOUT 4.0V
147
(L + R) signal output pin.
13
(9)
↓
200µ
–6–
1k
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin
voltage
Description
Equivalent circuit
VCC
147
14
30k
(11)
11
14
PCINT1
4.0V
22k
Stereo block PLL loop filter
integrating pin.
VCC
147
15
12
15
PCINT2
4.0V
(12)
10k
10k
2k
×2
4k
VCC
20k
13
16
PLINT
20k
Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)
147
5.1V
16
(13)
20k
↓
26µ
20k
20k ↓
50µ
10k
VCC
50k
147
17
(14)
14
17
COMPIN
4.0V
20k
22k
3k
3V
4k
4k
4k
16k
–7–
24k
Audio multiplexing signal
input pin.
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin
voltage
3k
15
18
VGR
1.3V
Description
Equivalent circuit
19.4k
9.7k
11k
147
VCC
×4
11k
11k
Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)
18
(15)
2.06k
VCC
40k
40k
30k
30k
15k
30k
×2
Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based
on the current which flows to
this pin.
(Connect a 62kΩ (±1%)
resistor between this pin and
GND.)
VCC
16
19
IREF
1.3V
30p 1.8k
19
147
6.3k
17
20
GND
(16)
16k
20
(17)
—
Analog block GND.
VCC
8k
10k
1k
3k
18
21
SAPTC
VCC
4.5V
4k
↓ 50µ
Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
21
(18)
19
22
VCC
—
22
Supply voltage pin.
(19)
–8–
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin
voltage
Description
Equivalent circuit
Vcc
2k
2k
10P
4k
580
21
23
SUBOUT 4.0V
(L – R) signal output pin.
23
2k
14.4k
2k
580 147
4k
2k
(21)
1k
VCC
23k
22
24
STIN
23k
Input the (L – R) signal from
SUBOUT (Pin 23 (21)).
4.0V
11.7k
147
147
25
27
SAPIN
4.0V
24
27
(22)
(25)
18k
18k
4V
Input the (SAP) signal from
SAPOUT (Pin 26 (24)).
4V
20k
Vcc
3.3k
8k
10k
1k
23
25
NOISETC 3.0V
2k
4k
×2
4V
Vcc
3k
3k
Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
200k
25
(23)
Vcc
5P
580
24
26
580
SAPOUT 4.0V
SAP FM detector output pin.
10k
26
147
24k
↓ 10µ
4k
↓ 50µ
–9–
(24)
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin
voltage
Description
Equivalent circuit
VCC
7.5k
26
28
VE
Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3kΩ resistor in series
between this pin and GND.)
147
4.0V
28
(26)
Vcc
2.9V
580
27
29
VEWGT 4.0V
29
(27)
4V
147
580
36k
8k
30k
↓ 8µ
Weight the variable
de-emphasis control
effective value detection
circuit.
(Connect a 0.047µF
capacitor and a 3kΩ resistor
in series between this pin
and GND.)
4k
↓ 50µ
Vcc
28
30
VETC
1.7V
×4
30
×4
(28)
20k
↓ 7.5µ
4k
↓ 50µ
Determine the restoration
time constant of the variable
de-emphasis control
effective value detection
circuit.
(The specified restoration
time constant can be
obtained by connecting a
3.3µF capacitor between this
pin and GND.)
Vcc
5P
580
30
31
VEOUT
4.0V
31
(30)
580
– 10 –
10k
Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 31
(30) and 32 (31).)
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin
voltage
Description
Equivalent circuit
VCC
47k
31
32
VCAIN
20k
4.0V
47k
VCA input pin.
Input the variable
de-emphasis output signal
from Pin 31 (30) via a
coupling capacitor.
VCC
32
(31)
VCC
×4
32
33
VCATC
33
(32)
×4
1.7V
4k
↓
50µ
Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(The specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)
20k
↓
7.5µ
VCC
40k
40k 3p
580
33
34
VCAWGT 4.0V
34
2.9V
580 147
36k
↓
50µ
35
35
4k ↓
8µ
30k
8k
AUX1-R 4.0V
VCC
10k
36
36
AUX1-L
4.0V
147
35
27.5k
37
37
AUX2-R 4.0V
38
AUX2-L
4.0V
36
37
47k
38
(33)
Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)
Right channel external input
1 pin.
Left channel external input
1 pin.
Right channel external input
2 pin.
38
4V
– 11 –
Left channel external input
2 pin.
CXA2074Q/S
Pin No.
QFP SDIP
Symbol
Pin
voltage
Description
Equivalent circuit
VCC
3k
39
39
LPOUT right channel output
pin.
LPOUT-R 4.0V
147
580
39
580
40
40
40
LPOUT-L 4.0V
41
41
LPIN-R
LPOUT left channel output
pin.
VCC
4.0V
10k
Right channel loop input pin.
147
41
42
47k
42
42
LPIN-L
Left channel loop input pin.
4.0V
4V
7
—
NC
—
(7)
10
—
NC
—
(10)
20
—
NC
—
(20)
29
—
NC
—
(29)
34
—
NC
—
(34)
43
—
NC
—
(43)
– 12 –
FCdeem
FCmain
Main de-emphasis
frequency characteristic
Main LPF frequency
characteristic
Main distortion
Main overload distortion
3
4
5
6
– 13 –
FCsub
THst
HYst
Sub LPF frequency
characteristic
Sub distortion
Sub overload distortion
Sub S/N
ST → SAP
Crosstalk
Sub pilot leak
Stereo ON level
Stereo ON/OFF
hysteresis
9
10
11
12
13
14
15
16
PCsub
CTst
SNsub
THDsmax
THDsub
Vsub
Sub output level
8
SNmain
Main S/N
7
THDmmax
THDm
Vmain
Main output level
2
Icc
Signal
Current consumption
Item
ST
ST
SAP
ST
ST
ST
ST
ST
MONO
MONO
MONO
MONO
MONO
MONO
Mode
SUB (L-R), 1kHz,
100% mod., NR OFF
17
(14)
PILOT (fH) 0dB
17
(14)
Change
PILOT (fH) Level
20 log
('NRSW = 0'/
'NRSW = 1')
SUB (L-R), 1kHz,
100% mod., NR ON,
SAP Carrier (5fH)
17
(14)
17
(14)
15kLPF
20 log
('100%'/'0%')
SUB (L-R) 1kHz,
NR OFF
17
(14)
20 log (‘on
level'/'off level')
0dB = 49mVrms
0dB = 49mVrms
15kLPF
SUB (L-R), 1kHz,
200% mod., NR OFF
17
(14)
fH BPF
1kBPF
15kLPF
SUB (L-R) 1kHz,
100% mod., NR OFF
17
(14)
20 log
('12k'/'1k')
SUB (L-R) 12kHz,
30% mod., NR OFF
17
(14)
15kLPF
Mono 1kHz,
Pre-em. ON
17
(14)
20 log
('100%'/'0%')
15kLPF
Mono 1kHz 200% mod.
Pre-em. OFF
17
(14)
3.5
–9.0
–
23
(21)
BUS
RETURN
60
56
–
–
–3.0
150
61
–
–
–3.0
–1.2
40
23
(21)
23
(21)
23
(21)
23
(21)
23
(21)
39/40
39/40
39/40
15kLPF
Mono 1kHz 100% mod.
Pre-em. ON
17
(14)
39/40
39/40
20 log
('5k'/'1k')
Mono 12kHz 30% mod. 20 log
Pre-em. ON
('12k'/'1k')
Mono 5kHz 30% mod.
Pre-em. ON
17
(14)
17
(14)
440
39/40
Min.
Mono 1kHz 100% mod.
Pre-em. ON
Output
pin
17
(14)
Filter
30
Measurement
conditions
No signal
Input signal
6.0
–6.0
–35
70
64
0.2
0.1
–0.5
190
69
0.15
0.1
–1.0
0
490
40
Typ.
dB
dB
–3.0
8.5
dB
dB
dB
%
%
dB
mVrms
dB
%
%
dB
dB
mVrms
mA
Unit
–27
–
–
2.0
1.0
1.0
230
–
0.5
0.5
1.0
1.0
540
50
Max.
The pin numbers in parenthesis are for the CXA2074Q.
(Ta = 25°C, VCC = 9V)
17
(14)
Input pin
Main (L + R) (Pre-Emphasis: OFF) = 245mVrms
SUB (L – R) (dbx-TV: OFF) = 490mVrms
Pilot = 49mVrms
SAP Carrier = 147mVrms
fH = 15.734kHz
1
No.
Electrical Characteristics
COMPIN input level
(100% modulation level)
CXA2074Q/S
– 14 –
HYsap
STLsep1
STRsep1
STLsep2
STRsep2
SAP ON level
SAP ON/OFF hysteresis
ST separation 1 L → R
ST separation 1 R → L
ST separation 2 L → R
ST separation 2 R → L
LPOUT output level
22
23
24
25
26
27
28
LSOUT output level
LSOUT cross talk
LSOUT muted amount
31
32
33
30
LPOUT
muted amount
CTsap
SAP → ST
Cross talk
21
29
SNsap
SAP S/N
20
MUls
CTls
Vls
MUlp2
MUlp1
Vtp
THsap
SAP
THDsap
SAP distortion
19
1kBPF
1kBPF
0dB = 490mVrms
EXT → INT
0dB=490mVrms
INT → EXT
20 log (M2 =
"0"/M2 = "1")
Sine wave 1kHz,
490mVrms
MONO 1kHz
100%, Pre-em. on
Sine wave 1kHz,
490mVrms
35/36
37/38
17
(14)
35/36
37/38
EXT
EXT
INT
EXT
1kBPF
0dB = 490mVrms
Sine wave 1kHz,
490mVrms
35/36
37/38
0dB = 490mVrms
MONO 1kHz
100%, Pre-em. on
17
(14)
1kBPF
INT
INT
EXT
20 log (M1 =
"0"/M1 = "1")
0dB = 490mVrms
15kLPF
Sine wave 1kHz,
490mVrms
ST-R 3kHz 30% mod.
NR ON
Sine wave 1kHz,
490mVrms
17
(14)
15kLPF
15kLPF
35/36
37/38
ST-R 300Hz 30% mod.
NR ON
ST-L 3kHz 30% mod.
NR ON
17
(14)
17
(14)
15kLPF
EXT
ST-L 300Hz 30% mod.
NR ON
17
(14)
20 log (‘on
level’/’off level’)
0dB = 147mVrms
MONO 1kHz, 100%, 20 log (M1 =
Pre-em. on
"0"/M1 = "1")
Change
SAP Carrier (5fH)
Level
17
(14)
1kBPF
15kLPF
20 log
SAP 1kHz, NR OFF ('100%'/'0%')
17
(14)
17
(14)
SAP 1kHz 100% mod. 20 log ('NRSW
NR ON, Pilot (fH)
= 1'/'NRSW = 0')
15kLPF
SAP 1kHz 100% mod.
NR OFF
Filter
17
(14)
Measurement
conditions
SAP 1kHz 100% mod.
NR OFF
SAP 10kHz, 30% mod. 20 log
NR OFF
('10k'/'1k')
Input signal
17
(14)
17
(14)
Input pin
35/36
37/38
17
(14)
ST
ST
ST
ST
SAP
ST
SAP
SAP
FCsap
SAP LPF frequency
characteristic
18
SAP
Mode
Vsap
Symbol
SAP output level
Item
17
No.
–
–
7/8
(2/3)
–
–0.9
–
–
–0.5
23
23
23
23
2.0
–12.0
60
46
–
–3.0
150
Min.
7/8
(2/3)
7/8
(2/3)
7/8
(2/3)
39/40
39/40
39/40
39/40
39/40
39/40
BUS
RETURN
40
26
(24)
26
(24)
26
(24)
Output
pin
26
(24)
–90
–90
–75
0
–90
–85
0
35
35
35
35
4.0
–9.0
70
55
2.5
0
190
Typ.
–75
–80
–60
0.9
–75
–70
0.5
–
–
–
–
6.0
–6.5
–
–
6.0
2.5
230
Max.
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
%
dB
mVrms
Unit
CXA2074Q/S
Volume minimum value
42
BASS minimum value
39
TREBLE minimum value
BASS maximum value
38
41
LSOUT overload distortion
37
TREBLE maximum value
SNls
LSOUT S/N
36
40
THDls
LSOUT distortion
35
– 15 –
VOLmin
TTmin
TTmax
TBmin
TBmax
THDlsmax
OSls
Symbol
LSOUT DC offset
Item
34
No.
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
2Vrms
Sine wave 100Hz,
245mVrms
Sine wave 100Hz,
245mVrms
35/36
37/38
35/36
37/38
35/36
37/38
35/36
37/38
EXT
EXT
EXT
EXT
EXT
EXT
EXT
Sine wave 1kHz,
490mVrms
35/36
37/38
EXT
7/8
(2/3)
7/8
(2/3)
TREBLE = "0"
0dB = 245mVrms
VOL-L = "0",
VOL-R = "0"
0dB = 490mVrms
Sine wave 10kHz,
245mVrms
Sine wave 1kHz,
490mVrms
35/36
37/38
35/36
37/38
7/8
(2/3)
7/8
(2/3)
7/8
(2/3)
7/8
(2/3)
7/8
(2/3)
7/8
(2/3)
7/8
(2/3)
Output
pin
TREBLE = "F"
0dB = 245mVrms
1kBPF
15kLPF
15kLPF
15kLPF
Filter
Sine wave 10kHz,
245mVrms
BASS = "0"
0dB = 245mVrms
BASS = "F"
0dB = 245mVrms
20 log
('490mVrms'/
'No signal')
Mute (M2 = 0)/
DC difference
when there is
no signal
Measurement
conditions
35/36
37/38
No signal
—
INT
EXT
Input signal
Input pin
Mode
–
–13
11
–13
11
–
75
–
–25
Min.
–90
–12
12
–12
12
0.1
88
0.01
0
Typ.
–75
–11
13
–11
13
1.0
–
0.5
25
Max.
dB
dB
dB
dB
dB
%
dB
%
mV
Unit
CXA2074Q/S
CXA2074Q/S
I2C BUS block items (SDA, SCL)
No.
Item
Symbol
Min.
Typ.
Max.
Unit
1
High level input voltage
VIH
3.0
—
5.0
2
Low level input voltage
VIL
0
—
1.5
3
High level input current
IIH
—
—
10
4
Low level input current
IIL
—
—
10
5
Low level output voltage SDA (Pin 9) during 3mA inflow
VOL
0
—
0.4
V
6
Maximum inflow current
IOL
3
—
—
mA
7
Input capacitance
CI
—
—
10
pF
8
Maximum clock frequency
fSCL
0
—
100
kHz
9
Minimum waiting time for data change
tBUF
4.7
—
—
10
Minimum waiting time for start of data transfer
tHD: STA
4.0
—
—
11
Low level clock pulse width
tLOW
4.7
—
—
12
High level clock pulse width
tHIGH
4.0
—
—
13
Minimum waiting time for start preparation
tSU: STA
4.7
—
—
14
Minimum data hold time
tHD: DAT
0
—
—
15
Minimum data preparation time
tSU: DAT
250
—
—
ns
16
Rise time
tR
—
—
1
µs
17
Fall time
tF
—
—
300
ns
18
Minimum waiting time for stop preparation
tSU: STO
4.7
—
—
µs
V
µA
µs
I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V)
Load capacity 200pF (Connect to GND)
I2C BUS Control Signal
SDA
tHD: STA
tF
tR
tBUF
SCL
P
S tHD: STA
tLOW
tHD: DAT
tHIGH
tSU: DAT
– 16 –
Sr
tSU: STA
tSU: STO
P
CXA2074Q/S
Electrical Characteristics Measurement Circuit
CXA2074Q
C3
4.7µ
C4
4.7µ
SIGNAL
GENERATOR
V1
AC
C5
4.7µ
C6
4.7µ
V3
AC
C7
4.7µ
VCATC
30
29
28
SAPOUT
24
NOISETC 23
38 AUX2-L
39
C28
4.7µ
SAPIN
VCAWGT
AUX2-R
31
VE
32
R4
R6
3k
3.3k
C18
C19
0.047µ 2700p
27
26
25
VEWGT
33
TANTALUM
34
C17
3.3µ
VETC
35
C15
4.7µ
NC
36
NC
C14
10µ
AUX1-R
37
C12
4.7µ
AUX1-L
C2
4.7µ
R1
3.9k
C13
1µ
MEASURES
15kHz LPF
fH BPF
1kHz BPF
V6
AC
V5
AC
C10
4.7µ
FILTERS
VEOUT
V4
AC
BUFF
VCAIN
V2
AC
SIGNAL SIGNAL
GENE- GENERATOR RATOR
TANTALUM
SIGNAL SIGNAL
GENE- GENERATOR RATOR
S6
S5
S4
S3
S2
S1
LPOUT-R
STIN 22
40 LPOUT-L
SUBOUT 21
41 LPIN-R
NC 20
42 LPIN-L
VCC 19
C22
4.7µ
C29
4.7µ
C23
100µ
SAPTC 18
43 NC
SIGNAL
GENERATOR
44 BASSR1
GND 17
C24
4.7µ
VCC
V8
9V
GND
GND
IREF 16
46 BASSL1
VGR 15
C11
6.8n
MAININ
MAINOUT
NC
PCINT1
5
6
7
8
9
10
11
R3
220
C16
4.7µ
C20
5600P
PCINT2
NC
4
R2
220
DGND
3
SCL
2
SDA
LSOUT-L
1
48 TRER
C1
6.8n
R8
62k METAL ± 1%
C25
10µ
SIGNAL
GENERATOR
C26
4.7µ
V7
AC
COMPIN 14
47 BASSL2
LSOUT-R
C9
47n
45 BASSR2
TREL
C8
47n
PLINT 13
C27
1µ
12
R7
1MEG
R5
C21
100k 0.012µ
I2C BUS DATA
DGND
– 17 –
GND
LSOUT-R
7
TREL
6
TRER
8
LSOUT-L
5
C11
4.7µ
C13
4.7µ
R1
220
I2C BUS DATA
10
SDA
9
R3
220
C18
4.7µ
DGND
DGND
12
MAININ
11
PCINT2
MAINOUT
R4
C22
100k 0.012µ
C20 5600p
15
PLINT
16
C24
1µ
C26
4.7µ
COMPIN
18
VGR
GND
AC
SIGNAL
GENERATO
R
V7
17
C27
10µ
IREF
19
SAPTC
21
GND
20
GND
2
LPIN-L
BASSR1
C9
6.8n
LPIN-R
BASSR2
C7
6.8n
LPOUT-L
BASSL1
C5
47n
LPOUT-R
BASSL2
C2
47n
AUX2-L
1
R6
1MEG
AUX2-R
14
AUX1-L
PCINT1
13
AUX1-R
4
VCAWGT
SCL
– 18 –
3
22
23
24
25
26
27
28
29
30
C29
4.7µ
31
C28
4.7µ
32
C25
4.7µ
VCATC
C23
2700p
VCAIN
C21
0.047µ
R7
3.3k
VEOUT
33
C17
4.7µ
R5
3k
VETC
34
C15
1µ
R2
3.9k
VEWGT
35
C14
4.7µ
15kHz LPF
fH BPF
1kHz BPF
VE
36
C12
4.7µ
AC
V6
SAPIN
37
C10
4.7µ
AC
V5
SAPOUT
38
C8
4.7µ
AC
V4
NOISETC
39
C6
4.7µ
AC
V3
STIN
40
C4
4.7µ
SIGNAL
GENERATOR
MEASURE
S
SUBOUT
41
C3
4.7µ
AC
V2
FILTER
S
VCC
42
C1
4.7µ
AC
V1
SIGNAL
SIGNAL
GENERATOR GENERATOR SIGNAL
GENERATOR
C16 10µ
TANTALUM
SIGNAL
GENERATOR
BUFF
C19 3.3µ
TANTALUM
SIGNAL
GENERATOR
S
6
S
5
S
4
S
3
S
2
S
1
R8 62k
METAL ± 1%
CXA2074S
C30
4.7µ
C31
100µ
VCC
GND
V8
9V
CXA2074Q/S
CXA2074Q/S
I2C BUS Register Data Standard Setting Values
Register
Number Classifi- Standard
of bits cation
setting
Contents
ATT
4
A
9
VCO
6
A
1F
FILTER
6
A
1F
SPECTRAL
6
A
1F
WIDEBAND
6
A
1F
TEST-DA
1
T
0
TEST1
1
T
0
FST
1
T
0
VOL-L
6
U
3F
3F = 0dB
VOL-R
6
U
3F
3F = 0dB
BASS
4
U
8
7 or 8 = 0dB
TREBLE
4
U
8
7 or 8 = 0dB
NRSW
1
U
—
FOMO
1
U
—
TVSW
1
U
0
EXT
1
U
0
FEXT1
1
U
FEXT2
1
PSW
Setting value when electrical
characteristics are measured
Center point
Adjustment point
Normal mode
Standard setting value
Normal mode
FST = 0
According to the mode control table
TV decoder output selection
Standard setting value
0
External input 1 forced MONO
Standard setting value
U
0
External input 2 forced MONO
Standard setting value
1
U
0
TVSW output selection
Standard setting value
M1
1
U
1
M2
1
U
1
ATTSW
1
S
—
SAPC
1
S
—
Mute OFF
Fixed by the set specifications
Classification A: Adjustment
U: User control
S: Proper to set
T: Test
– 19 –
FILTER
WIDEBAND
ST & SAP
& dbx FILTER
Low frequency
ST separation
3
SPECTRAL
VCO
ST & SAP
VCO
2
High frequency
ST separation
ATT
MAIN VCA
1
4
Adjustment
data
Adjustment item
List of Adjustment Contents
ST-L 30%
300Hz
COMPIN
Pin 17
(Pin 14)
ST-L 30%
3kHz
9.4kHz
600mVrms
COMPIN
Pin 17
(Pin 14)
COMPIN
Pin 17
(Pin 14)
None
100Hz
245mVrms
COMPIN
Pin 17
(Pin 14)
None
Input signal
data
Input pin
LPOUT-R output
level
LPOUT-R output
level
Minimize the output level
Minimize the output level
Adjust to the center of the
FILADJ = 1 condition
Adjust as close to 62.936kHz
as possible
LPOUT-R output
frequency
STA5
(FILADJ)
Adjust as close to 490mVrms
as possible
Adjustment contents
LPOUT-L output
level
Measurement
TEST1 = 1
TEST-DA = 1
Test mode
setting
The pin numbers in parenthesis are for the CXA2074Q.
CXA2074Q/S
– 20 –
CXA2074Q/S
Adjustment Method (Adjust this IC through Tuner and IF when this IC is mounted on the set.)
1. ATT adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LPOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the LPOUT-L output goes to the standard value
(490mVrms).
3) Adjustment range: ±30%
Adjustment bits:
4 bits
2. Stereo, SAPVCO adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 1”.
2) Monitor the LPOUT-R output (4fH free running) frequency in a no input state, and adjust “VCO”
adjustment data so that this frequency is as close to 4fH (62.936kHz) as possible.
3) Adjustment range: ±20%
Adjustment bits:
6 bits
3. Stereo, SAP block, dbx filter adjustment
1) TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”.
2) Input a 9.4kHz, 600mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA5)
condition, adjust the “FILTER” adjustment data.
3) Adjustment range: ±20%
Adjustment bits:
6 bits
Align “FILTER” with the center of the STA5 = 1 (adjustment OK) condition range.
Adjustment point
3F
0
Control data
"FILTER"
1
Measurement data
STA5 "FILADJ"
0
4.Separation adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz
NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce LPOUT-R output to
the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce LPOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
5) “WIDEBAND”
“SPECTRAL”
Adjustment range: ±30%
Adjustment range: ±15%
Adjustment bits:
6 bits
Adjustment bits: 6 bits
– 21 –
CXA2074Q/S
Description of Operation [The pin numbers in parenthesis are for the CXA2074Q.]
The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz
50
AM-DSB-SC
50
L-R
dbx-TV
NR
25
PILOT
25
15
SAP
dbx-TV NR
FM 10kHz
50 – 10kHz
L+R
5
50 – 15kHz
2fH
fH
3fH
4fH
5fH
TELEMETRY
FM 3kHz
3
6fH
6.5fH
f
fH = 15.734kHz
Fig. 1. Base band spectrum
2fHL0°
fHL90°
fHL0°
PLL
(VCO 8fH)
17
PILOT
DET
MAIN LPF DE.EM
STEREO LPF
(COMPIN)
I2C BUS
DECODER
MODE
CONTROL
(MAIN OUT)
PILOT
CANCEL
MVCA
(9)
(14)
SUB LPF
L-R (DSB)
DET
SAP BPF
SAP(FM)
DET
(MAIN IN)
13
WIDEBAND
4.7µ
L+R
(SUBOUT) (ST IN)
SUBVCA
INJ.
LOCK
SAP
DET
(Lch)
NR SW
A
(SAP OUT)
26
(24)
NOISE
DET
MATRIX
23
24
(21) 4.7µ (22)
L–R
SAP LPF
12
(8)
dbx-TV
BLOCK
B
(SAP IN)
I2C BUS
DECODER 4.7µ
27
(25)
MODE
CONTROL
I2C BUS
DECODER
MODE
CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(ST IN)
(22) 24
FIXED
VARIABLE
DEEMPHASIS DEEMPHASIS
NR SW
A
(VE OUT) (VCA IN)
32
31
(30) 4.7µ (31)
(SAP IN)
(25) 27
HPF
RMS
DET
LPF
LPF
RMS
DET
Fig 3. dbx-TV block
– 22 –
B
VCA
to
MATRIX
(Rch)
to
TVSW
CXA2074Q/S
(LPIN-L) (LPIN-R)
(AUX2-L) (AUX2-R)
38
37
42
41
(LPOUT-L) (LPOUT-R)
40
(AUX1-L)
39
VOL-L
36
35
TVSW
BASS
PASSSW
(LSOUT-L)
8 (3)
7 (2)
VOL-R
(AUX1-R)
(Lch)
TREBLE
(LSOUT-R)
(Rch)
from MATRIX
Fig. 4. Sound processor block
(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 17 (Pin 14)) passes through MVCA, the
SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are
canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency
characteristics are flattened (de-emphasized) and input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 26 output is
soft muted.
(4) Mode discrimination
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.
(5) dbx-TV block
Either the L – R signal or SAP signal input respectively from ST IN (Pin 24 (Pin 22)) or SAP IN (Pin 27
(Pin 25)) is selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
– 23 –
CXA2074Q/S
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.
(6) Matrix, TVSW, PASSSW
The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the BUS data and whether there is ST / SAP discrimination.
“TVSW” switches the “MATRIX” output signal, external input signal (input to AUX1-L, R), external input
signal (input to AUX2-L, R) and external forced MONO.
“PASSSW” switches the “TVSW” output signal and external input signal (input to LPIN-L, R).
(7) Sound processor block
The sound processor block contains, “BASS/TREBLE” tone control functions, and “VOLUME”.
BASS:
±12dB (±1.7dB/STEP at 100Hz)
TREBLE: ±12dB (±1.7dB/STEP at 10kHz)
VOLUME: 0 to –80dB (–1.25dB/STEP)
(8) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 19 (Pin 16)) with GND become the reference current.
Standard input and output levels
Input pin
COMPIN
∗1
∗2
∗3
LPOUT output level
LSOUT output level∗3
245mVrms∗1
490mVrms∗2
490mVrms∗2
Pin No.
Input level
17
(14)
AUX1-L/AUX1-R
36/35
490mVrms
490mVrms
490mVrms
AUX2-L/AUX2-R
38/37
490mVrms
490mVrms
490mVrms
LPIN-L/LPIN-R
42/41
490mVrms
—
490mVrms
MONO, 25kHz Deviation, Pre-Em. off
MONO, 25kHz Deviation, Pre-Em. on
VOLUME MAX, BASS & TREBLE CENTER
– 24 –
CXA2074Q/S
Register Specifications
Slave address
SLAVE RECEIVER SLAVE TRANSMITTER
80H (1000 0000)
81H (1000 0001)
Register table
DATA
SUB ADDRESS
MSB
LSB
BIT7
BIT6
BIT5
BIT4
BIT3
TEST-DA
TEST1
BIT2
BIT1
BIT0
∗∗∗∗0000
∗
∗∗∗∗0001
∗
VCO (6)
∗∗∗∗0010
∗
FILTER (6)
∗∗∗∗0011
∗
SPECTRAL (6)
∗∗∗∗0100
∗
WIDEBAND (6)
∗∗∗∗0101
∗
ATTSW
FST
NRSW
FOMO
SAPC
M1
∗∗∗∗0110
∗
PSW
FEXT1
FEXT2
TVSW
EXT
M2
∗∗∗∗0111
∗
VOL-L (6)
∗∗∗∗1000
∗
VOL-R (6)
ATT (4)
∗∗∗∗1001
∗
BASS (4)
∗∗∗∗1010
∗
TREBLE (4)
∗ : Don't Care
Status Registers
when TEST1 = 0
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SAP
NOISE
—
—
—
—
POWER
STEREO
ON RESET
when TEST1 = 1
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SAP
NOISE
FILADJ
—
—
—
POWER
STEREO
ON RESET
– 25 –
CXA2074Q/S
Description of Registers
Control registers
Register
Number of bits Classification∗1
Contents
ATT
4
A
Input level adjustment
VCO
6
A
STEREO VCO & SAP VCO free running frequency adjustment
FILTER
6
A
STEREO and SAP and dbx filter adjustment
SPECTRAL
6
A
Adjustment of stereo separation (3kHz)
WIDEBAND
6
A
Adjustment of stereo separation (300Hz)
TEST-DA
1
T
Turn to DAC test mode and VCO adjustment mode by means
of TEST-DA = 1.
TEST1
1
T
Turn to test mode by means of TEST = 1.
(Adjustment of FILTER)
FST
1
T
Turn to forced stereo by means of FST = 1.
VOL-L
6
U
LSOUT-L output signal level control
VOL-R
6
U
LSOUT-R output signal level control
BASS
4
U
LSOUT output bass control
TREBLE
4
U
LSOUT output treble control
NRSW
1
U
Selection of the output signal (Stereo mode, SAP mode)
FOMO
1
U
Turn to forced MONO by means of FOMO = 1.
(Left channel only is MONO during SAP output.)
TVSW
1
U
Selection of TV mode or external input mode for LPOUT
output
EXT
1
U
Selection of external input 1 mode or external input 2 mode
for LPOUT output. (TVSW = 1)
FEXT1
1
U
External input 1 forced MONO (1: forced MONO ON)
FEXT2
1
U
External input 2 forced MONO (1: forced MONO ON)
PSW
1
U
Selection of internal mode or LPIN mode for LSOUT output.
M1
1
U
Selection of LPOUT mute ON/OFF
(0: mute ON, 1: mute OFF)
M2
1
U
Selection of LSOUT mute ON/OFF
(0: mute ON, 1: mute OFF)
ATTSW
1
S
Turn the input stage MVCA off when ATTSW = 1.
SAPC
1
S
Selection of SAP mode or L + R mode according to the
presence of SAP broadcasting
∗1 Classification U: User control
A: Adjustment
S: Proper to set
T: Test
– 26 –
CXA2074Q/S
Status registers
Register
Number of bits
Contents
PONRES
1
POWER ON RESET detection;
1: RESET
STEREO
1
Stereo discrimination of the COMPIN input signal;
1: Stereo
SAP
1
SAP discrimination of the COMPIN input signal;
1: SAP
NOISE
1
Noise level discrimination of the SAP signal;
1: Noise
FILADJ
1
Status of FILTER adjustment;
1: OK range
Description of Control Registers
ATT (4):
Adjust the signal level input to COMPIN (Pin 17 (Pin 14)) to the standard input level (245mVrms).
Variable range of the input signal: 245mVrms –5.0dB to +3.0dB
0 = Level min.
F = Level max.
VCO (6):
Adjust STEREO & SAP VCO free running frequency (fo).
Variable range: fo ±20%
0 = Free running frequency min.
3F = Free running frequency max.
FILTER (6):
Adjust the filter fo of the ST, SAP and dbx blocks.
Variable range: fo ±20%
0 = Frequency min.
3F= Frequency max.
SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.
0 = Level max.
3F = Level min.
WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment.
0 = Level min.
3F = Level max.
TEST-DA (1): Set DAC output test mode and VCO adjustment mode.
0 = Normal mode
1 = DAC output test mode and VCO adjustment mode
In addition, the following outputs are present at Pins 40 and 39.
LPOUT-L (Pin 40): DA control DC level
LPOUT-R (Pin 39): STEREO VCO oscillation frequency (4fH)
– 27 –
CXA2074Q/S
TEST1 (1):
Set filter adjustment mode.
0 = Normal mode
1 = FILTER (STA5) adjustment mode
In addition, the following outputs are present at Pins 40 and 39.
LPOUT-L (Pin 40): SAP BPF OUT
LPOUT-R (Pin 39): NR BPF OUT
FST (1):
Select forced STEREO mode
0 = Normal mode
1 = Forced stereo mode
VOL-L (6):
LSOUT-L output signal level control
0 = Volume Min. (–80dB)
3F= Volume Max. (0dB)
–1.25 dB/STEP
VOL-R (6):
LSOUT-R output signal level control
0 = Volume Min. (–80dB)
3F= Volume Max. (0dB)
–1.25 dB/STEP
BASS (4):
LSOUT output bass control
0 = Bass Min.
7 & 8 = Bass Center (0dB)
F = Bass Max.
TREBLE (4): LSOUT output treble control
0 = Treble Min.
7 & 8 = Treble Center (0dB)
F = Treble Max.
NRSW (1):
Select stereo mode or SAP mode
0 = Stereo mode
1 = SAP mode
FOMO (1):
Select forced MONO mode
0 = Normal mode
1 = Forced MONO mode
TVSW (1):
Select TV mode or external input mode for LPOUT output.
0 = TV mode
1 = External input mode
EXT (1):
Select external input [1] mode or external input [2] mode for LPOUT output. (TVSW = 1)
0 = External input [1] mode
1 = External input [2] mode
– 28 –
CXA2074Q/S
FEXT1 (1):
Turn external input [1] to forced MONO.
0 = Normal mode
1 = External input [1] is forced MONO.
Input the same signal to both AUX1-L and AUX1-R.
FEXT2 (1):
Turn external input [2] to forced MONO
0 = Normal mode
1 = External input [2] is forced MONO
Input the same signal to both AUX2-L and AUX2-R.
PSW (1)
Select INT mode or LPIN mode for LSOUT output.
0 = INT mode
1 = LPIN mode
M1 (1):
Mute the LPOUT-L and LPOUT-R output.
0 = Mute ON
1 = Mute OFF
M2 (1):
Mute the LSOUT-L and LSOUT-R output.
0 = Mute ON
1 = Mute OFF
ATTSW (1)
Select BYPASS SW of MVCA
0 = Normal mode
1 = MVCA is passed
SAPC (1):
Select the SAP signal output mode
When there is no SAP signal, the conditions for selecting SAP output are selected by
SAPC.
0 = L + R output is selected
1 = SAP output is selected
– 29 –
CXA2074Q/S
Description of Mode Control
Priority ranking: M1/M2 > TVSW/EXT > TEST-DA > TEST1 > (NRSW & FOMO & SAPC)
Mode control
NRSW
SAPC = 0
SAPC = 1
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
• During ST input:
left channel: L,
right channel: R
• During other input: left channel: L + R,
right channel: L + R
As on the left
NRSW = 1 (SAP output)
• When there is “SAP” during SAP
discrimination
– left channel: SAP, right channel: SAP
• When there is “No SAP”, output is the
same as when NRSW = 0.
NRSW = 1 (SAP output)
• Regardless of the presence of SAP
discrimination,
dbx input: “SAP”
left channel: SAP, right channel: SAP
However, when there is no SAP, SAPOUT
output is soft muted (–7dB)
“Forced MONO”
FOMO
SAPC
FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC = 0: Switch to SAP output when there is SAP discrimination.
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.
“MUTE”
M1/M2
TVSW/EXT
TEST1
TEST-DA
M1 = 0: LPOUT output is muted.
M2 = 0: LSOUT output is muted.
“TV mode/external input mode selection”
TVSW = 0: Set LPOUT output to TV mode.
TVSW = 1: Set LPOUT output to external input mode.
EXT = 0: Set LPOUT output to external input [1] mode. (TVSW = 1)
EXT = 1: Set LPOUT output to external input [2] mode. (TVSW = 1)
“TEST1”
TEST1 = 1
Return adjustment data with STATUS REGISTER as an adjustment mode.
In addition, outputs are as follows.
left channel: SAP BPF OUT
right channel: NR BPF OUT
“TEST-DA”
TEST-DA = 1
Used to adjust the D/A TEST and VCO.
left channel: D/A output
right channel: STVCO oscillation frequency (4fH)
– 30 –
CXA2074Q/S
Decoder Output and Mode Control Table 1 (SAPC = 1)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
0
0
∗
1
MUTE
L+R
L+R
0
0
0
1
0
1
SAP
SAP
SAP
0
0
0
1
1
1
SAP
L+R
SAP
0
∗
1
0
∗
1
MUTE
L+R
L+R
0
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
0
∗
1
1
1
1
(SAP)
L+R
(SAP)
1
0
∗
0
0
1
L–R
L
R
1
0
∗
0
1
1
MUTE
L+R
L+R
1
1
1
0
0
1
L–R
L
R
1
1
1
0
1
1
MUTE
L+R
L+R
1
0
0
1
0
1
SAP
SAP
SAP
1
0
0
1
1
1
SAP
L+R
SAP
1
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
1
∗
1
1
1
1
(SAP)
L+R
(SAP)
0
1
∗
0
0
1
MUTE
L+R
L+R
0
1
∗
0
1
1
MUTE
L+R
L+R
0
1
0
1
0
1
SAP
SAP
SAP
0
1
0
1
1
1
SAP
L+R
SAP
0
1
1
1
0
1
(SAP)
(SAP)
(SAP)
0
1
1
1
1
1
(SAP)
L+R
(SAP)
1
1
∗
0
0
1
L–R
L
R
1
1
∗
0
1
1
MUTE
L+R
L+R
1
1
0
1
0
1
SAP
SAP
SAP
1
1
0
1
1
1
SAP
L+R
SAP
1
1
1
1
0
1
(SAP)
(SAP)
(SAP)
1
1
1
1
1
1
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 31 –
CXA2074Q/S
Decoder Output and Mode Control Table 2 (SAPC = 0)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
∗
∗
∗
0
MUTE
L+R
L+R
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
0
∗
0
0
0
L–R
L
R
1
0
∗
0
1
0
MUTE
L+R
L+R
1
0
∗
1
0
0
L–R
L
R
1
0
∗
1
1
0
MUTE
L+R
L+R
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
0
1
0
0
0
0
MUTE
L+R
L+R
0
1
0
0
1
0
MUTE
L+R
L+R
0
1
0
1
0
0
SAP
SAP
SAP
0
1
0
1
1
0
SAP
L+R
SAP
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
1
0
0
0
0
L–R
L
R
1
1
0
0
1
0
MUTE
L+R
L+R
1
1
0
1
0
0
SAP
SAP
SAP
1
1
0
1
1
0
SAP
L+R
SAP
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 32 –
CXA2074Q/S
Mode Control Table 3
M1
TVSW
EXT
FEXT1
FEXT2
LPOUT-L
LPOUT-R
1
0
–
–
–
–
MUTE
MUTE
2
1
0
–
–
–
TV (L)
TV (R)
3
1
1
0
0
–
AUX1-L
AUX1-R
4
1
1
0
1
–
AUX1-L
AUX1-L
5
1
1
1
–
0
AUX2-L
AUX2-R
6
1
1
1
–
1
AUX2-L
AUX2-L
TV (L) / TV (R) are selected in MATRIX
TV (L): MONO, ST-L, SAP, (SAPBPFout, D/Aout)
TV (R): MONO, ST-R, SAP, (NRBPFout, STVCO freerun (4fH))
I2C BUS Signal
There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.
• Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
– 33 –
CXA2074Q/S
• I2C data Write (Write from I2C controller to the IC)
L during Write
MSB
MSB
LSB
HIZ
HIZ
SDA
1
SCL
2
3
4
5
6
7
8
9
1
8
9
S
Address
MSB
ACK
Sub Address
ACK
LSB
HIZ
1
HIZ
9
8
DATA (n)
1
ACK
8
DATA (n + 1)
ACK
HIZ
8
9
DATA (n + 2)
HIZ
9
1
8
∗ Data can be transferred in 8-bit units to be
9
set as required.
Sub address is incremented automatically.
P
DATA
ACK
DATA
ACK
• I2C data Read (Read from the IC to I2C controller)
H during Read
HIZ
SDA
SCL
1
6
7
8
9
7
1
8
9
P
S
Address
ACK
DATA
ACK
• Read timing
LSB
MSB
IC output SDA
SCL
Read timing
9
1
2
3
4
DATA
ACK
∗ Data Read is performed during SCL rise.
– 34 –
5
6
7
8
9
ACK
CXA2074Q/S
Input level vs. Distortion characteristics 2 (Stereo)
Input level vs. Distortion characteristics 1 (MONO)
10
Input signal: Stereo L = –R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF, ST mode
Measurement point: LPOUT-L/R
Distortion [%]
Distortion [%]
1.0
Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF
Measurement point: LPOUT-L/R
1.0
0.1
Standard level (100%)
–10
0
10
Standard level (100%)
Input level [dB]
–10
0
Input level [dB]
Input level vs. Distortion characteristics 3 (SAP)
Distortion [%]
10
Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: LPOUT-L/R
1.0
Standard level (100%)
–10
0
Input level [dB]
10
– 35 –
10
CXA2074Q/S
Stereo LPF frequency characteristics
10
Gain [dB]
5
0
–5
–10
0
20
40
60
80
100
Frequency [kHz]
Main LPF and Sub LPF frequency characteristics
Gain (FC main and FC sub) [dB]
30
20
10
0
–10
–20
–30
–40
–50
1
2
5
7
10
20
50 70 100
Frequency [kHz]
SAP frequency characteristics and group delay
100
20
90
5fH
70
60
50
0
40
30
–10
20
Group delay
3.8fH
–20
20
40
60
6.2fH
80
Frequency [kHz]
– 36 –
100
10
0
120
Group delay [µs]
10
Gain [dB]
80
Gain
CXA2074Q/S
BASS-TREBLE characteristics
BASS. MAX
TREBLE. MAX
BASS. MIN
TREBLE. MIN
+12
+4
0
–4
–8
–12
20
100
1k
Frequency [Hz]
10k
Input:
AUX1, 2
245mVrms
Output: LSOUT
Volume characteristics
0
–20
LSOUT output level [dB]
Boost amount [dB]
+8
–40
–60
–80
Input:
AUX1, 2
1kHz, 490mVrms
Output: LSOUT
–100
0
F
1F
Control data VOL-L, VOL-R
– 37 –
2F
3F
20k
CXA2074Q/S
Package Outline
Unit: mm
CXA2074Q
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
48
13
13.5
37
12
0.8
+ 0.15
0.3 – 0.1
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
± 0.12 M
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
SONY CODE
QFP-48P-L04
EIAJ CODE
∗QFP048-P-1212-B
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
CXA2074S
+ 0.1
– 0.05
0.25
42PIN SDIP (PLASTIC) 600mil
+ 0.4
37.8 – 0.1
42
+ 0.3
13.0 – 0.1
15.24 ± 0.25
22
0° to 15°
21
1
0.5 MIN
3.0 MIN
0.5 ± 0.1
0.9 ± 0.15
+ 0.4
4.6 – 0.1
1.778 ± 0.25
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SDIP-42P-02
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SDIP042-P-0600-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
4.4g
JEDEC CODE
– 38 –