CXA1734S US Audio Multiplexing Decoder For the availability of this product, please contact the sales office. Description The CXA1734S is an IC designed as a decoder for the Zenith TV Multi-channel System also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation and dbx noise reduction. Various kinds of filters are built in while adjustment and mode control are all executed through I2C BUS. 30 pin SDIP (Plastic) Features • Audio multiplexing decoder and dbx noise reduction decoder are all included in a single chip. Almost any sort of signal processing is possible through this IC. • All adjustments are possible through I2C BUS to Absolute Maximum Ratings (Ta=25°C) 11 • Supply voltage VCC • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 1.35 allow for automatic adjustment. • Various built-in filter circuits greatly reduce external parts. Range of Operating Supply Voltage 9 ± 0.5 V °C °C W V Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Standard I/O Level • Input level COMPIN (Pin 11) 245 mVrms • Output level LOUT (Pin 29) 490 mVrms ROUT (Pin 28) 490 mVrms Structure Bipolar silicon monolithic IC LOUT ROUT ITIME VCATC VCAWGT VCAIN VEOUT VETC VEWGT VE SAPIN SAPOUT GND NOISETC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCL DGND SAD VGR IREF MAININ MAINOUT PLINT STFIL COMPIN SAPTC SUBOUT STIN VCC NC 30 SDA Pin Configuration (Top View) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E94612B5Z-TE 26 25 24 23 22 21 20 14 19 18 1 2 3 4 6 RMSDET 5 SPECTRAL VGR SW LPF IREF "PONRES" LPF SAD I2 C BUS I/F AMP (+4dB) DGND IRE F "SAPLPF" RMSDET VCA SCL 27 SAPFDET HPF VE SDA ITIME STLPF STVCO SAPLPF SAPVCO SAPIND DeEm SAPOUT 12 "SAP" "NOISE" LPF LOGIC NRSW/FOMO/SAPC/M1 SAPIN SAPTC NOISE DET SAPVCO "SAPVCO" WIDEBAND STIN NOISETC 16 BPF SAPVDET +6dB LPF VE 17 STIND DeEm VEWGT GND ATT "STEREO" VCA MATRIX VETC 15 LPF LPF 1/2 7 VEOUT VCC VCA FLT 1/4 8 MAINOUT VCAIN 11 VCO STFIL LFLT 13 PLINT 9 MAININ VCAWGT —2— VCATC COMPIN "STLPF" STLPF SUBOUT 10 28 29 ROUT LOUT CXA1734S Block Diagram CXA1734S Pin Description Pin No. Symbol (Ta = 25°C, VCC = 9 V) Pin voltage Equivalent circuit VCC Description 7.5k ↓ 35µ 2.1V 4k ×2 1 SDA — 7.5k ×5 4.5k Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V 3k 1 VCC 7.5k ↓ 35µ 2.1V Serial clock input pin. VIH > 3.0 V VIL < 1.5 V 4k 2 SCL — ×4 19.5k 3k 2 3 DGND 3 — Digital block GND. VCC 2V 4 4 SAD Slave address control switch. The slave address is selected by changing the voltage applied to this pin. 40k — 80k 10k 3k 5 VGR 1.3V 11k 9.7k VCC 19.4k ×4 147 11k 5 2.06k —3— 1.3V 11k Band gap reference output pin. Connect a 10 µF capacitor between this pin and GND. CXA1734S Pin No. Symbol Pin voltage Equivalent circuit 40k 40k 30k Description 30k 15k ×2 VCC 6 IREF 1.3V 30p 1.8k 6 147 6.3k 30k Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 kΩ ±1%) resistor between this pin and GND.) 16k VCC 23k 23k ↓ 10µ VCC 7 MAININ 4.0V 147 Input the (L + R) signal from MAINOUT (Pin 8). 7 47k 4V VCC 15k ×4 VCC 8 MAINOUT 4.0V 147 (L + R) signal output pin. 8 ↓ 200µ 1k VCC 12k 12k 147 9 PLINT 9 6.3V 20k ↓ 26µ 20k 20k ↓ 50µ —4— 10k Pilot cancel circuit loop filter integrating pin. (Connect a 1 µF capacitor between this pin and GND.) CXA1734S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 3k 3k 150k 10 STFIL 5.3V 4k 4k 75k 10 Stereo block PLL loop filter integrating pin. 147 75k 12k 1k 1k VCC 50k 147 11 11 COMPIN 4.0V Audio multiplexing signal input pin. 20k 22k 3k 3V 4k 4k 4k 16k 24k VCC 8k 10 k 3k 12 SAPTC 4.5V 1k VCC 4k 50µ ↓ 12 Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.) Vcc 2k 2k 10P 4k 13 SUBOUT 500 4.0V 14.4k 2k 2k 2k 4k —5— 500 147 1k 13 (L - R) signal output pin. CXA1734S Pin No. Symbol Pin voltage Equivalent circuit 23k 14 STIN Description 23k Input the (L - R) signal from SUBOUT (Pin 13). 4.0V 11.7k 147 147 14 19 SAPIN 4.0V 19 47k 4V 15 VCC Input the (SAP) signal from SAPOUT (Pin 18). 47k 4V 20k — Supply voltage pin. 15 Vcc 8k 3.3k Set the time constant for 10k 1k 16 NOISETC 2k 4k ×2 3.0V Vcc 3k 4V 3k the noise detection circuit. (Connect a 4.7 µF capacitor and a 200 kΩ resistor between this pin and GND.) 16 17 GND 17 — Analog block GND. Vcc 5P 500 18 SAPOUT 500 4.0V SAP FM detector output pin. 7.4k 147 18 17k 24k 4k ↓ 10µ ↓ 50µ 4V 7.5k 20 VE 4.0V 147 20 —6— Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 kΩ resistor in series between this pin and GND.) CXA1734S Pin No. Symbol Pin voltage Equivalent circuit Description Vcc 2.9V 500 21 VEWGT 4.0V 4V 21 147 500 36k 8k 30k 4k ↓ 8µ ↓ 50µ Vcc 22 VETC 22 ×4 1.7V ×4 20k ↓ 50µ 4V ↓ 7.5µ Weight the variable deemphasis control effective value detection circuit. (Connect a 0.047 µF capacitor and a 3 kΩ resistor in series between this pin and GND.) Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. The specified restoration time constant can be obtained by connecting a 3.3 µF capacitor between this pin and GND. Vcc 5P 500 23 VEOUT 4.0V 23 10k 500 Variable de-emphasis output pin. (Connect a 4.7 µF nonpolar capacitor between Pins 23 and 24.) VCC 47k 24 VCAIN 4.0V 20k VCC 24 —7— 47k VCA input pin. Input the variable deemphasis output signal from Pin 23 via a coupling capacitor. CXA1734S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 40k 40k 3p Weight the VCA control effective value detection circuit. (Connect a 1 µF capacitor and a 3.9 kΩ resistor in series between this pin and GND.) 500 25 VCAWGT 4.0V 25 500 147 2.9V 36k ↓ 50µ 4k ↓ 8µ 30k 8k Determine the restoration time constant of the VCA control effective value detection circuit. The specified restoration time constant can be obtained by connecting a 10 µF capacitor between this pin and GND. VCC ×4 26 VCATC 26 ×4 1.7V ↓ 50µ 4k ↓ 7.5µ 20k VCC 40k 40k 30k 20k 40k 10k 2.6V 27 ITIME 1.3V 30p 1.8k 27 47k 147 25k ×4 —8— Set the reference current for the effective value detection timing current. The reference current is adjusted with the BUS DATA “SPECTRAL” based on the current which flows to this pin. The timing current determines the restoration time constant of the detection circuit and the variable de-emphasis characteristics. Connect a 43 kΩ (±1%) resistor between this pin and GND. CXA1734S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 3k 28 ROUT Right channel output pin. 500 4.0V 29 29 LOUT 30 NC 15k 28 500 3p Left channel output pin. — 30 —9— — —10— Vsub FCsub THDsub THDsmax SNsub PCsub THst HYst Sub output level Sub LPF frequency characteristics Sub distortion Sub overload distortion Sub S/N Sub pilot leak ST on level ST on/off hysteresis 8 9 10 11 12 13 14 15 SNmain Mono S/N 7 THDmmax 11 11 11 11 11 ST ST ST ST ST 11 ST 11 ST 11 11 Mono ST 11 Mono 11 Mono THDm 11 Mono FCmain Main overload distortion Main distortion 11 11 — Input Mono Mono Mode fH fH SUB 1k 100% NR-OFF SUB 12k 30% NR-OFF SUB 1k 100% NR-OFF SUB 1k 200% NR-OFF fH 0dB (49mVrms) fH 0dB (49mVrms) NO Signal MAIN 1k 100% Pre-em ON MAIN 5k 30% Pre-em ON MAIN 12k 30% Pre-em ON MAIN 1k 100% Pre-em ON MAIN 1k 200% Pre-em ON Input signal (Pre-Emphasis : OFF) (dbx-TV : OFF) FCdeem Vmain Icc Symbol =245mVrms =490mVrms =49mVrms =147mVrms 6 5 4 De-emphasis frequency characteristics Main LPF frequency characteristics Main output level 2 3 Current consumption Item Main (L+R) SUB (L-R) Pilot SAP Carrier 1 No. fH=15.734kHz COMPIN input level (100% modulation level) Electrical Characteristics — — 13 13 13 13 13 13 28 29 28 29 28 29 28 29 28 29 28 29 — Using 15 kHz LPF Using 15 kHz LPF Using 15 kHz LPF Using 15 kHz LPF Others 0dB=49mVrms 0dB=49mVrms Using fH BPF Compared with the TEST8 output level Using 15 kHz LPF Using 15 kHz LPF Using 15 kHz LPF Using 15 kHz LPF Compared with the TEST2 output level Conditions Output 3.5 –8.0 — 56 — — –3.0 150 61 — — –3.0 –1.2 440 22 Min. 6.0 –6.0 1.0 64 0.5 0.1 –0.5 190 69 0.15 0.1 –1.0 0 490 32 Typ. 8.5 –4.0 7.0 — 2.0 1.0 1.0 230 — 0.5 0.5 1.0 1.0 540 42 Max. dB mVrms dB % dB mVrms dB % dB mVrms mA Unit CXA1734S STsep1 STsep2 Vsap FCsap THDsap SNsap THsap HYsap ST separation 2 SAP output level SAP LPF frequency characteristics SAP distortion SAP S/N SAP on level SAP on/off hysteresis 17 18 19 20 21 22 23 Symbol ST separation 1 Item 16 No. 11 11 11 11 SAP SAP SAP 11 SAP SAP 11 ST 11 11 ST SAP Input Mode SAP Carrier SAP Carrier Input signal ST 300Hz 30%, NR-ON ST 3kHz 30%, NR-ON SAP 1k 100% NR-OFF SAP 10k 30% NR-OFF SAP 1k 100% NR-OFF SAP Carrier 147mVrms — — 18 18 18 18 Using 15kHz LPF Using 15kHz LPF Using 15kHz LPF Others L→R R→L L→R R→L 0dB=147mVrms 0dB=147mVrms Compared with the TEST18 output level Conditions Output 28 29 28 29 2.5 –12 46 — –3.0 150 23 23 Min. 4 –9 56 2.5 0 190 35 35 Typ. 5.5 –6.5 — 6.0 2.5 230 — — Max. dB % dB mVrms dB Unit CXA1734S —11— CXA1734S I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 1) during 3 mA inflow Max. inflow current Input capacitance Max. clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Min. data hold time Min. data preparation time Rise time Fall time Minimum waiting time for stop preparation I2C BUS load conditions: Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Min. 3.0 0 — — 0 3 — 0 4.7 4.0 4.7 4.0 4.7 0 250 — — 4.7 Typ. — — — — — — — — — — — — — — — — — Max. 5.0 1.5 10 10 0.4 — 10 100 — — — — — — — 1 300 — Unit V µA V mA pF kHz µs ns µs ns µs Pull-up resistor 4 kΩ (Connect to +5 V) Load capacity 200 pF (Connect to GND) I2C BUS Control Signal SDA tBUF tHD;STA tF tR SCL P S tHD;STA tLOW tHD;DAT tHIGH tSU;STA tSU;DAT —12— Sr tSU;STO P —13— 22 VETC 23 VEOUT 24 VCAIN 25 VCAWGT 26 VCATC 27 ITIME 28 ROUT 29 1 16 17 18 19 20 21 VEWGT LOUT NC SDA 220 R2 4.7µ 2 SCL 220 C1 4.7µ SAD 4 DGND 3 C2 DGND C3 5 R5 6 BUFF C5 3.9k C6 4.7µ 8 7 4.7µ C7 15kHz LPF fHBPF FILTERS MAININ 9 PLINT C9 R6 10 STFIL 0.22µ C13 11 COMPIN 0.047µ R7 R8 2700p 3k C12 12 GND AC V2 SIGNAL GENERATOR C14 SAPTC MEASURES 2.2k C11 R3 43k METAL ±1% 10µ VGR 10µ C4 TANTALUM 1µ R4 IREF 62k METAL ±1% MAINOUT TANTALUM 3.3µ C8 1µ C10 0.47µ S4 VE S3 SAPIN 4.7µ C18 S2 SAPOUT S1 GND 30 I2C BUS DATA R1 NOISETC 3.3k 4.7µ 4.7µ 13 4.7µ C17 14 SUBOUT C15 STIN 4.7µ 15 VCC C16 R9 200k C19 VCC 100µ A GND 9V V1 Electrical Characteristics Measurement Circuit CXA1734S CXA1734S I2C BUS Register Data Standard Setting Values Number of Classification bits 4 A 6 A 4 A 4 A 6 A 6 A 6 A 1 T 1 T 1 U 1 U 1 U 1 S 1 S Register ATT STVCO SAPVCO SAPLPF STLPF SPECTRAL WIDEBAND TEST-DA TEST1 NRSW FOMO M1 SAPC ATTSW Classification A: U: S: T: Standard setting 9 1F 8 8 1F 1F 1F 0 0 — — 1 — — Setting value when electrical characteristics are measured Contents Center point Adjustment point Normal mode According to the mode control table Mute OFF Fixed by the set specifications Adjustment User control Proper to set Test List of Adjustment Contents Adjustment Adjustment item data 1 MAIN VCA 2 ST VCO 3 SAP VCO 4 5 ST & dbx FILTER SAP FILTER Low frequency 6 ST separation High frequency ST separation ATT STVCO SAPVCO STLPF SAPLPF WIDEBAND SPECTRAL Input pin Input signal Measurement item Adjustment contents COMPIN 100Hz LOUT output Adjust as close to 490 (Pin 11) 245mVrms level None COMPIN (Pin 11) frequency STA7 5fH (78.67k) 147mVrms (SAPVCO1) STA8 (SAPVCO2) kHz as possible TEST-DA=1 Adjust to the center of the SAPVCO1 = 0, SAPVCO2 = 1 condition COMPIN 9.4kHz STA3 Adjust to the center of the (Pin 11) 600mVrms (STLPF) STLPF = 1 condition COMPIN 88kHz STA4 Adjust to the center of the (Pin 11) 120mVrms (SAPLPF) SAPLPF = 1 condition COMPIN ST-L 30% ROUT output (Pin 11) 300Hz level COMPIN ST-L 30% ROUT output (Pin 11) 3kHz level —14— setting mVrms as possible ROUT output Adjust as close to 62.936 None Test mode Minimize the output level Minimize the output level TEST1=1 TEST1=1 CXA1734S Adjustment Method 1 ATT adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2. Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the LOUT output level. Then, adjust the “ATT” data for ATT adjustment so that LOUT output goes to the standard value. 3. Adjustment range: ±30% Adjustment bits: 4 bits 2 Stereo VCO adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 1”. 2. Monitor the ROUT output (4 fH free run) frequency in a no input state, and adjust “STVCO” adjustment data so that this frequency is as close to 4fH (62.936 kHz) as possible. 3. Adjustment range: ±20% Adjustment bits: 6 bits 3 SAPVCO adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2. Input a 5fH (SAP carrier , 78.67 kHz) , 147 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA7, STA8) condition, adjust “SAPVCO” adjustment data. 3. Adjustment range: ±20% Adjustment bits: 4 bits Align SAPVCO with the center of the STA7 = 0 and STA8 = 1 (adjustment OK) condition range. Adjustment point 0 F 1 0 Measurement data STA7 "SAPVCO1" 1 0 4 Control data "SAPVCO" STA8 "SAPVCO2" Stereo block dbx filter adjustment 1. TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”. 2. Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA3) condition, adjust the “STLPF” adjustment data. 3. Adjustment range: ±20% Adjustment bits: 6 bits Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range. Adjustment point 3F 0 1 0 Control data "STLPF" Measurement data STA3 "STLPF" —15— CXA1734S 5 SAP block filter adjustment 1. TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”. 2. Input a 88 kHz, 120 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA4) condition, vary and adjust the “SAPLPF” adjustment data. 3. Adjustment range: ±20% Adjustment bits: 4 bits Align SAPLPF with the center of the STA4 = 1 (adjustment OK) condition range. Adjustment point 0 F 1 0 6 Control data "SAPLPF" Measurement data STA4 "SAPLPF" Separation adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2. Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300 Hz) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce ROUT output to the minimum. 3. Next, set the frequency only of the input signal to 3 kHz and adjust the “SPECTRAL” adjustment data to reduce ROUT output to the minimum. 4. Then, the adjustments in 2 and 3 above are performed to optimize the separation. 5. “WIDEBAND” “SPECTRAL” Adjustment range: ±30% Adjustment range: ±15% Adjustment bits: 6 bits Adjustment bits: 6 bits —16— CXA1734S Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1. PEAK DEV kHz 50 AM-DSB-SC 50 L-R dbx-TV NR L+R 50-15kHz PILOT 25 25 15 SAP dbx-TV NR FM 10kHz 50-10kHz 5 2fH fH 3fH 4fH TELEMETRY FM 3kHz 3 5fH 6fH f 6.5fH fH=15.734kHz Fig. 1. Base band spectrum I2C BUS DECODER MODE CONTROL 2fHL0° PLL (VCO 8fH) fHL0° DET MAIN LPF DE.EM STEREO LPF (COMPIN) 11 fHL90° PILOT MVCA (MAIN IN) (MAIN OUT) PILOT 7 8 CANCEL 4.7µ L+R SUB LPF L-R (DSB) WIDEBAND SUBVCA DET (SUBOUT) (ST IN) 13 MATRIX 14 L-R NR SW SAP(FM) SAP BPF DET INJ. SAP LPF A dbx-TV (R-OUT) B 28 BLOCK (SAP OUT) 18 LOCK (SAP IN) NOISE DET I2C BUS 4.7µ DECODER 19 MODE CONTROL I2C BUS DECODER MODE CONTROL SAP DET Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block) FIXED 14 NR SW A VARIABLE DEEMPHASIS DEEMPHASIS (VE OUT) (VCA IN) 23 24 4.7µ 19 HPF RMS DET LPF LPF RMS DET Fig. 3. dbx-TV block —17— (L-OUT) 29 4.7µ B VCA TO MATRIX CXA1734S (1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L - R (SUB) The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig.1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and freqency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 18 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25 kHz after FM detection. (5) dbx-TV block Either the SAP signal or L - R signal input respectively from ST IN (Pin 14) or SAP IN (Pin 19) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Others “MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. In addition, the input signal enters the decoder without passing through MVCA by setting to ATTSW = 1. The signals (L + R, L - R, SAP) input to “MATRIX” are selected according to the BUS data and whether there is ST or SAP discrimination, and any one of the ST-L, ST-R, MONO or SAP signals is output to LOUT and ROUT. “Bias” supplies the reference voltage and reference current to the other blocks. The currents flowing to the resistors connecting IREF (Pin 6) and ITIME (Pin 27) with GND become the reference current. —18— CXA1734S Register Specifications Slave address SAD pin GND VCC SLAVE RECEIVER 80H 8AH SLAVE TRANSMITTER 81H 8BH Register table SUB ADDRESS MSB LSB ∗∗∗∗0000 ∗∗∗∗0001 ∗∗∗∗0010 ∗∗∗∗0011 ∗∗∗∗0100 ∗∗∗∗0101 ∗∗∗∗0110 DATA BIT7 ∗ BIT6 ATTSW BIT5 TEST-DA BIT4 BIT3 BIT2 BIT1 BIT0 TEST1 ATT [4] INPUT LEVEL adj STVCO [6] STEREO VCO adj (SAPLPF [4] SAP FILTER adj) STLPF [6] ST FILTER adj SPECTRAL [6] WIDEBAND [6] NRSW FOMO SAPC M1 ∗ (SAPVCO [4] SAP VCO adj) ∗ ∗ ∗ ∗ ∗: Don't Care Status Register When TEST1 = 0 STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 POWER ON RESET STEREO SAP NOISE — — SAP VCO1 SAP VCO2 When TEST1 = 1 STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 POWER ON RESET STEREO STLPF SAPLPF — — — — —19— CXA1734S Description of Registers Control registers Number of bits 4 6 4 4 6 6 6 Classification∗ A A A A A A A TEST-DA 1 T TEST1 1 T NRSW 1 U FOMO 1 U M1 1 U SAPC 1 S ATTSW 1 S Register ATT STVCO SAPVCO SAPLPF STLPF SPECTRAL WIDEBAND ∗Classification U: A: S: T: Contents Input level adjustment STEREO VCO free running frequency adjustment SAP VCO free running frequency adjustment SAP filter adjustment STEREO and dbx filter adjustment Adjustment of stereo separation (3 kHz) Adjustment of stereo separation (300 Hz) Turn to DAC test mode and STVCO adjustment mode by means of TEST-DA = 1. Turn to test mode by means of TEST = 1. (Adjustment of STLPF and SAPLPF) Selection of the output signal (STEREO mode , SAP mode) Turn to forced MONO by means of FOMO = 1. (LOUT only is MONO during SAP output.) Selection of mute ON/OFF (0: mute ON, 1: mute OFF) Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Turns the input stage MVCA off when ATTSW = 1. User control Adjustment Proper to set Test Status registers Register PONRES STEREO SAP NOISE STLPF SAPLPF SAPVCO1 SAPVCO2 Number of bits 1 1 1 1 1 1 1 1 Contents POWER ON RESET detection; 1: RESET Stereo discrimination of the input signal; 1: Stereo SAP discrimination of the input signal; 1: SAP Noise level discrimination of the input signal mode; 1: Noise Status of STEREO filter adjustment; 1: OK range Status of SAP filter adjustment; 1: OK range Status 1 of SAP VCO free running frequency adjustment; 0: OK range Status 2 of SAP VCO free running frequency adjustment; 1: OK range —20— CXA1734S Description of Control Registers ATT (4): Adjust the signal level input to COMPIN (Pin 11) to the reference level (245 mVrms). Variable range of the input signal: 245 mVrms –5.0 dB to +3.0 dB 0 = Level min. F = Level max. STVCO (6): Adjust STEREO VCO free running frequency (f0). Variable range: f0 ±20% 0 = Free running frequency min. 3F = Free running frequency max. SAPVCO (4): Adjust SAPVCO free running frequency (f0). Variable range: f0 ±20% 0 = Free running frequency min. F = Free running frequency max. SAPLPF (4): Adjust the filter f0 of the SAP block. Variable range: f0 ±20% 0 = Frequency min. F = Frequency max. STLPF (6): Adjust the filter f0 of the ST and dbx blocks. Variable range: f0 ±20% 0 = Frequency min. 3F = Frequency max. SPECTRAL (6): Perform high frequency (fs = 3 kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6): Perform low frequency (fs = 300 Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST1 (1): Set filter adjustment mode. 0 = Normal mode 1 = STLPF (STA3) and SAPLPF (STA4) adjustment mode In addition, the following outputs are present at Pins 28 and 29. LOUT (Pin 29): SAP BPF OUT ROUT (Pin 28): NR BPF OUT TEST-DA (1): Set DAC output test mode and STVCO adjustment mode. 0 = Normal mode 1 = DAC output test mode and STVCO adjustment mode LOUT (Pin 29): DA control DC level ROUT (Pin 28): STEREO VCO oscillation frequency (4 fH) —21— CXA1734S NRSW (1) Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode FOMO (1): Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode SAPC (1): Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected ATTSW (1) MAIN VCA switch 0 = Normal mode 1 = MAIN VCA is passed. M1 (1) Mute the LOUT and ROUT output 0 = Mute ON 1 = Mute OFF —22— CXA1734S Description of Mode Control Priority ranking: TEST-DA > TEST1 > M1 > (NRSW & FOMO & SAPC) Mode control SAPC=0 “Select dbx input and LOUT & ROUT output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) SAPC=1 “Select dbx input and LOUT & ROUT output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) • During ST input: As on the left • During other input: NRSW FOMO SAPC M1 TEST1 TEST-DA LOUT : L, ROUT : R LOUT : L + R, ROUT : L + R NRSW = 1 (SAP output) NRSW = 1 (SAP output) • Regardless of the presence of SAP • When there is “SAP” during SAP discrimination, discrimination dbx input: “SAP” LOUT: SAP, ROUT: SAP LOUT: SAP, ROUT: SAP • When there is “No SAP”, output is the same However, when there is no SAP, SAPLPF as when NRSW = 0. output is soft muted (–7 dB) “Forced MONO” FOMO = 1 • During SAP output: LOUT: L + R, ROUT: SAP • During ST or MONO output: LOUT: L + R, ROUT: L + R Change the selection conditions for “MONO or ST output” and “SAP output”. SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. “MUTE” M1 = 0 Output is muted. “TEST1” TEST1 = 1 Return adjustment data with STATUS REGISTER as an adjustment mode. In addition, outputs are as follows. LOUT: SAP BPF OUT ROUT: NR BPF OUT “TEST-DA” TEST-DA = 1 Used to TEST of D/A. LOUT: D/A output ROUT: STVCO oscillation frequency (4 fH) —23— CXA1734S Mode Control No. 1 (SAPC = 1) Input signal mode 1) MONO 1) STEREO MONO & SAP STEREO & SAP Mode detection ST SAP NOISE 0 0 0 0 0 0 0 0 0 0 ∗ 1 0 ∗ 1 0 ∗ 1 1 0 ∗ 1 0 ∗ 1 1 1 1 1 1 1 0 0 1 0 0 1 ∗ 1 1 ∗ 1 0 1 ∗ 0 1 ∗ 0 1 0 0 1 0 0 1 1 0 1 1 1 1 ∗ 1 1 ∗ 1 1 0 1 1 0 1 1 1 1 1 1 Mode control NRSW FOMO SAPC 0 ∗ 1 1 0 1 1 1 1 0 ∗ 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch Rch L+R L+R SAP SAP L+R SAP L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) Note) (SAP) : The SAPOUT output signal is soft muted (approximately –7 dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. —24— CXA1734S Mode Control No. 2 (SAPC = 0) Input signal mode 1) MONO 1) STEREO MONO & SAP STEREO & SAP Mode detection ST SAP NOISE 0 0 ∗ 0 1 1 0 1 1 0 1 1 0 1 1 1 0 ∗ 1 0 ∗ 1 0 ∗ 1 0 ∗ 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Mode control NRSW FOMO SAPC ∗ ∗ 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE MUTE MUTE L-R MUTE SAP SAP L-R MUTE L-R MUTE Output Lch Rch L+R L+R L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R L R L+R L+R (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP L+R L+R L+R L+R L+R L+R L+R L+R L R L+R L+R SAP SAP L+R SAP L R L+R L+R L R L+R L+R Note) (SAP) : The SAPOUT output signal is soft muted (approximately –7 dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. —25— CXA1734S I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signal. SDA is a bidirectional signal. • Accordingly there are 3 values outputs, H, L and HIZ. H L HIZ L • I2C transfer begins with Start Condition and ends with Stop Condition. Start Condition S Stop Condition P SDA SCL • I2C data Write (Write from I2C controller to the IC) L during Write MSB SDA MSB LSB HIZ SCL 1 2 3 4 5 6 7 8 9 HIZ 1 8 9 S Address MSB ACK ACK LSB HIZ 1 8 HIZ 9 DATA(n) 1 ACK 8 8 9 9 DATA(n+1) HIZ ACK DATA(n+2) HIZ 1 8 9 P DATA Sub Address ACK DATA ACK —26— ∗ Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically. CXA1734S • I2C data Read (Read from the IC to I2C controller) H during Read HIZ SDA SCL 1 6 7 8 9 7 1 8 9 P S Address ACK DATA ACK • Read timing LSB MSB IC output SDA SCL 9 1 2 3 4 5 6 7 8 9 Read timing DATA ACK ∗ Data Read is performed during SCL rise. —27— ACK CXA1734S Input level vs. Distortion characteristics 1 (MONO) Input signal: MONO (Pre-emphasis on), 1 kHz 0dB=100% modulation LPF VCC=9V, 30kHz using LPF Measurement point: L/R out 10 Input signal: Stereo L=-R (dbx-TVNR ON), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF, ST mode Measurement point: L/R out Distortion (%) Distortion (%) 1.0 Input level vs. Distortion characteristics 2 (Stereo) 0.1 1.0 Standard level (100%) –10 0 Input level [dB] 10 Standard level (100%) –10 Input level vs. Distortion characteristics 3 (SAP) Distortion (%) 10 Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB=100% modulation level VCC=9V, 30kHz using LPF, SAP mode Measurement: L/R out 1.0 Standard level (100%) –10 0 Input level [dB] 10 —28— 0 Input level [dB] 10 CXA1734S Stereo LPF frequency characteristics 10 Gain (dB) 5 0 –5 –10 0 20 40 60 80 100 Frequency (kHz) Main LPF and Sub LPF frequency characteristics Gain (FC main and FC sub) (dB) 30 20 10 0 –10 –20 –30 –40 –50 1 2 5 10 7 20 50 70 100 Frequency (kHz) SAP frequency characteristics and group delay 100 20 90 5fH 70 60 50 0 40 30 –10 20 Group delay 3.8fH –20 20 40 60 6.2fH 80 Frequency (kHz) —29— 100 10 0 120 Group delay 10 Gain (dB) 80 Gain CXA1734S Unit : mm + 0.1 .05 0.25 – 0 30PIN SDIP (PLASTIC) + 0.4 26.9 – 0.1 10.16 + 0.3 8.5 – 0.1 16 30 0° to 15° 15 1 0.5 ± 0.1 + 0.4 3.7 – 0.1 0.5 MIN 1.778 3.0 MIN Package Outline 0.9 ± 0.15 PACKAGE STRUCTURE SONY CODE SDIP-30P-01 EIAJ CODE SDIP030-P-0400 JEDEC CODE MOLDING COMPOUND EPOXY / PHENOL RESIN LEAD TREATMENT SOLDER/PALLADIUM PLATING LEAD MATERIAL COPPER ALLOY PACKAGE WEIGHT 1.8g —30—