SONY CXA2104S

CXA2104S
US Audio Multiplexing Decoder
Description
The CXA2104S is an IC designed as a decoder for
the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction. Various kinds of
filters are built in while adjustment and mode control
are all executed through I2C BUS.
30 pin SDIP (Plastic)
Features
• Adjustment free of VCO and filter.
• Audio multiplexing decoder and dbx noise
reduction decoder are all included in a single chip.
Almost any sort of signal processing is possible
through this IC.
• All adjustments are possible through I2C BUS to
allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external
parts.
• There is an additional SAP output.
Standard I/O Level
• Input level
COMPIN (Pin 11)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
11
• Operating temperature Topr –20 to +75
• Storage temperature
Tstg –65 to +150
• Allowable power dissipation
PD
1.35
V
°C
°C
W
Range of Operating Supply Voltage
9 ± 0.5
V
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
100mVrms
245mVrms (Selected by INSW)
• Output level
TVOUT-L/R (Pins 2 and 1)
Structure
Bipolar silicon monolithic IC
490mVrms
∗ A license of the dbx-TV noise reduction system is
required for the use of this device.
SOUT
NC
VCAWGT
VCATC
VCAIN
VEOUT
VETC
VEWGT
VE
SAPIN
SAPOUT
NOISETC
STIN
SUBOUT
VCC
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TVOUT-R
TVOUT-L
SDA
SCL
DGND
MAININ
MAINOUT
PCINT1
PCINT2
PLINT
COMPIN
VGR
IREF
GND
SAPTC
Pin Configuration (Top View)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97726B96-PS
27
28
26
25
24
23
22
18
21
20
3
4
5
DGND
IREF
VGR
RMSDET
SCL
SPECTRAL
RMSDET
VCA
SDA
13
SW
LPF
HPF
VE
SAPOUT
12
"PONRES"
LPF
DeEm
LOGIC
NRSW/FOMO/SAPC
SAPIN
I2C BUS I/F
AMP
(+4dB)
WIDEBAND
STIN
IREF
SAPIND
"SAP"
"NOISE"
LPF
(+6dB)
LPF
VE
SAPTC 15
NOISE
DET
SAPVCO
DeEm
VCA
MATRIX
6
VEWGT
NOISETC 19
BPF
STIND
"STEREO"
LPF
1/2
7
VETC
GND 14
LPF
FLT
1/4
17
SUBOUT
VEOUT
VCC 16
ATT/INSW
VCA
VCO
PCINT1
LFLT
10
PCINT2
9
MAINOUT
VCAIN
COMPIN 11
STLPF
PLINT
8
MAININ
VCAWGT
–2–
VCATC
Block Diagram
LPF
TVOUT-R
TVOUT-L
30 SOUT
1
2
CXA2104S
CXA2104S
Pin Description
Pin
No.
Symbol
(Ta = 25°C, VCC = 9V)
Pin
voltage
Equivalent circuit
Description
VCC
3k
1
TVOUT-R
TVOUT right channel output
pin.
4.0V
580
1
580
2
2
TVOUT-L
TVOUT left channel output
pin.
4.0V
VCC
7.5k
↓ 35µ
2.1V
4k
×2
3
SDA
—
7.5k
×5
4.5k
Serial data I/O pin.
VIH > 3.0V
VIL < 1.5V
3k
3
VCC
7.5k
↓ 35µ
2.1V
4
SCL
4k
—
×4
10.5k
3k
Serial clock input pin.
VIH > 3.0V
VIL < 1.5V
4
5
DGND
5
—
Digital block GND.
VCC
10k
VCC
6
MAININ
Input the (L + R) signal from
MAINOUT (Pin 7).
4.0V
147
6
53k
4V
–3–
CXA2104S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
15k
×4
VCC
7
MAINOUT
4.0V
147
(L + R) signal output pin.
7
↓
200µ
1k
VCC
147
8
8
PCINT1
30k
4.0V
22k
Stereo block PLL loop filter
integrating pin.
VCC
147
9
9
PCINT2
10k
4.0V
10k
2k
×2
4k
VCC
20k
20k
147
10
PLINT
10
5.1V
20k
↓
26µ
20k
20k ↓
50µ
10k
–4–
Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)
CXA2104S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
24k
24k
14k
147
11
11
COMPIN
Audio multiplexing signal
input pin.
4.0V
34k
4V
24k
3k
12
VGR
1.3V
9.7k
11k
19.4k
×4
147
VCC
11k
11k
Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)
12
2.06k
VCC
40k
40k
30k
30k
15k
×2
Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based on
the current which flows to this
pin.
(Connect a 62kΩ (±1%)
resistor between this pin and
GND.)
VCC
13
IREF
1.3V
30p 1.8k
13
147
6.3k
14
GND
30k
16k
14
—
Analog block GND.
VCC
8k
10k
1k
3k
15
SAPTC
4.5V
VCC
4k
↓ 50µ
15
–5–
Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
CXA2104S
Pin
No.
Symbol
Pin
voltage
16
VCC
—
Equivalent circuit
Description
Supply voltage pin.
16
Vcc
2k
2k
10P
4k
580
17
SUBOUT
4.0V
(L–R) signal output pin.
17
14.4k
2k
2k
580 147
4k
2k
1k
VCC
18
STIN
23k
4.0V
Input the (L-R) signal from
SUBOUT (Pin 17).
23k
11.7k
147
147
18
21
SAPIN
4.0V
21
18k
Input the (SAP) signal from
SAPOUT (Pin 20).
18k
4V
4V
20k
Vcc
3.3k
8k
10k
1k
19
NOISETC
3.0V
2k
4k
×2
4V
Vcc
3k
200k
19
–6–
3k
Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
CXA2104S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
5P
580
20
SAPOUT
580
4.0V
SAP FM detector output pin.
10k
20
147
24k
↓ 10µ
4k
↓ 50µ
VCC
7.5k
22
VE
Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3kΩ resistor in series
between this pin and GND.)
147
4.0V
22
Vcc
2.9V
580
23
VEWGT
4.0V
4V
23
147
580
36k
8k
30k
↓ 8µ
Weight the variable
de-emphasis control effective
value detection circuit.
(Connect a 0.047µF capacitor
and a 3kΩ resistor in series
between this pin and GND.)
4k
↓ 50µ
Vcc
24
VETC
1.7V
×4
24
×4
20k
↓ 7.5µ
4k
↓ 50µ
–7–
Determine the restoration
time constant of the variable
de-rmphasis control effective
value detection circuit.
(the specified restoration time
constant can be obtained by
connecting a 3.3µF capacitor
between this pin and GND.)
CXA2104S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
5P
Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 25
and 26.)
580
25
VEOUT
25
4.0V
10k
580
VCC
47k
26
VCAIN
20k
4.0V
47k
VCA input pin.
Input the variable
de-emphasis output signal
from Pin 25 via a coupling
capacitor.
VCC
26
VCC
×4
27
VCATC
Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(the specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)
27
×4
1.7V
4k
↓
50µ
↓
7.5µ
20k
VCC
40k
40k 3p
580
28
VCAWGT
4.0V
28
2.9V
580 147
36k
↓
50µ
29
NC
—
4k↓
8µ
30k
Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)
8k
—
29
–8–
CXA2104S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
15k
×4
30
SOUT
4.0V
Additional SAP output pin.
30
↓
200µ
1k
–9–
– 10 –
FCdeem
FCmain
Vsub
FCsub
Main de-emphasis
frequency characteristic
Main LPF frequency
characteristic
Main distortion
Main overload distortion
Main S/N
Sub output level
Sub LPF frequency
characteristic
Sub distortion
Sub overload distortion
Sub S/N
ST → SAP
Crosstalk
3
4
5
6
7
8
9
10
11
12
13
CTst
SNsub
THDsmax
THDsub
SNmain
THDmmax
THDm
Vmain
Main output level
2
Icc
Signal
SAP
ST
ST
ST
ST
ST
MONO
MONO
MONO
MONO
MONO
MONO
Mode
11
11
11
11
11
11
11
11
11
11
11
11
—
Min.
15kLPF
1kBPF
20 log
('100%'/'0%')
20 log
('NRSW = 0'/
'NRSW = 1')
SUB (L-R) 1kHz,
100% mod., NR ON,
SAP Carrier (5fH)
15kLPF
SUB (L-R) 1kHz,
200% mod., NR OFF
SUB (L-R) 1kHz,
NR OFF
15kLPF
20 log
('12k'/'1k')
15kLPF
SUB (L-R) 1kHz,
100% mod., NR OFF
SUB (L-R) 12kHz,
30% mod., NR OFF
SUB (L-R) 1kHz,
100% mod., NR OFF
20 log
('100%'/'0%')
15kLPF
Mono 1kHz 200% mod.
Pre-em. ON
Mono 1kHz,
Pre-em. ON
1/2
15kLPF
Mono 1kHz 100% mod.
Pre-em. ON
2
17
17
17
17
17
1/2
1/2
1/2
1/2
Mono 12kHz 30% mod. 20 log
Pre-em. ON
('12k'/'1k')
Mono 5kHz 30% mod.
Pre-em. ON
60
56
–
–
–3.0
150
61
–
–
–3.0
–1.2
440
1/2
Output
pin
Mono 1kHz 100% mod.
Pre-em. ON
Filter
22
20 log
('5k'/'1k')
Measurement
conditions
= 60mVrms
= 20mVrms
= 200mVrms
= 100mVrms
INSW = 1
No signal
Input signal
= 147mVrms
SAP Carrier
Input pin
= 49mVrms
Pilot
Current consumption
Item
= 490mVrms
SUB (L – R) (dbx-TV: OFF)
fH = 15.734kHz
= 245mVrms
INSW = 0
Main (L + R)
(Pre-Emphasis: OFF)
1
No.
Electrical Characteristics
COMPIN input level
(100% modulation level)
70
64
0.2
0.1
–0.5
190
69
0.15
0.1
–1.0
0
490
32
Typ.
–
–
2.0
1.0
1.0
230
–
0.5
0.5
1.0
1.0
540
42
Max.
dB
dB
%
%
dB
mVrms
dB
%
%
dB
dB
mVrms
mA
Unit
(Ta = 25°C, VCC = 9V)
CXA2104S
Vsap
FCsap
THDsap
SNsap
CTsap
SAP output level
SAP LPF frequency
characteristic
SAP distortion
SAP S/N
SAP → ST
Cross talk
17
18
19
20
21
HYsap
STLsep1
STRsep1
STLsep2
STRsep2
SAP ON level
SAP ON/OFF hysteresis
ST separation 1 L → R
ST separation 1 R → L
ST separation 2 L → R
ST separation 2 R → L
22
23
24
25
26
27
THsap
SAP
HYst
Stereo ON/OFF
hysteresis
16
– 11 –
ST
ST
ST
ST
SAP
ST
11
11
11
11
11
11
15kLPF
15kLPF
15kLPF
15kLPF
ST-R 300Hz 30% mod.
NR ON
ST-L 3kHz 30% mod.
NR ON
ST-R 3kHz 30% mod.
NR ON
20 log (‘on
level’/’off level’)
0dB = 147mVrms
1kBPF
ST-L 300Hz 30% mod.
NR ON
Change
SAP Carrier (5fH)
Level
SAP 1kHz 100% mod. 20 log ('NRSW
= 1'/'NRSW = 0')
NR ON, Pilot (fH)
1/2
1/2
1/2
1/2
BUS
RETURN
2
20
SAP 1kHz, NR OFF
11
SAP
15kLPF
20
SAP 1kHz 100% mod.
NR OFF
11
SAP
20 log
('100%'/'0%')
20
BUS
RETURN
17
Output
pin
SAP 10kHz 30% mod. 20 log
('10k'/'1k')
NR OFF
20 log (‘on
level'/'off level')
15kLPF
fH BPF
0dB = 49mVrms
0dB = 49mVrms
Filter
Measurement
conditions
11
Change
PILOT (fH) Level
PILOT (fH) 0dB
Input signal
20
11
11
11
Input pin
SAP 1kHz 100% mod.
NR OFF
SAP
ST
THst
Stereo ON level
ST
PCsub
15
Mode
Signal
Sub pilot leak
Item
14
No.
23
23
23
23
2.0
–12.0
60
46
–
–3.0
150
35
35
35
35
4.0
–9.0
70
55
2.5
0
190
–
–
–
–
6.0
–6.5
–
–
6.0
2.5
230
10.0
–3.0
–6.0
–9.0
6.0
–30
–42
–
2.0
Max.
Typ.
Min.
dB
dB
dB
dB
dB
dB
dB
dB
%
dB
mVrms
dB
dB
dB
Unit
CXA2104S
TVOUT-L
2
TVOUT-R
1
SDA
DGND
I2C BUS DATA
4
SCL
3
R3
220
7
MAININ
6
C7
4.7µ
MAINOUT
DGND
5
C10
5600p
R6
1MEG
9
PCINT2
R4
C11
100k 0.012µ
8
10
C13
1µ
C16
10µ
12
V1
AC
SIGNAL
GENERATOR
GND
11
R8
62k
SOUT
R1
220
NC
C1
4.7µ
VCAWGT
GND
METAL
± 1%
14
VCATC
13
16
17
18
19
20
21
22
C18
4.7µ
23
C15
4.7µ
C17
4.7µ
24
C14
4.7µ
25
C3
4.7µ
R7
3.3k
VCAIN
C9
C12
0.047µ 2700P
R5
3k
26
C8
3.3µ
VEOUT
27
C6
4.7µ
MEASURES
VETC
28
C5
10µ
15kHz LPF
fH BPF
1kHz BPF
FILTERS
VEWGT
29
C4
1µ
R2
3.9k
BUFF
VE
TANTALUM
SAPIN
PCINT1
SAPOUT
PLINT
NOISETC
COMPIN
STIN
VGR
SUBOUT
IREF
– 12 –
GND
VCC
30
C2
4.7µ
S5
S4
S3
S2
S1
TANTALUM
Electrical Characteristics Measurement Circuit
SAPTC
15
C19
4.7µ
C20
100µ
GND
V2
9V
VCC
CXA2104S
CXA2104S
Adjustment Method (This is the case when standard input level is 245mVrms.)
1. ATT adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value
(490mVrms).
3) Adjustment range: ±30%
Adjustment bits:
4 bits
2.Separation adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz
NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUT-R output
to the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce TVOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
5) “WIDEBAND”
“SPECTRAL”
Adjustment range: ±30%
Adjustment range: ±15%
Adjustment bits:
6 bits
Adjustment bits: 6 bits
∗ Adjust this IC through Tuner and IF when this IC is mounted in the set.
– 13 –
CXA2104S
Description of Operation
The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz
50
AM-DSB-SC
50
L-R
dbx-TV
NR
25
PILOT
25
15
SAP
dbx-TV NR
FM 10kHz
50 – 10kHz
L+R
5
50 – 15kHz
2fH
fH
3fH
4fH
TELEMETRY
FM 3kHz
3
5fH
6fH
6.5fH
f
fH = 15.734kHz
Fig. 1. Base band spectrum
2
2fHL0°
fHL90°
fHL0°
PLL
(VCO 8fH)
STEREO LPF
(COMPIN)
11
I C BUS
DECODER
MODE
CONTROL
PILOT
DET
MAIN LPF DE.EM
(MAIN OUT)
PILOT
CANCEL
MVCA
(MAIN IN)
6
7
4.7µ
L+R
SUB LPF
L-R (DSB)
DET
WIDEBAND
SUBVCA
(SUBOUT) (ST IN)
L – R 4.7µ
SAP BPF
SAP (FM)
DET
SAP LPF
INJ.
LOCK
MATRIX
18
17
(Lch)
NR SW
A
(SAP OUT)
(SAP IN)
20
dbx-TV
BLOCK
B
21
4.7µ
NOISE
DET
SAP
DET
I 2C BUS
DECODER
LPF
(SOUT)
30
I 2C BUS
DECODER
MODE
CONTROL
MODE
CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(ST IN)
18
NR SW
A
FIXED
VARIABLE
DEEMPHASIS DEEMPHASIS
(VE OUT)
(VCA IN)
26
25
(SAP IN)
4.7µ
21
HPF
RMS
DET
LPF
LPF
RMS
DET
Fig 3. dbx-TV block
– 14 –
B
VCA
to
MATRIX
(Rch)
to
TVSW
CXA2104S
(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the
L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened
(de-emphasized) and input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 20 output is
soft muted.
(4) Mode discrimination
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.
(5) dbx-TV block
Either the L – R signal or SAP signal input respectively from ST IN (Pin 18) or SAP IN (Pin 21) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.
(6) Matrix
The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the mode control and whether there is ST / SAP discrimination.
(7) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 13) with GND become the reference current.
– 15 –
CXA2104S
Register Specifications
Slave address
SLAVE RECEIVER
SLAVE TRANSMITTER
84H (1000 0100)
85H (1000 0101)
Register table
DATA
SUB ADDRESS
MSB
LSB
BIT7
BIT6
BIT5
BIT4
BIT3
TEST-DA
TEST1
BIT2
BIT1
BIT0
∗∗∗∗0000
∗
∗∗∗∗0001
∗
SPECTRAL (6)
∗∗∗∗0010
∗
WIDEBAND (6)
∗∗∗∗0011
∗
DATA1
DATA2
NRSW
FOMO
SAPC
M1
∗∗∗∗0100
∗
INSW
DATA5
ATTSW
FST
DATA3
DATA4
ATT (4)
∗ : Don't Care
Status Registers
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SAP
NOISE
—
—
—
—
POWER
STEREO
ON RESET
– 16 –
CXA2104S
Description of Registers
Control registers
Number
of bits
Classification∗1
Standard
setting
ATT
4
A
9
SPECTRAL
6
A
1F
Adjustment of stereo separation (3kHz)
WIDEBAND
6
A
1F
Adjustment of stereo separation (300Hz)
TEST-DA
1
T
0
Turn to DAC test mode by means of TEST-DA = 1.
TEST1
1
T
0
Turn to test mode by means of TEST = 1.
FST
1
T
0
Turn to forced stereo by means of FST = 1.
NRSW
1
U
—
Selection of the output signal (Stereo mode, SAP mode)
FOMO
1
U
—
Turn to forced MONO by means of FOMO = 1.
(Left channel only is MONO during SAP output.)
M1
1
U
1
Selection of TVOUT mute ON/OFF
(0: mute ON, 1: mute OFF)
ATTSW
1
S
—
Turn the input stage MVCA off when ATTSW = 1.
INSW
1
S
—
Selection of standard input level
SAPC
1
S
—
Selection of SAP mode or L + R mode according to the
presence of SAP broadcasting
DATA1
1
T
0
DATA2
1
T
0
DATA3
1
T
0
DATA4
1
T
0
DATA5
1
T
0
Register
Contents
Input level adjustment
Test mode (Normal standard setting value)
∗1 Classification U: User control
A: Adjustment
S: Proper to set
T: Test
Status registers
Register
Number of bits
Contents
PONRES
1
POWER ON RESET detection;
1: RESET
STEREO
1
Stereo discrimination of the COMPIN input signal;
1: Stereo
SAP
1
SAP discrimination of the COMPIN input signal;
1: SAP
NOISE
1
Noise level discrimination of the SAP signal;
1: Noise
– 17 –
CXA2104S
Description of Control Registers
ATT (4):
Adjust the signal level input to COMPIN (Pin 11) to the standard input level.
Variable range of the input signal: standard input level –5.0dB to +3.0dB
0 = Level min.
F = Level max.
SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.
0 = Level max.
3F = Level min.
WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment.
0 = Level min.
3F = Level max.
TEST-DA (1): Set DAC output test mode.
0 = Normal mode
1 = DAC output test mode
In addition, the following output are present at Pin 2.
TVOUT-L (Pin 2): DA control DC level
TEST1 (1):
Monitor SAPBPF and NRBPF output
0 = Normal mode
1 = SAPBPF, NRBPF output
In addition, the following outputs are present at Pins 1 and 2.
TVOUT-L (Pin 2): SAP BPF OUT
TVOUT-R (Pin 1): NR BPF OUT
FST (1):
Select forced STEREO mode
0 = Normal mode
1 = Forced stereo mode
NRSW (1):
Select stereo mode or SAP mode
0 = Stereo mode
1 = SAP mode
– 18 –
CXA2104S
FOMO (1):
Select forced MONO mode
0 = Normal mode
1 = Forced MONO mode
M1 (1):
Mute the TVOUT-L and TVOUT-R output.
0 = Mute ON
1 = Mute OFF
ATTSW (1)
Select BYPASS SW of MVCA
0 = Normal mode
1 = MVCA is passed
INSW (1):
Select standard input level of COMPIN (Pin 11).
0 = 245mVrms
1 = 100mVrms
SAPC (1):
Select the SAP signal output mode
When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC.
0 = L + R output is selected
1 = SAP output is selected
– 19 –
CXA2104S
Description of Mode Control
Mode control
NRSW
SAPC = 0
SAPC = 1
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
• During ST input:
left channel: L,
right channel: R
• During other input: left channel: L + R,
right channel: L + R
As on the left
NRSW = 1 (SAP output)
• When there is “SAP” during SAP
discrimination
– left channel: SAP, right channel: SAP
• When there is “No SAP”, output is the
same as when NRSW = 0.
NRSW = 1 (SAP output)
• Regardless of the presence of SAP
discrimination,
dbx input: “SAP”
left channel: SAP, right channel: SAP
However, when there is no SAP, SAPOUT
output is soft muted (–7dB)
“Forced MONO”
FOMO
SAPC
M1
FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC = 0: Switch to SAP output when there is SAP discrimination.
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.
“MUTE”
M1 = 0: TVOUT output is muted.
– 20 –
CXA2104S
Decoder Output and Mode Control Table 1 (SAPC = 1)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
0
0
∗
1
MUTE
L+R
L+R
0
0
0
1
0
1
SAP
SAP
SAP
0
0
0
1
1
1
SAP
L+R
SAP
0
∗
1
0
∗
1
MUTE
L+R
L+R
0
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
0
∗
1
1
1
1
(SAP)
L+R
(SAP)
1
0
∗
0
0
1
L–R
L
R
1
0
∗
0
1
1
MUTE
L+R
L+R
1
1
1
0
0
1
L–R
L
R
1
1
1
0
1
1
MUTE
L+R
L+R
1
0
0
1
0
1
SAP
SAP
SAP
1
0
0
1
1
1
SAP
L+R
SAP
1
∗
1
1
0
1
(SAP)
(SAP)
(SAP)
1
∗
1
1
1
1
(SAP)
L+R
(SAP)
0
1
∗
0
0
1
MUTE
L+R
L+R
0
1
∗
0
1
1
MUTE
L+R
L+R
0
1
0
1
0
1
SAP
SAP
SAP
0
1
0
1
1
1
SAP
L+R
SAP
0
1
1
1
0
1
(SAP)
(SAP)
(SAP)
0
1
1
1
1
1
(SAP)
L+R
(SAP)
1
1
∗
0
0
1
L–R
L
R
1
1
∗
0
1
1
MUTE
L+R
L+R
1
1
0
1
0
1
SAP
SAP
SAP
1
1
0
1
1
1
SAP
L+R
SAP
1
1
1
1
0
1
(SAP)
(SAP)
(SAP)
1
1
1
1
1
1
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 21 –
CXA2104S
Decoder Output and Mode Control Table 2 (SAPC = 0)
MONO ∗1
STEREO ∗1
MONO & SAP
STEREO & SAP
Mode control
Mode detection
Output
ST
SAP
NOISE
NRSW
FOMO
SAPC
dbx
input
0
0
∗
∗
∗
0
MUTE
L+R
L+R
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
0
∗
0
0
0
L–R
L
R
1
0
∗
0
1
0
MUTE
L+R
L+R
1
0
∗
1
0
0
L–R
L
R
1
0
∗
1
1
0
MUTE
L+R
L+R
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
0
1
0
0
0
0
MUTE
L+R
L+R
0
1
0
0
1
0
MUTE
L+R
L+R
0
1
0
1
0
0
SAP
SAP
SAP
0
1
0
1
1
0
SAP
L+R
SAP
0
1
1
0
0
0
MUTE
L+R
L+R
0
1
1
0
1
0
MUTE
L+R
L+R
0
1
1
1
0
0
(SAP)
(SAP)
(SAP)
0
1
1
1
1
0
(SAP)
L+R
(SAP)
1
1
0
0
0
0
L–R
L
R
1
1
0
0
1
0
MUTE
L+R
L+R
1
1
0
1
0
0
SAP
SAP
SAP
1
1
0
1
1
0
SAP
L+R
SAP
1
1
1
0
0
0
L–R
L
R
1
1
1
0
1
0
MUTE
L+R
L+R
1
1
1
1
0
0
(SAP)
(SAP)
(SAP)
1
1
1
1
1
0
(SAP)
L+R
(SAP)
Input signal mode
Lch
Rch
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 22 –
CXA2104S
I2C BUS block items (SDA, SCL)
No.
Item
Symbol
Min.
Typ.
Max.
Unit
1
High level input voltage
VIH
3.0
—
5.0
2
Low level input voltage
VIL
0
—
1.5
3
High level input current
IIH
—
—
10
4
Low level input current
IIL
—
—
10
5
Low level output voltage SDA (Pin 3) during 3mA inflow
VOL
0
—
0.4
V
6
Maximum inflow current
IOL
3
—
—
mA
7
Input capacitance
CI
—
—
10
pF
8
Maximum clock frequency
fSCL
0
—
100
kHz
9
Minimum waiting time for data change
tBUF
4.7
—
—
10
Minimum waiting time for start of data transfer
tHD: STA
4.0
—
—
11
Low level clock pulse width
tLOW
4.7
—
—
12
High level clock pulse width
tHIGH
4.0
—
—
13
Minimum waiting time for start preparation
tSU: STA
4.7
—
—
14
Minimum data hold time
tHD: DAT
0
—
—
15
Minimum data preparation time
tSU: DAT
250
—
—
ns
16
Rise time
tR
—
—
1
µs
17
Fall time
tF
—
—
300
ns
18
Minimum waiting time for stop preparation
tSU: STO
4.7
—
—
µs
V
µA
µs
I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V)
Load capacity 200pF (Connect to GND)
I2C BUS Control Signal
SDA
tBUF
tF
tR
tHD: STA
SCL
P
S tHD: STA
tLOW
tHD: DAT
tHIGH
tSU: STA
tSU: DAT
– 23 –
Sr
tSU: STO
P
CXA2104S
I2C BUS Signal
There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.
• Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
– 24 –
CXA2104S
• I2C data Write (Write from I2C controller to the IC)
L during Write
MSB
MSB
LSB
HIZ
SDA
1
SCL
2
3
4
5
6
7
8
HIZ
9
1
8
9
S
Address
MSB
ACK
Sub Address
ACK
LSB
HIZ
1
8
HIZ
9
DATA (n)
1
ACK
8
DATA (n+1)
ACK
HIZ
8
9
DATA (n + 2)
HIZ
9
1
8
∗ Data can be transferred in 8-bit units to be
9
set as required.
Sub address is incremented automatically.
P
DATA
ACK
DATA
ACK
• I2C data Read (Read from the IC to I2C controller)
H during Read
HIZ
SDA
1
SCL
6
7
8
9
7
1
8
9
P
S
Address
ACK
DATA
ACK
• Read timing
MSB
LSB
IC output SDA
SCL
Read timing
9
1
2
3
4
DATA
ACK
∗ Data Read is performed during SCL rise.
– 25 –
5
6
7
8
9
ACK
CXA2104S
Input level vs. Distortion characteristics 2 (Stereo)
Input level vs. Distortion characteristics 1 (MONO)
10
Input signal: Stereo L = –R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF, ST mode
Measurement point: TVOUT-L/R
Distortion [%]
Distortion [%]
1.0
Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF
Measurement point: TVOUT-L/R
1.0
0.1
Standard level (100%)
–10
0
10
Standard level (100%)
Input level [dB]
–10
0
Input level [dB]
Input level vs. Distortion characteristics 3 (SAP)
Distortion [%]
10
Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: TVOUT-L/R
1.0
Standard level (100%)
–10
0
Input level [dB]
10
– 26 –
10
CXA2104S
Stereo LPF frequency characteristics
Main LPF and Sub LPF frequency characteristics
10
Gain (FC main and FC sub) [dB]
30
Gain [dB]
5
0
–5
20
10
0
–10
–20
–30
–40
–10
–50
0
20
40
60
80
1
100
2
Frequency [kHz]
5
7
10
20
50 70 100
Frequency [kHz]
SAP frequency characteristics and group delay
Additional SAP frequency characteristics
100
20
90
5fH
60
50
0
40
30
–10
20
Group delay
3.8fH
–20
20
40
60
80
6.2fH
100
Output level [mVrms]
Gain [dB]
70
Group delay [µs]
Gain
10
500
80
100% modulation
30% modulation
100
10% modulation
1% modulation
10
0
120
10
0.1
Frequency [kHz]
1.0
Frequency [kHz]
– 27 –
10
CXA2104S
Package Outline
Unit: mm
+ 0.1
.05
0.25 – 0
30PIN SDIP (PLASTIC)
+ 0.4
26.9 – 0.1
30
+ 0.3
8.5 – 0.1
10.16
16
0° to 15°
15
1
+ 0.4
3.7 – 0.1
0.5 MIN
1.778
0.5 ± 0.1
3.0 MIN
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
0.9 ± 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SONY CODE
SDIP-30P-01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
SDIP030-P-0400
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
1.8g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 28 –