CXA2054S US Audio Multiplexing Decoder Description The CXA2054S is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in while adjustment, mode control and sound processor control are all executed through I2C BUS. 48 pin SDIP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 11 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 2.2 Features • Audio multiplexing decoder, dbx noise reduction decoder and sound processor (surround, volume limiter, bass · treble, volume) are all included in a single chip. Almost any sort of signal processing is possible through this IC. • All adjustments are possible through I2C BUS to Structure Bipolar silicon monolithic IC • Output level TVOUT-L/R (Pins 44 and 43) LSOUT-L/R (Pins 7 and 6) SURROUT (Pin 5) 245 mVrms 490 mVrms 490 mVrms 490 mVrms 18 19 21 SUBOUT STIN NOISETC SAPIN SAPOUT 20 25 VCC 17 26 GND 16 27 SAPTC 15 28 VGR 14 29 IREF VE 30 COMPIN VETC VEWGT 31 PLINT VEOUT 32 PCINT2 VCAIN VCATC 33 PCINT1 13 34 MAINOUT 12 35 NC VLDC 11 VCAWGT 10 36 SAD 9 37 MAININ DGND 8 AUX1-R AUX1-L VLTC 38 SCL 39 AUX2-R 3 40 NC AUX2-L 2 41 SDA TVOUT-R SURRTC LSOUT-L BASSR1 7 TREL 6 BASSL1 5 BASSR2 LSOUT-R 42 TVOUT-L 43 SURRIN 44 4 1 490 mVrms 490 mVrms 490 mVrms ∗A license of the dbx-TV noise reduction system is required for the use this device. SURROUT 45 BASSL2 46 TRER 47 V Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Pin Configuration (Top View) 48 W Range of Operating Supply Voltage 9±0.5 allow for automatic adjustment. • Various built-in filter circuits greatly reduce external parts. • There are two channel external inputs for LSOUT outputs. • Automatic volume control between input sources is possible through volume limiter. Standard I/O Level • Input level COMPIN (Pin 19) AUX1-L/R (Pins 40 and 39) AUX2-L/R (Pins 42 and 41) SURRIN (Pin 4) V °C °C 22 23 24 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E96Y15B86-TE FILTER SW3 5 6 7 35 36 34 33 32 31 30 26 29 28 9 10 11 DGND 12 SAD 21 IREF VGR (L-R) 4 SURRIN 2 TRER 3 TREL 47 BASSR2 46 BASSR1 1 BASSL2 48 BASSL1 45 SURRTC 37 VLDC 38 VLTC 41 AUX2-R 42 AUX2-L 43 TVOUT-R 44 TVOUT-L SURRSW MATRIX SCL RMSDET SDA SPECTRAL SAPOUT 20 LPF VCA SAPIN “PONRES” LPF RMSDET VE SURROUND PREVOL STIN SW AMP (+4dB) HPF LOGIC NRSW/FOMO/SAPC FEXT2 VE I2C BUS I/F “SAP” DeEm WIDEBAND VOLLIM SW2 SW1 39 40 VEWGT IREF VCO SAPIND “NOISE” LPF LPF VCA MATRIX FEXT1 VETC SAPTC 23 NOISE DET SAPVCO (+6dB) DeEm LPF 1/2 13 VEOUT NOISETC 27 BPF STIND “STEREO” FLT 1/4 14 MAINOUT VCAIN GND 22 ATT LPF VCO SUBOUT 25 MAININ VCAWGT VCC 24 VCA PCINT1 LFLT PLINT 18 AUX1-L VCATC COMPIN 19 “FILTER” PCINT2 17 VL EXT1/EXT2/M1 SURR PR-VOL BASS TREBLE 16 BASS TREB VOL-L LSOUT-L M2 VOL-L VOL-R AUX1-R BASS TREB VOL-R LSOUT-R VOL-S SURROUT —2— VOL-SURR STLPF CXA2054S Block Diagram CXA2054S Pin Description Pin No. Symbol (Ta=25 °C, VCC=9 V) Pin voltage Equivalent circuit Description VCC 1 BASSL2 3k 4.0 V 1 580 47 48 BASSL1 13.2k 4.0 V 580 10.7k 8.57k 6.89k 47 BASSR2 4.0 V 5.66k VCC 4.44k 46 3.67k 46 BASSR1 48 15.3k 4.0 V 4V BASS filter pin. (Left channel) (Connect a 15 nF capacitor between Pins 1 and 48.) The cutoff frequency is determined by the built-in resistor and the external capacitance. BASS filter pin. (Right channel) (Connect a 15 nF capacitor between Pins 47 and 46.) The cutoff frequency is determined by the built-in resistor and the external capacitance. VCC 3k 2 TRER 4.0 V TREBLE filter pin. (Right channel) (Connect a 6.8 nF capacitor between this pin and GND.) 580 4.2k 580 3.42k 2.73k 2.2k 1.8k 1.42k 3 TREL 4.0 V TREBLE filter pin. (Left channel) (Connect a 6.8 nF capacitor between this pin and GND.) 1.17k VCC 4.88k 2 3 VCC 10k 4 27.5k 4 SURRIN 4.0 V Surround external input pin. 47k 4V 20k 20k —3— CXA2054S Pin No. Symbol Pin voltage 5 SURROUT 4.0 V Equivalent circuit Description VCC (L-R) signal output pin. VCC 580 6 LSOUT-R LSOUT right channel output pin. 5 4.0 V 580 6 7 7 LSOUT-L 4.0 V 8 NC — LSOUT left channel output pin. — 8 VCC 7.5k ↓ 35µ 2.1V 4k ×2 9 SDA — 7.5k 4.5k ×5 Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V 3k 9 VCC 7.5k ↓ 35µ 2.1V 4k 10 SCL — ×4 3k 10.5k Serial clock input pin. VIH > 3.0 V VIL < 1.5 V 10 11 DGND — 11 Digital block GND. —4— CXA2054S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 2V 12 SAD Slave address control switch. The slave address is selected by changing the voltage applied to this pin. 40k 12 — 80k 10k VCC 10k VCC 13 MAININ Input the (L+R) signal from MAINOUT (Pin 14). 4.0 V 147 13 53k 4V VCC 15k ×4 VCC 14 MAINOUT 4.0 V 147 (L+R) signal output pin. 14 ↓ 200µ 15 NC — 1k — 15 VCC 147 16 16 PCINT1 4.0 V 30k 22k Stereo block PLL loop filter integrating pin. VCC 147 17 17 PCINT2 4.0 V 10k 2k —5— 10k ×2 4k CXA2054S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 15k 15k Pilot cancel circuit loop filter integrating pin. (Connect a 1 µF capacitor between this pin and GND.) 147 18 PLINT 5.1 V 18 20k ↓ 26µ 20k 20k ↓ 50µ 10k VCC 50k 19 COMPIN 147 19 4.0 V 3k 4k 16k 3k 20 VGR 1.3 V Audio multiplexing signal input pin. 9.7k 19.4k ×4 147 VCC 11k 20 Band gap reference output pin. (Connect a 10 µF capacitor between this pin and GND.) 2.06k VCC 40k 40k 30k 30k VCC 21 IREF 1.3 V 30p 1.8k 21 147 16k —6— Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 kΩ (±1 %) resistor between this pin and GND.) CXA2054S Pin No. Symbol Pin voltage 22 GND — Equivalent circuit Description 22 Analog block GND. VCC 8k 10k 23 SAPTC Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.) 1k 3k VCC 4.5 V 4k ↓ 50µ 23 24 VCC — Supply voltage pin. 24 VCC 2k 2k 10P 4k 580 25 SUBOUT 25 4.0 V 2k 2k 2k 14.4k (L-R) signal output pin. 580 147 4k 1k VCC 26 STIN 23k 4.0 V Input the (L-R) signal from SUBOUT (Pin 25). 23k 11.7k 147 147 26 29 SAPIN 4.0 V 29 18k 18k 4V 20k —7— 4V Input the (SAP) signal from SAPOUT (Pin 28). CXA2054S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 8k 3.3k 10k 27 NOISETC 1k 3.0 V 2k 4k ×2 4V VCC 3k 200k 3k Set the time constant for the noise detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.) 27 VCC 5P 580 28 SAPOUT 580 4.0 V 10k SAP FM detector output pin. 28 147 24k ↓ 10µ 4k ↓ 50µ VCC 7.5k Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 kΩ resistor in series between this pin and GND.) 147 30 VE 30 4.0 V VCC 580 31 VEWGT 4.0 V 4V 2.9V 31 147 580 36k 8k —8— 30k ↓ 8µ 4k ↓ 50µ Weight the variable deemphasis control effective value detection circuit. (Connect a 0.047 µF capacitor and a 3 kΩ resistor in series between this pin and GND.) CXA2054S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 32 VETC 1.7 V 32 ×4 ×4 20k ↓ 7.5µ 4k ↓ 50µ Determine the restoration time constant of the variable deemphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3 µF capacitor between this pin and GND.) VCC 5P 580 33 VEOUT 4.0 V 33 10k 580 Variable de-emphasis output pin. (Connect a 4.7 µF non-polar capacitor between Pins 33 and 34.) VCC 47k 34 VCAIN 47k 20k 4.0 V VCC 34 VCC ×4 35 VCATC 35 ×4 1.7 V ↓ 50µ 4k ↓ 7.5µ 20k —9— VCA input pin. Input the variable deemphasis output signal from Pin 33 via a coupling capacitor. Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10 µF capacitor between this pin and GND.) CXA2054S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 40k 40k 3P 580 36 VCAWGT 36 4.0 V 2.9V 580 147 36k 4k ↓ 8µ ↓ 50µ 30k Weight the VCA control effective value detection circuit. (Connect a 1 µF capacitor and a 3.9 kΩ resistor in series between this pin and GND.) 8k VCC 3k Volume limiter detection circuit bias pin. (Connect a 1 MΩ resistor between pins 37 and 38.) 147 37 VLDC 0.7 V 37 VCC 200 38 VLTC Set the time constant for the volume limiter detection circuit. 200 38 147 100k 39 AUX1-R 4.0 V 100k VCC Right channel external input 1 pin. 10k 40 AUX1-L 4.0 V 39 27.5k 41 AUX2-R 4V 20k 42 AUX2-L 40 41 47k 4.0 V Left channel external input 1 pin. 42 Right channel external input 2 pin. 20k Left channel external input 2 pin. 4.0 V —10— CXA2054S Pin No. Symbol Pin voltage Equivalent circuit Description VCC 3k 43 TVOUT right channel output pin. TVOUT-R 4.0 V 580 43 580 44 44 147 TVOUT left channel output pin. TVOUT-L VCC 10k 20k 45 SURRTC 4.0 V 20k VCC 40k 580 24k 580 45 —11— Set the central frequency of the SURROUND circuit phase shifter. The frequency is determined by the built-in resistor and the external capacitance. (Connect a 0.022 µF capacitor between this pin and GND.) —12— 14 13 Sub pilot leak Cross talk ST → SAP 19 ST 19 ST SNsub Sub S/N 12 PCsub 19 ST THDsmax Sub overload distortion 11 19 19 ST THDsub Sub distortion 10 SAP 19 ST FCsub Sub LPF frequency characteristic 9 CTst 19 ST Vsub Sub output level 8 19 MONO SNmain Main S/N 7 19 MONO Main overload distortion 6 THDmmax Main distortion 5 19 19 MONO FCmain MONO 19 19 Input pin MONO MONO Mode FCdeem Vmain ICC Symbol Input signal =245 mVrms =490 mVrms =49 mVrms =147 mVrms =15.734 kHz PILOT (fH) 0 dB Mono 1 kHz 100 % mod. Pre-em. on Mono 5 kHz 30 % mod. Pre-em. on Mono 12 kHz 30 % mod. Pre-em.on Mono 1 kHz 100 % mod. Pre-em. on Mono 1 kHz 200 % mod. Pre-em off Mono 1 kHz, Pre-em on SUB (L-R), 1 kHz, 100 % mod., NR OFF SUB (L-R) 12 kHz, 30 % mod., NR OFF SUB (L-R) 1 kHz, 100 % mod., NR OFF SUB (L-R), 1 kHz, 200 % mod., NR OFF SUB (L-R) 1 kHz, NR OFF SUB (L-R) 1 kHz, 100 % mod., NR ON SAP Carrier (5 fH) No signal Main (L+R) (Pre-Emphasis : OFF) SUB (L–R) (dbX-TV : OFF) Pilot SAP Carrier fH THDm 4 Main de-emphasis frequency characteristic Main LPF frequency characteristic Main output level 2 3 Current consumption Item 1 No. COMP IN input level (100 % modulation level) Electrical Characteristics 20 log ('100 %'/'0 %') 20 log ('NRSW=0'/ 'NRSW=1') 20 log ('out'/'in') 20 log ('12 k'/'1 k') 20 log ('100 %'/'0 %') fH BPF 1 kBPF 15 kLPF 15 kLPF 15 kLPF 15 kLPF 15 kLPF 25 44 25 25 25 25 25 43/44 43/44 43/44 43/44 20 log ('12 k'/'1 k') 43/44 Output pin 43/44 15 kLPF Filter 20 log ('5 k'/'1 k') Measurement conditions — 60 56 — — –3.0 150 61 — — –3.0 –1.2 440 37 Min. –42 70 64 0.2 0.1 –0.5 190 69 0.15 0.1 –1.0 0 490 47 Typ. –30 — — 2.0 1.0 1.0 230 — 0.5 0.5 1.0 1.0 540 57 Max. dB dB dB % % dB mVrms dB % % dB dB mVrms mA Unit (Ta=25 °C, VCC=9 V) CXA2054S Stereo ON/OFF hysteresis 16 —13— STLsep1 STRsep1 STLsep2 STRsep2 ST separation 1 L → R ST separation 1 R → L ST separation 2 L → R ST separation 2 R → L TVOUT output level 28 29 30 31 32 Vtv HYsap SAP ON/OFF hysteresis 27 THsap SAP ON level CTsap Ndbx 26 Cross talk SAP → ST dbx out noise level 24 25 SAP soft mute 23 Smute SNsap SAP S/N 22 THDsap1 FCsap THDsap2 SAP distortion SAP LPF frequency characteristic Vsap2 Vsap1 HYst THst Symbol 21 20 19 18 SAP output level Stereo ON level 15 17 Item No. — SAP 19 39/40 EXT 19 19 19 19 ST ST ST ST SAP 19 19 SAP ST 19 19 19 19 19 Input pin SAP SAP SAP SAP ST Mode 20 log (‘on level’/’off level’) 0 dB=49 mVrms Measurement conditions 20 log ('100 %'/'0 %') 0 dB=147 mVrms 20 log (‘on level’/’off level’) ST-L 300 Hz 30 % mod. 20 log NR ON (‘Lch’/‘Rch’) ST-R 300 Hz 30 % mod. 20 log NR ON (‘Rch’/‘Lch’) ST-L 3 kHz 30 % mod. 20 log NR ON (‘Lch’/‘Rch’) ST-R 3 kHz 30 % mod. 20 log NR ON (‘Rch’/‘Lch’) Sine wave 1 kHz, 0 dB=490 mVrms 490 mVrms SAP Carrier (5 fH) Level Change SAP 1 kHz, 100 % mod. 20 log (‘NRSW=1’ NR ON, Pilot (fH) /‘NRSW=0’) No signal SAP 1 kHz, 100 % mod. NR OFF SAP 1 kHz, NR OFF SAP 1 kHz 100 % mod. NR OFF SAP 1 kHz 100 % mod. NR ON SAP 10 kHz, 30 % mod. 20 log NR OFF ('10 k'/'1 k') SAP 1 kHz 100 % mod. NR OFF SAP 1 kHz 100 % mod. NR ON Change PILOT (fH) Level Input signal 15 kLPF 15 kLPF 15 kLPF 15 kLPF 1 kBPF 15 kLPF 15 kLPF 15 kLPF 15 kLPF Filter 43/44 43/44 43/44 43/44 43/44 BUS RETURN 44 43/44 28 28 43/44 28 28 43/44 28 BUS RETURN Output pin –0.5 23 23 23 23 2.0 –12.0 60 — –8.5 46 — — –3.0 370 150 2.0 –9.0 Min. 0 35 35 35 35 4.0 –9.0 70 –75 –7.0 55 0.6 2.5 0 490 190 6.0 –6.0 Typ. 0.5 — — — — 6.0 –6.5 — –54 –5.5 — 1.5 6.0 2.5 610 230 10.0 –3.0 Max. dB dB dB dB dB dB dB dB dBm dB dB % % dB mVrms mVrms dB dB Unit CXA2054S TVOUT S/N TVOUT overload distortion 39 40 —14— MUls LSOUT muted amount LSOUT DC offset LSOUT distortion LSOUT S/N LSOUT overload distortion BASS maximum value BASS minimum value 44 45 46 47 48 49 50 TBmin TBmax THDlsmax SNls THDls OSls CTls2 LSOUT cross talk CTls1 EXT EXT EXT EXT 39/40 41/42 39/40 41/42 39/40 41/42 39/40 41/42 39/40 41/42 — INT EXT EXT 39/40 41/42 19 39/40 41/42 39/40 41/42 19 39/40 39/40 EXT EXT INT EXT INT Vls1 Vls2 EXT EXT 39/40 — INT EXT EXT 39/40 19 19 39/40 Input pin EXT INT EXT INT Mode THDtvmax SNtv THDtv OStv MUtv2 MUtv1 CTtv2 CTtv1 Symbol 43 42 LSOUT output level TVOUT distortion 38 41 TVOUT DC offset TVOUT muted amount TVOUT cross talk Item 37 36 35 34 33 No. Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 2 Vrms Sine wave 100 Hz, 245 mVrms Sine wave 100 Hz, 245 mVrms No signal Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms/No signal Sine wave 1 kHz, 2 Vrms MONO 1 kHz, 100 %, mod. Pre-em. on Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms MONO 1 kHz, 100 %, mod. Pre-em. on Sine wave 1 kHz, 490 mVrms No signal Sine wave 1 kHz, 490 mVrms MONO 1 kHz, 100 %, mod. Pre-em. on MONO 1 kHz, 100 %, mod. Pre-em. on Sine wave 1 kHz, 490 mVrms Input signal BASS="F" 0 dB=245 mVrms BASS="0" 0 dB=245 mVrms signal') 20 log ('490 mVrms'/'No when there is no signal Mute (M2=0)/DC difference 0 dB=490 mVrms 20 log (M2="0"/M2="1") 0 dB=490 mVrms INT → EXT 0 dB=490 mVrms EXT → INT 0 dB=490 mVrms 0 dB=490 mVrms signal') 20 log ('490 mVrms'/'No when there is no signal Mute (M1=0)/DC difference 0 dB=490 mVrms 20 log (M1="0"/M1="1") 0 dB=490 mVrms 20 log (M1="0"/M1="1") 0 dB=490 mVrms INT → EXT Measurement conditions 0 dB=490 mVrms EXT → INT 15 kLPF 15 kLPF 15 kLPF 1 kBPF 1 kBPF 15 kLPF 15 kLPF 15 kLPF 1 kBPF 1 kBPF Filter 6/7 6/7 6/7 6/7 6/7 6/7 6/7 6/7 6/7 6/7 43/44 43/44 43/44 43/44 43/44 43/44 43/44 43/44 Output pin –13 11 — 75 — –25 — — — –0.9 — 75 — –25 — — — — Min. –12 12 0.1 88 0.01 0 –90 –90 –75 0 0.1 88 0.01 0 –90 –85 –90 –75 Typ. –11 13 1.0 — 0.5 25 –75 –80 –60 0.9 1.0 — 0.5 25 –75 –70 –80 –60 Max. dB dB % dB % mV dB dB dB dB % dB % mV dB dB dB dB Unit CXA2054S Volume minimum value 53 Oltv Olls TVOUT overload leak LSOUT overload leak SURROUT 59 60 VL2 VL limit level 2 58 VL1 VL limit level 1 Sr2 Sr1 SVOLmin VOLmin TTmin TTmax Symbol 57 56 55 SURROUT volume minimum value SURROUND frequency characteristic 1 SURROUND frequency characteristic 2 TREBLE minimum value 52 54 TREBLE maximum value Item 51 No. INT INT EXT 19 19 39/40 41/42 39/40 41/42 40/42 EXT EXT 40/42 39/40 41/42 39/40 41/42 39/40 41/42 39/40 41/42 Input pin EXT EXT EXT EXT EXT Mode Sine wave 1 kHz, 9 Vp-p Sine wave 10 kHz, 245 mVrms Sine wave 10 kHz, 245 mVrms Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms Sine wave 330 Hz, 490 mVrms Sine wave 10 kHz, 490 mVrms Sine wave 1 kHz, 220 mVrms Sine wave 1 kHz, 1 Vrms Sine wave 1 kHz, 9 Vp-p Input signal 1 kBPF 1 kBPF M1=M2=“0” VOL-L=VOL-R= VOL-SURR=“0” 1 kBPF 1 kBPF Filter M1=M2=“0” VL=“1” VL=“1” 0 dB=490 mVrms VOL-SURR="0" 0 dB=490 mVrms SURR="1" 0 dB=490 mVrms SURR="1" 0 dB=490 mVrms VOL-L="0", VOL-R="0" Measurement conditions TREBLE="F" 0 dB=245 mVrms TREBLE="0" 0 dB=245 mVrms 5/6/7 43/44 6/7 6/7 7 7 5 6/7 6/7 6/7 Output pin — — 200 175 4.5 1.3 — — –13 11 Min. 0.04 0.04 250 220 6.0 3.0 –90 –90 –12 12 Typ. 0.2 0.2 300 265 7.5 4.6 –75 –75 –11 13 Max. mVrms mVrms mVrms mVrms dB dB dB dB dB dB Unit CXA2054S —15— CXA2054S I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 9) during 3 mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation I2C BUS load conditions : Min. 3.0 0 — — 0 3 — 0 4.7 4.0 4.7 4.0 4.7 0 250 — — 4.7 Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO Typ. — — — — — — — — — — — — — — — — — — Max. 5.0 1.5 10 10 0.4 — 10 100 — — — — — — — 1 300 — Unit V µA V mA pF kHz µs ns µs ns µs Pull-up resistor 4 kΩ (Connect to +5 V) Load capacity 200 pF (Connect to GND) I2C BUS Control Signal SDA tR tBUF tF tHD;STA SCL P S tHD;STA tLOW tHD;DAT tHIGH tSU;STA tSU;DAT —16— Sr tSU;STO P —17— C1 15n 44 TVOUT-L SURRTC BASSR1 BASSR2 BASSL1 C2 2 TRER 6.8n C4 3 TREL 6.8n C5 C6 4 4.7µ C8 5 GND 43 TVOUT-R 45 AC 42 AUX2-L 46 4.7µ C10 6 GENERATOR 41 AUX2-R 15n V1 SIGNAL 40 AUX1-L 47 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 AUX1-R C3 VLTC SURRIN SURROUT LSOUT-R 4.7µ C12 7 LSOUT-L 0.022µ 4.7µ C7 4.7µ C9 4.7µ 4.7µ 8 NC 9 10 I2C BUS DATA R1 220 R2 220 SDA SCL C11 4.7µ C13 4.7µ C14 4.7µ GND 12 11 1MEG C16 R3 DGND GENERATOR VLDC C15 4.7µ SAD AC VCAWGT AC VCATC 1µ 13 MAININ 4.7µ C18 14 MAINOUT AC VCAIN AC VEOUT R4 V5 SIGNAL VETC V4 VEWGT V3 VE V2 SAPIN SIGNAL GENERATOR SAPOUT C17 3.9k 10µ C19 15 TANTALUM S7 S6 S5 S4 S3 S2 S1 NC 100k 0.012µ 1MEG 17 3.3µ C23 BUFF 5600p C22 R5 C21 R6 16 4.7µ C20 PCINT1 PCINT2 TANTALUM C24 0.047µ R7 18 PLINT 1µ C26 GND AC 21 GENERATOR 20 4.7µ 22 MEASURES C29 V1 SIGNAL 19 3.3k C27 VGR IREF 15kHz LPF fHBPF 1kHz BPF C25 3k 2700P R8 COMPIN 4.7µ C28 10µ R9 62k METAL ±1% GND GND 23 SAPTC 4.7µ 24 4.7µ C32 VCC FILTERS NOISETC SIGNAL SIGNAL GENERATOR GENERATOR STIN 48 BASSL2 SUBOUT C30 C31 4.7µ C33 100µ VCC GND 9V V7 A Electrical Characteristics Measurement Circuit CXA2054S CXA2054S I2C BUS Register Data Standard Setting Values Number Classifi- Standard Setting value when electrical Contents of bit cation setting characteristics are measured ATT 4 A 9 VCO 6 A 1F FILTER 6 A 1F Center point Adjustment point SPECTRAL 6 A 1F WIDEBAND 6 A 1F TEST-DA 1 T 0 TEST1 1 T 0 Normal mode FST 1 T 0 PR-VOL 4 U F F=0 dB VOL-L 6 U 3F 3 F=0 dB VOL-R 6 U 3F 3 F=0 dB VOL-SURR 6 U 3F 3 F=0 dB TREBLE 4 U 8 7 or 8=0 dB BASS 4 U 8 7 or 8=0 dB NRSW 1 U — According to the modecontrol table FOMO 1 U — FEXT1 1 U 0 AUX1 forced MONO OFF FEXT2 1 U 0 AUX2 forced MONO OFF VL 1 U 0 VL OFF SURR 1 U 0 Surround OFF SURRSW 1 U 0 Internal mode selection EXT1 1 U 0 TV decoder output selection EXT2 1 U 0 M1 1 U 1 Mute OFF M2 1 U 1 ATTSW 1 S — Fixed by the set specifications SAPC 1 S — Register Classification A: U: S: T: Adjustment User control Proper to set Test —18— CXA2054S List of Adjustment Contents Adjustment Adjustment item data 1 MAIN VCA 2 3 ST & SAP VCO ST & SAP & dbx FILTER Low frequency 4 ST separation High frequency ST separation ATT VCO FILTER WIDEBAND SPECTRAL Input pin Input signal data COMPIN 100 Hz (Pin 19) None TVOUT-L 245 mVrms output level None COMPIN 9.4 kHz (Pin 19) Measurement TVOUT-R STA5 COMPIN ST-L 30 % TVOUT-R (Pin 19) output level COMPIN ST-L 30 % TVOUT-R (Pin 19) output level 3 kHz —19— Test mode setting Adjust as close to 490 mVrms as possible Adjust as close to output frequency 62.936 kHz as possible 600 mVrms (FILADJ) 300 Hz Adjustment contents Adjust to the center of the FILADJ=1 condition Minimize the output level Minimize the output level TEST-DA=1 TEST1=1 CXA2054S Adjustment Method (Adjust this through Tuner and IF when this IC is mounted on the set.) 1. ATT adjustment 1) TEST BIT is set to “TEST1=0” and “TEST-DA=0”. 2) Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value (490mVrms). 3) Adjustment range : ±30 % Adjustment bits : 4 bits 2. Stereo, SAP VCO adjustment 1) TEST BIT is set to “TEST1=0” and “TEST-DA=1”. 2) Monitor the TVOUT-R output (4 fH free running) frequency in a no input state, and adjust “VCO” adjustment data so that this frequency is as close to 4 fH (62.936 kHz) as possible. 3) Adjustment range : ±20 % Adjustment bits : 6 bits 3. Stereo, SAP, dbx filter adjustment 1) TEST BIT is set to “TEST1=1” and “TEST-DA=0”. 2) Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA5) condition, adjust the “FILTER” adjustment data. 3) Adjustment range : ±20 % Adjustment bits : 6 bits Align with the center of the STA5=1 (adjustment OK) condition range. Adjustment point 0 3F 1 0 Control data “FILTER” Measurement data STA5 “FILTER” 4. Separation adjustment 1) TEST BIT is set to “TEST1=0” and “TEST-DA=0”. 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30 %, frequency 300 Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3 kHz and adjust the “SPECTRAL” adjustment data to reduce TVOUT-R output to the minimum. 4) Then, the adjustments in 2 and 3 above are performed to optimize the separation. 5) “WIDEBAND” “SPECTRAL” Adjustment range : ±30 % Adjustment range: ±15 % Adjustment bits : 6 bits Adjustment bits: 6 bits —20— CXA2054S Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1. PEAK DEV kHz 50 AM-DSB-SC 50 L-R dbx-TV BR L+R 50-15KHZ PILOT 25 25 15 SAP dbx-TV NR FM 10kHz 50-10kHz 5 fH 2fH 3fH 4fH TELEMETRY FM 3kHz 3 5fH 6fH 6.5fH f fH=15.734kHz Fig. 1. Base band spectrum 2fHL0° fHL90° fHL0° PLL (VCO 8fH) STEREO LPF (COMPIN) 19 I2C BUS DECODER MODE CONTROL PILOT DET MAIN LPF DE.EM (MAIN OUT) (MAIN IN) 14 13 PILOT CANCEL MVCA L+R 4.7µ SUB LPF WIDEBAND (SUBOUT) (STIN) L-R (DSB) DET SUBVCA 25 (Lch) L–R 4.7µ SAP BPF SAP (FM) SAP LPF DET INJ. LOCK MATRIX 26 NR SW A B dbx-TV BLOCK (SAP OUT) 28 (SAP IN) NOISE DET I2C BUS DECODER 4.7µ 29 MODE CONTROL I2C BUS DECODER MODE CONTROL SAP DET Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block) (STIN) 26 NR SW A FIXED DEEMPHASIS VARIABLE DEEMPHASIS (VE OUT) (VCAIN) 33 4.7µ 29 (SAPIN) 34 HPF RMS DET LPF LPF RMS DET Fig 3. dbx-TV block —21— B VCA TO MATRIX (Rch) TO SW CXA2054S (TVOUT-L) (TVOUT-R) 44 43 (LSOUT-L) (AUX2-L) (AUX2-R) 41 7 VOL-L 40 (AUX1-L) BASS (LSOUT-R) TREBLE 40 SW1 SW2 VOLLIM PREVOL SURROUND VOL-R 6 39 (SURROUT) (AUX1-R) SW3 (Lch) (Rch) VOL-S 5 from MATRIX 4 (SURRIN) Fig. 4. Sound processor block (1) L+R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 19) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L-R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (deemphasized) and input to the matrix. (2) L-R (SUB) The L-R signal follows the same course as L+R before the pilot signal is canceled. L-R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L-R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L-R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5 fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 28 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5 fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25 kHz after FM detection of SAP signal. (5) dbx-TV block Either the SAP signal or L-R signal input respectively from ST IN (Pin 26) or SAP IN (Pin 29) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. —22— CXA2054S The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, SW1, SW2 The signals (L+R, L-R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the BUS data and whether there is ST/SAP discrimination. “SW1” switch the “MATRIX” output signal, external input signal (input to AUX1-L, R (Pins 40 and 39)) and external forced MONO. “SW2” switch the “SW1” output signal, external input signal (input to AUX2-L, R (Pins 42 and 41)) and external forced MONO. (7) Sound processor block The sound processor block contains “VOLUME LIMITER”, “PREVOL”, “BASS/TREBLE” tone control functions, “SURROUND” (quasi-surround function) and “VOLUME”. VL : 250 mVrms (limit level) BASS : ±12 dB (±1.7 dB/STEP at 100 Hz) TREBLE : ±12 dB (±1.7 dB/STEP at 10 kHz) VOLUME : 0 to –80 dB (–1.25 dB/STEP) • Prevolume “PREVOL” controls the input signal level of the sound processor block. When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using “PREVOL” so that the signal is not dissipated inside the processor. PR-VOL : 0 to –13.75 dB (–1.25 dB/STEP) • Surround At “SURROUND”, the L and R differential components are phase-shifted and these components are added to the left and right channels. When surround is OFF (SURR=0) Inputs are output as is. Lout=Lin Rout=Rin { When surround is ON (SURR=1) 1–jωRC Lout=Lin – (Lin-Rin) 1+jωRC 1–jωRC Rout=Rin + (Lin-Rin) 1+jωRC { R=24 kΩ (IC on-chip) { C=0.022 µF (Externally attached to Pin 45) (Lin, Lout) and (Rin, Rout) indicate the left- and right- channel I/O of the surround circuit. —23— CXA2054S (8) Others “MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 21) with GND become the reference current. Standard input and output levels Input pin Pin No. COMPIN 19 AUX1-L/AUX1-R 40/39 AUX2-L/AUX2-R 42/41 SURRIN 4 ∗1 ∗2 ∗3 ∗4 Input level 245 mVrms ∗1 490 mVrms 490 mVrms 490 mVrms TVOUT output level 490 mVrms ∗2 490 mVrms — — LSOUT output level ∗3 490 mVrms ∗2 490 mVrms 490 mVrms 490 mVrms ∗4 MONO, 25 kHz Deviation, Pre-Em. off MONO, 25 kHz Deviation, Pre-Em. on VOLUME MAX, PREVOL MAX, BASS & TREBLE CENTER, SURROUND OFF, VL OFF Only SURROUT output —24— CXA2054S Register Specifications Slave address SAD pin GND VCC SLAVE RECEIVER 80 H 8 AH SLAVE TRANSMITTER 81 H 8 BH Register table SUB ADDRESS MSB LSB ∗∗∗∗0000 ∗∗∗∗0001 ∗∗∗∗0010 ∗∗∗∗0011 ∗∗∗∗0100 ∗∗∗∗0101 ∗∗∗∗0110 ∗∗∗∗0111 ∗∗∗∗1000 ∗∗∗∗1001 ∗∗∗∗1010 ∗∗∗∗1011 ∗∗∗∗1100 DATA BIT7 BIT6 BIT5 TEST-DA ∗ ∗ ∗ ∗ ∗ ∗ EXT1 ∗ EXT2 ∗ ∗ ∗ ∗ VL ∗ ∗ BIT4 TEST1 BIT3 BIT2 ATT (4) BIT1 VCO (6) FILTER (6) SPECTRAL (6) WIDEBAND (6) M2 NRSW FOMO SAPC ATTSW SURRSW FST FEXT1 SURR PR-VOL (4) VOL-L (6) VOL-R (6) VOL-SURR (6) TREBLE (4) BASS (4) BIT0 M1 FEXT2 ∗ : Don’t care Status Registers When TEST1=0 STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 POWER ON RESET STEREO SAP NOISE — — — — STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 POWER ON RESET STEREO SAP NOISE FILADJ — — — When TEST1=1 —25— CXA2054S Description of Registers Control registers Register ATT Number of bits Classification∗ Contents 4 A Input level adjustment STEREO VCO and SAP VCO free running frequency VCO 6 A adjustment FILTER 6 A STEREO, SAP and dbx filter adjustment SPECTRAL 6 A Adjustment of stereo separation (3 kHz) WIDEBAND 6 A Adjustment of stereo separation (300 Hz) Turn to DAC test mode and STVCO adjustment mode by TEST-DA 1 T means of TEST-DA=1. Turn to test mode by means of TEST=1. TEST1 1 T (Adjustment of FILTER) FST 1 T Turn to forced stereo by means of FST=1. PR-VOL 4 U Input signal level control of sound processor block VOL-L 6 U LSOUT-L output signal level control VOL-R 6 U LSOUT-R output signal level control VOL-SURR 6 U SURROUT output signal level control TREBLE 4 U LSOUT output treble control BASS 4 U LSOUT output bass control NRSW 1 U Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO=1. FOMO 1 U (Left channel only is MONO during SAP output.) FEXT1 1 U External input 1 forced MONO (1 : forced MONO ON) FEXT2 1 U External input 2 forced MONO (1 : forced MONO ON) VL 1 U Selection of volume limiter function ON/OFF (0 : OFF, 1 : ON) SURR 1 U Selection of quasi-surround function ON/OFF (0 : OFF, 1 : ON) SURRSW 1 U Selection of internal or external mode for SURROUT output Selection of TV mode or external input mode for TVOUT EXT1 1 U output Selection of internal mode or external input mode for LSOUT EXT2 1 U output Selection of TVOUT mute ON/OFF M1 1 U (0 : mute ON, 1 : mute OFF) Selection of LSOUT mute ON/OFF M2 1 U (0 : mute ON, 1 : mute OFF) ATTSW 1 S Turn the input stage MVCA off when ATTSW=1. Selection of SAP mode or L+R mode according to the SAPC 1 S presence of SAP broadcasting ∗Classification U : U: S: T: User control Adjustment Proper to set Test —26— CXA2054S Status registers Register PONRES STEREO SAP NOISE FILADJ Number of bits 1 1 1 1 1 Contents POWER ON RESET detection; Stereo discrimination of the COMPIN input signal; SAP discrimination of the COMPIN input signal; Noise level discrimination of the SAP signal; Status of FILTER adjustment; 1 : RESET 1 : Stereo 1 : SAP 1 : Noise 1 : OK range Description of Control Registers ATT (4) : Adjust the signal level input to COMPIN (Pin 19) to the standard input level. Variable range of the input signal : 245 mVrms –5.0 dB to +3.0 dB 0 = Level min. F = Level max. VCO (6) : Adjust STEREO & SAP VCO free running frequency (fo). Variable range : fo ±20 % 0 = Free running frequency min. 3F = Free running frequency max. FILTER (6) : Adjust the filter fo of the ST, SAP and dbx blocks. Variable range : fo ±20 % 0 = Frequency min. 3F = Frequency max. SPECTRAL (6) : Perform high frequency (fs=3 kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6) : Perform low frequency (fs=300 Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST-DA (1) : Set DAC output test mode and VCO adjustment mode. 0 = Normal mode 1 = DAC output test mode and STVCO adjustment mode In addition, the following outputs are present at Pins 44 and 43. TVOUT-L (Pin 44) : DA control DC level TVOUT-R (Pin 43) : STEREO VCO oscillation frequency (4fH) TEST1 (1) : Set filter adjustment mode. 0 = Normal mode 1 = FILTER (STA5) adjustment mode In addition, the following outputs are present at Pins 44 and 43. TVOUT-L (Pin 44) : SAP BPF OUT TVOUT-R (Pin 43) : NR BPF OUT —27— CXA2054S FST (1) : Select forced STEREO mode 0 = Normal mode 1 = Forced stereo mode PR-VOL (4) : Input signal level control of sound processor block When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using “PR-VOL” so that the signal is not dissipated inside the processor. 4 = Volume Min. (–13.75 dB) F = Volume Max. (0 dB) –1.25 dB/STEP VOL-L (6) : LSOUT-L output signal level control 0 = Volume Min. (–80 dB) 3F = Volume Max. (0 dB) –1.25 dB/STEP VOL-R (6) : LSOUT-R output signal level control 0 = Volume Min. (–80 dB) 3F = Volume Max. (0 dB) –1.25 dB/STEP VOL-SURR (6) : SURROUT output signal level control 0 = Volume Min. (–80 dB) 3F = Volume Max. (0 dB) –1.25 dB/STEP TREBLE (4) : LSOUT output treble control 0 = Treble Min. 7 & 8 = Treble Center (0 dB) F = Treble Max. BASS (4) : LSOUT output bass control 0 = Bass Min. 7 & 8 = Bass Center (0 dB) F = Bass Max. NRSW (1) : Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode FOMO (1) : Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode —28— CXA2054S FEX1 (1) : Turn external input [1] to forced MONO. 0 = Normal mode 1 = External input [1] is forced MONO. Input the same signal to both AUX1-L and AUX1-R. FEX2 (1) : Turn external input [2] to forced MONO. 0 = Normal mode 1 = External input [2] is forced MONO. Input the same signal to both AUX2-L and AUX2-R. VL (1) : Volume limiter function selection 0 = Volume limiter OFF 1 = Volume limiter ON SURR (1) : Surround function selection 0 = Surround OFF 1 = Surround ON SURRSW (1) : Select INT mode or EXT mode for SURROUT output 0 = INT mode 1 = EXT mode EXT1 (1) : Select TV mode or external input mode for TVOUT output. 0 = TV mode 1 = External input mode EXT2 (1) : Select internal mode or external input mode for LSOUT output. 0 = internal mode 1 = External input mode M1 (1) : Mute the TVOUT-L and TVOUT-R output. 0 = Mute ON 1 = Mute OFF M2 (1) : Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF ATTSW (1) : Select BYPASS SW of Main VCA 0 = Normal mode 1 = Main VCA is passed SAPC (1) : Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L+R output is selected 1 = SAP output is selected —29— CXA2054S Description of Mode Control Priority ranking : M1/M2 > EXT1/EXT2 > TEST-DA > TEST1 > (NRSW & FOMO & SAPC) Mode control NRSW SAPC=0 “Select dbx input and TV decoder output” Conditions : FOMO = 0 NRSW=0 (MONO or ST output) SAPC=1 “Select dbx input and TV decoder output” Conditions : FOMO = 0 NRSW=0 (MONO or ST output) • During ST input : As on the left left channel: right channel: • During other input : left channel: right channel: L, R L+R, L+R NRSW=1 (SAP output) NRSW = 1 (SAP output) • When there is “SAP” during • Regardless of the presence of SAP SAPdiscrimination discrimination, dbx input : “SAP” –left channel : SAP, right channel : SAP left channel : SAP, right channel : SAP • When there is “No SAP”, output is the However, when there is no SAP, SAPOUT same as when NRSW=0. output is soft muted (–7 dB) “Forced MONO” FOMO SAPC M1/M2 EXT1/EXT2 TEST1 TEST-DA FOMO=1 • During SAP output: left channel : L+R, right channel : SAP • During ST or MONO output: left channel : L+R, right channel : L+R Change the selection conditions for “MONO or ST output” and “SAP output”. SAPC=0 : Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC=1 : Switch to SAP output regardless of whether there is SAP discrimination. “MUTE” M1=0 : TVOUT output is muted. M2=0 : LSOUT output is muted. “TV mode/external input mode selection” EXT1=0 : Set TVOUT output to TV mode. EXT1=1 : Set TVOUT output to external input [1] mode. EXT2=0 : Set LSOUT output to internal mode. EXT2=1 : Set LSOUT output to external input [2] mode. “TEST1” TEST1=1 Return adjustment data with STATUS REGISTER as an adjustment mode. In addition, outputs are as follows. left channel : SAP BPF OUT right channel : NR BPF OUT “TEST-DA” TEST-DA=1 Used to adjust the D/A TEST and STVCO. left channel : D/A output right channel : STVCO oscillation frequency (4fH) —30— CXA2054S Decoder Output and Mode Control Table 1 (SAPC=1) Input signal mode MONO 1) STEREO 1) MONO & SAP STEREO & SAP ST 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 Mode detection SAP NOISE 0 0 0 0 0 0 ∗ 1 ∗ 1 ∗ 1 0 ∗ 0 ∗ 1 1 1 1 0 0 0 0 ∗ 1 ∗ 1 1 ∗ 1 ∗ 1 0 1 0 1 1 1 1 1 ∗ 1 ∗ 1 0 1 0 1 1 1 1 Mode control NRSW FOMO SAPC 0 ∗ 1 1 0 1 1 1 1 0 ∗ 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 Note (SAP) : dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch Rch L+R L+R SAP SAP L+R SAP L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) The SAPOUT output signal is soft muted (approximately –7 dB). The signal is soft muted when NOISE=1. ∗ : Don’t care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. “NOISE” status rises earlier than “SAP” status when the amount of noise is increased to COMPIN. —31— CXA2054S Decoder Output and Mode Control Table 2 (SAPC=0) Input signal mode MONO 1) STEREO 1) MONO & SAP STEREO & SAP ST 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Mode detection SAP NOISE 0 ∗ 1 1 1 1 1 1 1 1 0 ∗ 0 ∗ 0 ∗ 0 ∗ 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 Mode control NRSW FOMO SAPC ∗ ∗ 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 Note (SAP) : dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L-R MUTE SAP SAP L-R MUTE (SAP) (SAP) Output Lch Rch L+R L+R L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R L R L+R L+R (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP L R L+R L+R SAP (SAP) L+R (SAP) The SAPOUT output signal is soft muted (approximately –7 dB). The signal is soft muted when NOISE=1. ∗ : Don’t care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. “NOISE” status rises earlier than “SAP” status when the amount of noise is increased to COMPIN. —32— CXA2054S Mode Control Table 3 EXT1 EXT2 FEXT1 FEXT2 0 0 * ∗ 1 0 0 ∗ 1 0 1 ∗ M1 1 1 1 M2 1 1 1 TV OUT-L TV-L AUX1-L AUX1-L Selected according to the EXT1, FEXT1 conditions Selected according to the EXT1, FEXT1 conditions TV OUT-R TV-R AUX1-R AUX1-L Selected according to the EXT1,FEXT1, conditions Selected according to the EXT1,FEXT1, conditions MUTE LS OUT-L TV-L AUX1-L AUX1-L LS OUT-R TV-R AUX1-R AUX1-L AUX2-L AUX2-R AUX2-L AUX2-L ∗ 1 ∗ 0 1 1 ∗ 1 ∗ 1 1 1 ∗ ∗ ∗ ∗ 0 1 MUTE ∗ ∗ ∗ ∗ 1 0 Selected according to Selected according to the EXT1, FEXT1 the EXT1,FEXT1, MUTE conditions conditions Selected according to Selected according to the EXT2, FEXT2, the EXT2, FEXT2, conditions conditions MUTE TV-L/TV-R are selected in Matrix. TV-L : MONO, ST-L, SAP (SAPBFout, D/A out) TV-R : MONO, ST-R, SAP (NRBPFout, STVCO free run (4fH)) I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. • Accordingly there are 3 values outputs, H, L and HIZ. H L HIZ L • I2C transfer begins with Start Condition and ends with Stop Condition. Start Condition S Stop Condition P SDA SCL —33— CXA2054S • I2C data Write (Write from I2C controller to the IC) L during Write MSB SDA HIZ MSB LSB 1 8 HIZ SCL 1 2 3 4 5 6 7 8 9 9 S Address MSB ACK Sub Address ACK LSB HIZ 1 8 HIZ 9 DATA (n) 1 ACK 8 DATA (n+1) ACK HIZ 8 DATA 9 DATA (n+2) HIZ 9 1 8 ACK ∗ Data can be transferred in 8-bit units to be set 9 DATA as required. P ACK Sub address is incremented automatically. • I2C data Read (Read from the IC to I2C controller) H during Read SDA HIZ SCL 1 6 S 7 8 9 Address 1 7 ACK 8 9 DATA ACK • Read timing MSB LSB IC output SDA SCL 9 1 2 3 4 5 6 7 8 9 Reat timing ACK DATA ∗ Data Read is performed during SCL rise. —34— ACK P CXA2054S Input level vs. Distortion characteristics 1 (MONO) Input signal : MONO (Pre-emphasis on), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF Measurement point : TVOUT-L/R 10 Input signal : Stereo L=–R (dbx-TVNR ON), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF, ST mode Measurement point : TVOUT-L/R Distortion (%) Distortion (%) 1.0 Input level vs. Distortion characteristics 2 (Stereo) 0.1 1.0 Standard level (100%) –10 0 Input level (dB) 10 Standard level (100%) –10 Input level vs. Distortion characteristics 3 (SAP) Distortion (%) 10 Input signal : SAP (dbx-TVNR ON) 1kHz, 0dB=100% modulation level VCC=9V, 30kHz using LPF, SAP mode Measurement point : TVOUT-L/R 1.0 Standard level (100%) –10 0 Input level (dB) 10 —35— 0 Input level (dB) 10 CXA2054S Stereo LPF frequency characteristics 10 Gain (dB) 5 0 –5 –10 0 20 40 60 80 100 Frequency (kHz) Main LPF and Sub LPF frequency characteristics Gain (FC main and FC sub) (dB) 30 20 10 0 –10 –20 –30 –40 –50 1 2 5 7 10 20 50 70 100 Frequency (kHz) SAP frequency characteristics and group delay 100 20 90 5fH 70 60 50 0 40 30 –10 20 Group delay –20 3.8 fH 20 40 60 80 Frequency (kHz) —36— 10 6.2fH 100 0 120 Group delay (µs) Gain (dB) 80 Gain 10 CXA2054S BASS - TREBLE characteristics BASS.MAX TREBLE.MAX +12 Boost amount (dB) +8 +4 0 –4 –8 –12 BASS. MIN TREBLE.MIN 20 100 1k Frequency (Hz) 10k 20k Input : AUXIN (Pins 40/39 and 42/41) 245 mVrms Output : LSOUT (PINS 5, 6 and 7) Volume characteristics 0 LSOUT output level (dB) –20 –40 –60 Input : AUXIN (Pins 40/39 and 42/41) 1kHz, 490mVrms Output : LSOUT (Pins 5, 6 and 7) –80 –100 0 F 1F 2F 3F Control data VOL-L, VCL-R, VOL-SURR Volume limiter characteristics 500 OUT (mVrms) 100 10 10–2 10–1 IN (Vrms) —37— 1 CXA2054S Package Outline Unit : mm + 0.1 5 0.0 0.25 – 48PIN SDIP (PLASTIC) + 0.4 43.2 – 0.1 25 15.24 + 0.3 13.0 – 0.1 48 1 0° to 15° 24 0.5 ± 0.1 0.9 ± 0.15 Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface. + 0.4 4.6 – 0.1 3.0 MIN 0.5 MIN 1.778 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-48P-02 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SDIP048-P-0600 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 5.1g JEDEC CODE —38—