SONY CXA2542AR

CXA2542AR
RF Signal Processing Servo Amplifier for CD Player
Description
The CXA2542AR is a bipolar IC developed for CD
player RF signal processing and servo control.
Features
• Automatic focus bias adjustment circuit
• Automatic tracking balance and gain adjustment
circuits
• RF level control circuit
• Interruption countermeasure circuit
• Anti-shock circuit
• Defect detection and prevention circuits
• RF I-V amplifier, RF amplifier
• APC circuit
• Focus and tracking error amplifier
• Focus, tracking and sled servo control circuits
• Focus OK circuit
• Mirror detection circuit
• Single power supply and dual power supplies
48 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
12
V
• Operating temperature Topr
–20 to +75 °C
• Storage temperature
Tstg
–65 to +150 °C
• Allowable power dissipation
PD
1400 mW
Recommended Operating Conditions
Operating supply voltage VCC – VEE 3.0 to 3.6 V
4.5 to 5.5 V
Applications
CD players
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98743-PS
CXA2542AR
CB
CC1
CC2
FOK
33
CP
RFTC
34
RF_I
LD
35
RF_O
PD
36
RF_M
PD1
Block Diagram
32
31
30
29
28
27
26
25
VCC
VCC
VEE
VCC
PD1 IV
AMP
VEE
VEE
VEE
RF SUMMING AMP
PD2 37
24 SENS2
VCC
PD2 IV
AMP
APC
VEE
LASER POWER CONTROL
F 38
IIL
↓
TTL
VCC
23 SENS1
F IV AMP
VCC
FE AMP
VCC
FO. BIAS
WINDOW COMP.
IFB6
IFB4
IFB5
IFB3
IFB1
E IV AMP
IFB2
E 39
22
VEE
C. OUT
VEE
BAL4
BAL2
BAL1
40
BAL3
INT
VEE
VEE
LEVEL S
TGFL
21 XRST
VEE
TOG3
IIL
↓
TTL
VCC
TOG4
TOG2
TOG1
VEE
MIRR
TEO 41
FOK
FOH
FOL
TGH
TGL
BALH
BALL
ATSC
TZC
FZC
ATSC 43
ATSC
WINDOW
COMP.
TZC 44
CC1
DFCT2
XDFCT1
MIRR
TGFL
LPCL
LDON
E-F BALANCE
WINDOW COMP.
LPFI 42
20
DATA
19
XLT
18
CLK
17
VCC
16
ISET
15
SL_O
14
SL_M
13
SL_P
TTL
↓
IIL
LPC
TRK. GAIN
WINDOW COMP.
IIL DATA REGISTER
INPUT SHIFT REGISTER
ADDRESS DECODER
SENS SELECTOR
OUTPUT DECODER
VCC
DFCT
TZC COMP.
TM1
DFCTO
TRACKING
PHASE COMPENSATION
TDFCT 45
IFB1-6
BAL1-4
TOG1-4
FS1-4
TG1-2
TM1-7
PS1-4
ISET
TG1
VCC
VCC
VCC
VC 46
TM4
TM6
VEE
VCC
FZC 47
TM7
VCC
FZC COMP.
FOCUS
PHASE COMPENSATION
FEO 48
TM3
FS1
TM5
VEE
VEE
FSET
FS2
DFCT
TG2
FS4
–2–
FDFCT
FGD
FLB
FE_O
FE_M
7
8
9
10
11
12
TA_O
6
TA_M
5
FSET
4
TG2
3
TGU
2
SRCH
1
FEI
VEE
TM2
CXA2542AR
Pin Description
Pin
No.
1
Symbol
FEI
I/O
Equivalent circuit
I
Description
Focus error input.
147
1
100k
147
2
FDFCT
I
3
FGD
I
2
3µ
Ground this pin through a capacitor
for cutting the focus servo highfrequency gain.
68k
147
Connects the capacitor for defect
time constant.
3
130k
4µ
40k
4
FLB
330k
External time constant setting pin
for boosting the focus servo lowfrequency.
4
I
470k
5
FE_O
O
12
TA_O
O
Focus drive output.
5
Tracking drive output.
12
15
15
SL_O
147
6
FE_M
Sled drive output.
250µ
O
I
90k
Focus amplifier inverted input.
6
50k
2µ
External time constant setting pin for
generating the focus search
waveform.
147
7
SRCH
I
7
20k
11µ
50k
–3–
CXA2542AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
110k
8
TGU
147 20k
I
External time constant setting pin for
switching the tracking high-frequency
gain.
423k
8
82k
9
TG2
External time constant setting pin for
switching the tracking high-frequency
gain.
9
I
470k
Peak frequency setting pin for focus
and tracking phase compensation
amplifier.
147k
10
FSET
I
10
15k
15k
100k
11
147
TA_M
I
Tracking amplifier inverted input.
11
11µ
13
SL_P
147
I
Sled amplifier non-inverted input.
13
2µ
147
14
SL_M
I
Sled amplifier inverted input.
14
22µ
16
ISET
I
Connect the external resistor to set
the current which determines the
Focus search, Track jump, and Sled
kick levels.
147
16
50µ
–4–
CXA2542AR
Pin
No.
Symbol
I/O
17
VCC
I
18
CLK
I
Equivalent circuit
Description
Positive power supply.
VCC
17
20µ
147
Serial data transfer clock input from
CPU. (no pull-up resistance)
1k
18
20
20
DATA
I
19
XLT
I
Serial data input from CPU.
(no pull-up resistance)
20µ
147
Latch input from CPU.
(no pull-up resistance)
4k
19
21
2.5p
21
XRST
I
Reset input; resets at Low.
(no pull-up resistance)
22
C. OUT
O
Track number count signal output.
23
SENS1
O
22
20k
Outputs FZC, DFCT1, TZC, BALH,
TGH, FOH, ATSC, and others
according to the command from CPU.
147
23
24
24
SENS2
100k
O
Outputs DFCT2, MIRR, BALL, TGL,
FOL, and others according to the
command from the CPU.
20k
147
25
FOK
O
40k
25
100k
–5–
Focus OK comparator output.
CXA2542AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
75k
26
CC2
147
I
39k
Input for the RF summing amplifier
output with capacitance coupled.
26
43k
147
28
CB
Connects the defect bottom hold
capacitor.
28
I
7.6k
240k
29
Connects the MIRR hold capacitor.
MIRR comparator non-inverted
input.
100k
29
CP
I
30
RF_I
I
31
RF_O
O
1.5k
Input for the RF summing amplifier
output with capacitance coupled.
RF summing amplifier output. Eyepattern check point.
147
30
147
31
32
RF_M
147
32
I
10k
10k
RF summing amplifier inverted
input.
The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.
27
147
27
CC1
O
33
RFTC
I
RF summing amplifier output.
Used for the defect capacitance
coupling.
147
50µ
External time constant setting pin
during RF level control.
33
50µ
10µ
–6–
CXA2542AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
10k
34
LD
1k
O
APC amplifier output.
34
20µ
8µ
35
PD
I
55k
147
35
APC amplifier input.
10k
10k 0.2p
8k
2k
36
37
PD1
PD2
I
I
RF I-V amplifier inverted input.
Connect these pins to the photo
diode A + C and B + D pins.
147
36
37
100µ
8.65k
12p
260k
38
39
F
E
I
I
147
38
39
500
F I-V and E I-V amplifier inverted
input.
Connect these pins to photo diodes
F and E pins.
10µ
40
VEE
—
40
VEE
–7–
Negative power supply.
CXA2542AR
Pin
No.
Symbol
41
TEO
I/O
Equivalent circuit
O
147
Description
Tracking error amplifier output.
E-F signal is output.
15k 32k 15k 6.6k 3k
41
150k
20k
150k
100k
45
TDFCT
I
Connects the capacitor for defect
time constant.
147
45
42
LPFI
3µ
Comparator input for balance
adjustment.
(Input from TEO through LPF)
147
I
42
7µ
1k
43
ATSC
I
100k
147
Window comparator input for ATSC
detection.
43
1k
100k
10µ
10µ
10µ
147
44
TZC
I
Tracking zero-cross comparator
input.
44
75k
–8–
CXA2542AR
Pin
No.
46
Symbol
VC
I/O
Equivalent circuit
120
50
O
Description
15k
(VCC + VEE)/2 DC voltage output.
46
120
VC
54k
147
47
FZC
I
7µ
47
Focus zero-cross comparator input.
6k
300k
10µ
25p
147
48
FEO
O
48
174k
10µ
300µ
–9–
Focus error amplifier output.
Connected internally to the window
comparator input for bias
adjustment.
CXA2542AR
Electrical Characteristics
(VCC = 1.5V, VEE = 1.5V, Topr = 25°C)
SD
Input
pin
Measurement pin
19 (OFF)
RST
17
Current
consumption 2
19 (OFF)
RST
Center amplifier
output offset
19 (OFF)
RST
TEST
Item
T1
Current
consumption 1
T2
T3
T4
SW conditions
(ON switches)
Min.
Typ.
Max.
Unit
17
12.0
18.5
25.0
mA
40
40
–25.0 –18.5 –12.0
mA
—
46
–100
0
100
mV
31
–70
–13
70
mV
RST
Offset
Measurement
conditions
RST
36
37
31
1kHz I/O ratio
16.5
19.5
22.5
dB
Max. output
10, 13
amplitude - High
RST
36
37
31
V2 = 0.2VDC
1.2
1.4
—
V
T7
Max. output
amplitude - Low
RST
36
37
31
V2 = 0.2VDC
—
–1.3
–1.0
V
T8
Offset
39F
48
1FB6: ON
–120
0
120
mV
T9
Voltage gain 1 10
39F
36
48
1kHz I/O ratio
15.6
18.6
21.6
dB
T10
Voltage gain 2 13
39F
37
48
1kHz I/O ratio
15.6
18.6
21.6
dB
T11
Voltage gain
difference
39F
–3
0
3
dB
T12
Max. output
13
voltage – High
39F
37
48
V2 = 100mVDC
1
1.4
—
V
T13
Max. output
voltage – Low
39F
36
48
V2 = 100mVDC
—
–1.3
–1
V
560
718
1042
mV
–29.0 –22.7 –16.5
mV
FE amplifier
T6
RF amplifier
10, 13
T5
Voltage gain
10, 13
10
BIAS0
3BF
48
IFB1, 2, 3, 4, 5, 6:
OFF
T15
BIAS1
3BE
48
IFB1: ON, BIAS0:
reference
T16
BIAS2
3BD
48
T17
BIAS3
3BB
48
T18
BIAS4
3B7
48
T19
BIAS5
3AF
48
T20
BIAS6
39F
48
T14
– 10 –
IFB2: ON, BIAS0: reference
Output gain difference with T15
IFB3: ON, BIAS0: reference
Output gain difference with V17
IFB4: ON, BIAS0: reference
Output gain difference with V18
IFB5: ON, BIAS0: reference
Output gain difference with V19
IFB6: ON, BIAS0: reference
Output gain difference with V20
5
6
7
dB
5
6
7
dB
5
6
7
dB
5
6
7
dB
5
6
7
dB
CXA2542AR
TEST
Item
SW conditions
(ON switches)
SD
Input
pin
Measurement pin
Measurement
conditions
48
Pin 1 voltage when SENS1
Min.
Typ.
Max.
Unit
5
20
35
mV
–35
–20
–5
mV
IFB6: ON
39F
FOL threshold
value
39F
T23
Offset
34F
308
38
39
41
TOG: OFF,
BAL1, 2, 3: ON
–25
0
25
mV
T24
GAIN UP (F)
14
36F
308
38
41
V1 = 2 kHz, I/O ratio
TOG: OFF, BAL1, 2, 3: ON
7.2
10.2
13.2
dB
T25
GAIN UP (E)
15
36F
308
39
41
V1 = 2 kHz, I/O ratio
TOG: OFF, BAL1, 2, 3: ON
7.2
10.2
13.2
dB
T26
Voltage gain
F0
14
34F
38
41
V1 = 2kHz, TOG: OFF
I/O ratio
1.2
4.2
7.2
dB
T27
Voltage gain
F1
14
34E
30F
38
41
V1 = 2kHz, TOG1: ON
Reference to F0
–2.3
–1.8
–1.3
dB
T28
Voltage gain
F2
14
34D
38
41
V1 = 2kHz, TOG2: ON
Reference to F0
–3.9
–3.4
–2.9
dB
T29
Voltage gain
F3
14
34B
38
41
V1 = 2kHz, TOG3: ON
Reference to F0
–6.9
–6.4
–5.9
dB
Voltage gain
F4
14
347
38
41
V1 = 2kHz, TOG4: ON
Reference to F0
–11.1 –10.6 –10.1
dB
T31
Voltage gain
E0
15
34F
30F
00
39
41
V1 = 2kHz, BAL: OFF
I/O ratio
–1.6
1.4
4.4
dB
T32
Voltage gain
E1
15
30E
39
41
V1 = 2kHz, BAL1: ON
Reference to E0
0.16
0.46
0.76
dB
T33
Voltage gain
E2
15
30D
39
41
V1 = 2kHz, BAL2: ON
Reference to E0
0.58
0.88
1.18
dB
T34
Voltage gain
E3
15
30B
39
41
V1 = 2kHz, BAL3: ON
Reference to E0
1.43
1.73
2.03
dB
T35
Voltage gain
E4
15
307
39
41
V1 = 2kHz, BAL4: ON
Reference to E0
2.96
3.26
3.56
dB
T36
Max. output
1
voltage – High
34F
308
38
41
V1 = 1VDC, TOG: OFF,
BAL1, 2, 3: ON
0.5
0.7
—
V
T37
Max. output
voltage – Low
34F
308
39
41
V1 = 1VDC, TOG: OFF,
BAL1, 2, 3: ON
—
–0.8
–0.5
V
T38
Output voltage
1
3C4
35
34
I1 = 364µA
–900 –704 –500
mV
T39
Output voltage
2
3C4
35
34
I1 = 439µA
–693 –293
107
mV
T40
Output voltage
3
3C4
35
34
I1 = 515µA
163
613
1063
mV
T41
Output voltage
9
4
3C4
35
34
0.8mA sink
–200
132
500
mV
T42
LD OFF
3C0
35
34
I1 = 515µA,
LD: OFF
1.1
1.3
—
V
TE amplifier
T30
APC
T22
FE amplifier
FOH threshold
value
T21
(Pin 23) goes from High to Low
IFB6: ON
48
Pin 1 voltage when SENS2
(Pin 24) goes from High to Low
1
– 11 –
CXA2542AR
SW conditions
(ON switches)
SD
Input
pin
Measurement pin
50% limit
8
3C7
35
30
34
30% limit
8
3C5
35
30
34
–50% limit
10, 13
3C7
T46
–30% limit
10, 13
3C5
T47
DC voltage
gain
1
T48
FCS total gain
T49
Feed through
1
T50
TEST
Item
T44
T45
RF level controll
T43
35
36
37
35
36
37
34
34
Measurement
conditions
I1 = 273µA
Output difference with LPC ON/OFF
I1 = 333µA
Output difference with LPC ON/OFF
I1 = 742µA
Output difference with LPC ON/OFF
I1 = 667µA
Output difference with LPC ON/OFF
Min.
Typ.
Max.
Unit
725
1330 1935
mV
315
915
1515
mV
–1421 –816 –211
mV
–1215 –615
–15
mV
17.4
20.9
24.4
dB
37.5
39.5
41.5
dB
—
—
–30
dB
123
150
177
mV
1
5
—
—
—
00
08
1
5
FZC threshold
20
value
00
47
47
Max. output
1
voltage – High
08
1
5
V1 = 200mVDC
1
1.3
—
V
T52
Max. output
voltage – Low
08
1
5
V1 = –200mVDC
—
–1.3
–1
V
T53
Search
voltage (–)
02
—
5
–721 –581 –441
mV
T54
Search
voltage (+)
03
—
5
399
539
679
mV
T55
DC voltage
gain
25
38
12
DC gain between
TEO and TA_O
11.4
14.6
17.8
dB
T56
TRK total gain
—
—
—
T26 + T55
16.8
18.8
20.8
dB
T57
Feed through
1
20
25
38
12
—
—
–39
dB
T58
Max. output
voltage – High
20
25
38
12
V1 = –0.3VDC
1
1.3
—
V
Max. output
voltage – Low
20
25
38
12
V1 = 0.3VDC
—
–1.3
–1
V
Jump output
voltage (–)
2C
12
–652 –512 –372
mV
T61
Jump output
voltage (+)
28
12
437
577
717
mV
T62
ATSC threshold
5, 17
value (–)
10
43
43
–25
–15
–7
mV
T63
ATSC threshold
5, 17
value (+)
10
43
43
7
15
25
mV
T64
TZC threshold
18
value
20
44
44
–20
0
20
mV
T59
T60
Tracking servo
T51
Focus servo
08
1
1
– 12 –
T9 + T47
I/O gain difference between
SD = 00 and SD = 08
Pin 47 voltage when SENS1
(Pin 23) goes from Low to High
I/O gain difference between
SD = 20 and SD = 25.
Input voltage when TG2
(Pin 9) goes from Vcc/2 to Vcc
Input voltage when TG2 (Pin 9)
goes from Vcc/2 to Vcc
Pin 44 voltage when
SENS1 (Pin 23) is 0V
CXA2542AR
SW conditions
(ON switches)
SD
Input
pin
Measurement pin
16
300
42
42
16
300
42
42
14
308
34F
38
41
14
308
34F
38
41
FOK
threshold value 8
—
30
25
Pin 30 voltage when
Pin 25 is 0V
T70
Voltage gain
6, 7
25
13
15
V1 = 100Hz, I/O ratio
T71
Feed through
6
20
25
13
15
T72
Max. output
voltage – High 6
25
13
15
Max. output
voltage – Low
25
13
TEST
Item
BAL COMP
T65
T67
Tracking servo
T66
threshold value – High
GAIN COMP
threshold value – High
FOK
threshold value – Low
Sled servo
T73
threshold value – Low
GAIN COMP
T68
T69
BAL COMP
6
Measurement
conditions
Pin 42 voltage when SENS1
(Pin 23) goes from High to Low
Pin 42 voltage when SENS2
(Pin 24) goes from High to Low
Pin 41 voltage when SENS1
(Pin 23) goes from High to Low
Pin 41 voltage when SENS2
(Pin 24) goes from Low to High
Min.
Typ.
Max.
Unit
5
20
35
mV
–35
–20
–5
mV
168
193
218
mV
127
145
163
mV
–560 –510 –450
mV
50
—
—
dB
—
—
–34
dB
V1 = 400mVDC
1
1.3
—
V
15
V1 = 400mVDC
—
–1.3
–1
V
I/O gain difference between
SD = 20 and SD = 25.
Kick voltage 1
20
—
15
REV × 1
–750 –600 –450
mV
T75
Kick voltage 2
20
—
15
FWD × 1
450
600
750
mV
T76
Max. operating
frequency 1
8
20
30
24
Measures at SENS2
pin.
30
—
—
kHz
8
20
30
24
Measures at SENS2
pin.
—
—
0.3
Vp-p
8
20
30
24
Measures at SENS2
pin.
1.8
—
—
Vp-p
T77
MIRROR
T74
Min. input
operating voltage 1
Max. input
T78
operating voltage 1
Min. operating
frequency 1
10, 11, 12,
13
10
36
37
23
Measures at SENS1
pin.
—
—
1
kHz
T80
Max. operating
frequency 1
10, 11, 12,
13
10
36
37
23
Measures at SENS1
pin.
2.5
—
—
kHz
Min. input
10, 11, 12,
13
10
36
37
23
Measures at SENS1
pin.
—
—
0.5
Vp-p
10, 11, 12,
13
10
36
37
23
Measures at SENS1
pin.
1.6
—
—
Vp-p
T81
T82
DEFECT
T79
operating voltage 1
Max. input
operating voltage 1
– 13 –
V1
S15
R1 390k
GND
DC
AC
GND
43 ATSC
42 LPFI
41 TEO
40 VEE
39 E
38 F
36
GND
S20
R3
10k
GND
S1
S2
3
S3
4
C4 R12
0.1µ 100k
R11
13k
7
6
5
GND
GND GND GND
C3
1000P
R9
47k
2
48 FEO
8
10
VCC
R16
510k
VCC
R15
10k
S5
9
12
13
R18
13k
GND
C8
0.01µ
SL_P
SL_M 14
SL_O 15
ISET 16
Vcc 17
CLK 18
XLT 19
DATA 20
XRST 21
C. OUT 22
SENS1 23
R17
100k
11
R19
10k
SENS2 24
25
26
27
28
29
C6 C7
0.01µ 0.01µ
30
R13
30k
S8
C9
0.068µ
31
1
47 FZC
44 TZC
C1 1000P
GND
45 TDFCT
S19
GND
46 VC
S18
S17
GND
GND
S16
R26 100k
C2 33µ
S14
S10
37 PD2
R7
34k
R2 390k
S13
R4
34k
GND
VEE
GND
GND
DC
AC
R14
10k
R8 R10
330 1M C5
1µ
S9
35
32
33
34
LD
FGD
I1
0µA
FEI
PD
FDFCT
RFTC
FLB
S11
TGU
S12
VCC
RF_M
TG2
V2
PD1
GND GND GND GND
RF_O
VCC VEE
I2
0.8mA
RF_I
VCC VEE
CP
FSET
R6 240k
CB
TA_M
R5
240k
CC1
FE_O
CC2
FE_M
FOK
SRCH
– 14 –
TA_O
Electrical Characteristics Measurement Circuit
GND
S6
S7
GND
C11 47µ
R24 5.1k
R25 13k
C10 33µ
R26 120k
R23
60k
VCC
VCC
GND
GND
VEE
VCC
CLK
XLT
DATA
XRST
VCC
AA
AA
AA
AA
R20 10k
R21 10k
R22 10k
CXA2542AR
CXA2542AR
Application Circuit 1 (±2.5V power supply)
Vcc
1µ
22
Vcc
1k
3.3µ
100µ
LD 10µH
PD
A
VEE VEE
VEE
C
100
500
MICRO
COMPUTER
DSP
0.033µ 0.01µ
1M 1µ
30k 0.01µ
0.068µ
33
32
31
30
29
28
27
26
RF_M
RF_O
RF_I
CP
CB
CC1
CC2
37 PD2
F
E
VEE
100k
150k
0.01µ
0.01µ
47k
470p
0.047µ
330k
25
FOK
34
LD
35
RFTC
36
PD
D
PD1
B
SENS2 24
38 F
SENS1 23
39 E
C. OUT 22
40 VEE
XRST 21
41 TEO
DATA 20
42 LPFI
XLT 19
43 ATSC
CLK 18
44 TZC
Vcc 17
Vcc
60k
45 TDFCT
0.022µ
VEE
ISET 16
0.1µ
10k
0.1µ
10k
7
8
9
10
11
4.7µ
100k
DRIVER
0.015µ
8.2k
13
3.3µ
12
22µ 15k
82k
100k
0.033µ
100k
510k
0.015µ
0.1µ
DRIVER
2200p
SL_P
TA_O
6
TA_M
TG2
5
0.1µ
4
FSET
2
3
680k
FE_O
FGD
FDFCT
FEI
1
TGU
SL_M 14
48 FEO
SRCH
47 FZC
0.022µ
FE_M
SL_O 15
FLB
46 VC
DRIVER
Vcc
Application Circuit 2 (Single +5V power supply)
Vcc
1µ
22
Vcc
1k
3.3µ
100µ
LD 10µH
PD
A
C
500
100
1M 1µ
MICRO
COMPUTER
DSP
0.033µ 0.01µ
30k 0.01µ
0.068µ
E
100k
32
31
30
29
28
27
26
RF_O
RF_I
CP
CB
CC1
CC2
25
FOK
33
RF_M
37 PD2
F
34
LD
35
RFTC
36
PD
D
PD1
B
SENS2 24
38 F
SENS1 23
39 E
C. OUT 22
40 VEE
XRST 21
41 TEO
DATA 20
42 LPFI
XLT 19
43 ATSC
CLK 18
44 TZC
Vcc 17
150k
0.01µ
0.01µ
0.047µ
330k
47k
470p
Vcc
60k
0.1µ
0.022µ
Vcc
10µ
45 TDFCT
ISET 16
46 VC
SL_O 15
47 FZC
SL_M 14
100k
10k
2200p
0.1µ
TA_M
8
9
10
11
4.7µ
100k
DRIVER
510k
0.033µ
SL_P
TA_O
7
FSET
6
TGU
FE_O
5
0.1µ
TG2
4
SRCH
2
3
0.1µ 680k
FE_M
1
10k
FLB
FEI
48 FEO
FGD
0.022µ
FDFCT
10µ
8.2k
13
3.3µ
12
100k
DRIVER
0.015µ
82k
22µ 15k
0.015µ
Vcc
DRIVER
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 15 –
CXA2542AR
Description of Functions
RF Amplifier
The photodiode currents input to the input pins (PD1 and PD2) are each I-V converted through a 58kΩ
equivalent resistor by the PD I-V amplifiers. These signals are added by the RF summing amplifier, and the
photodiode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check
can be performed at this pin.
1k
30k
3.3µ
RF_O
RF_M
32
A
31
58k
C
PD1
VA
36
10k
iPD1→
FOK
DEFECT
V1
PD1 IV AMP
B
D
VC
RF SUMMING AMP
58k
V3
PD2
VB
37
10k
iPD2→
V2
PD2 IV AMP
VC
The low frequency component of the RFO output voltage is
VRFO = –
30k
(VA + VB – 2V3) + V3
10k
= –3 {–58kΩ (iPD1 + iPD2) + V1 + V2 – 2V3} + V3, and
the setting is V1 = V2 = V3, then
VRFO = 174kΩ × (iPD1 + iPD2) + V3
– 16 –
CXA2542AR
Focus Error Amplifier
R3
58k
R7
174k
RF
V2
VB
PD2 37
R5
32k
48
B+D
FEO
PD2 IV AMP
R10
10k
FE AMP
R2
58k
VC
RF
V1
VA
PD1 36
1
R4
32k
R9
10k
A+C
PD1 IV AMP
R6
174k
VC
VCC
×1 ×2
6
×8 ×16 ×32
FOCUS
PHASE
COMPENSATION
IFB5
GND
FE_M
R11
100k
R8
100k
FE_O
5
DRIVER
IFB6
IFB3
IFB4
IFB2
VC
IFB1
C1
2200p
GND
R1
16k
×4
FEI
×32
VIN > VH L
VIN < VH H
25mV/STEP
VH
RESET : IFB1 to IFB6 ON
VC
FOH
23 SENS1
VEE
20mV
SENS
SELECTOR
VIN
VC
FOL
24 SENS2
VL
VIN > VL H
VIN < VL L
–20mV
VC
The focus error amplifier calculates the difference between outputs VA and VB of the RF I-V amplifier, and
outputs current-voltage converted voltage of the photodiode (A + C – B – D).
The FEO output voltage:
VFEO =
=
174kΩ
(VA – VB)
32kΩ
174kΩ
{(–58kΩ × iPD1) – (–58kΩ × iPD2)}
32kΩ
= 315.4kΩ (iPD2 – iPD1)
The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment.
The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and
OFF.
The 6-bit focus bias adjustment switches are controlled with commands.
IFB1 to IFB6 are all ON after a reset.
The voltage is varied by approximately 25mV per step.
– 17 –
CXA2542AR
• Focus error amplifier offset adjustment (when adjusting the IC offset)
The offset adjustment is performed by comparing the FEO when the focus servo is OFF with the reference
level.
The FEO and reference level are compared by the window comparator, and the comparison results are output
from SENS1 and SENS2. (ADDRESS D11001110D6)
Adjust the offset so that SENS1 and SENS2 are both High.
Set the reference level to the center ±20mV.
25mV
<
40mV
<
50mV
Reference level width
Variable voltage per step Variable voltage per 2 steps
• Focus bias fine adjustment
Fine adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF while
monitoring a DSP jitter meter with the microcomputer.
The 6-bit focus bias adjustment switches are controlled with commands.
– 18 –
CXA2542AR
Tracking Error Amplifier
R23
100k
R24
150k
C3
0.01µ
C4
0.01µ
GND
TEO
GND
R5
13k
R16
NORMAL
96k
R14
13k
TGFL
R9
R3
26k
R4
6.8k
TGFL
NORMAL
R12
96k
C1
12p
E 39
R13
13k
V
VL
–
+
VC
TOG4
R1
260k
R8
17k
TOG1
VC
F I-V AMP
VIN > VL H
–20mV VIN < VL L SENS
VIN > VH L SELECTOR
VIN < VH H
VH
TGH
200mV
VC
VC
SENS2
CPU
TGL
R6
75k
R7
BAL1 110k
R10
BAL2 56k
R11
BAL3 27k
R15
BAL4 13k
VC
E I-V AMP
24
VIN
VE
VC
SENS1
BALL
R18
15k
GAIN UP
GAIN UP
TOG3
VF
23
VIN
17k
VC
F 38
BALH
20mV
VC
TOG2
C2
12p
VIN > VH L
VIN < VH H
VH
TE AMP
R17
20k
R19
32k
R20
15k
R21
6.6k
R22
3k
R2
260k
LPFI
42
41
VL
150mV
RE
VIN > VL H
VIN < VL L
VC
21
COMAND
COMAND
CONTROL
CONTROL
VC
20
19
18
XRST
DATA
XLT
CLK
The difference between E I-V amplifier output VE and F I-V amplifier output VF is taken and output from TEO.
The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based
automatic adjustment.
The balance adjustment is performed by varying the combined resistance value of the T-configured feedback
resistance at the E I-V amplifier.
E I-V AMP feedback resistance = R1 + R4 + R1 × R4
RE
F I-V AMP feedback resistance = R2 + R5 + R2 × R5 = 403kΩ
R3
Vary the combined resistance value of the E I-V amplifier's feedback resistance by using the balance
adjustment switches (BAL1 to BAL4).
The gain adjustment is performed by resistance dividing the TE AMP output by the gain adjustment switches
(TOG1 to TOG4).
The balance and gain adjustment switches are controlled with commands.
Set the cut-off frequency of the external LPF between 10Hz and 100Hz.
– 19 –
CXA2542AR
• Balance adjustment
The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external
LPF, extracting the offset DC, and comparing it to the reference level.
However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete offset DC can not be extracted.
To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency
that can lower a sufficient gain appears on the LPF.
Use the C.OUT output to check this frequency.
The offset DC and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001100D6)
Adjust the balance so that the SENS1 and SENS2 pins are both High.
VIN < VL < VH
VL < VIN < VH
VL < VH < VIN
H
H
L
L
H
H
SENS1 pin
BALH
SENS2 pin
BALL
VH: High level threshold value
VIN: Window comparator input signal
VL: Low level threshold value
• Gain adjustment
Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component
to the reference level.
The AC component is generated by taking the difference between TE and the offset DC input to Pin 42.
The AC component and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001101D6)
The comparison signal is as follows.
(1)
(2)
(3)
VH
VL
VIN
SENS1 pin
TGH
SENS2 pin
TGL
H
H
L
The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2).
When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the
TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL
(SENS2 pin).
– 20 –
CXA2542AR
APC & Laser Power Control
VCC
C2
100µ
R1
22
LD
R6
1k
VCC
LDON
L1
10µH
R10
56k
130mV
PD
C1
1µ
34
R2
500
LD PD
R8
10k
35
R3
100
R4
10k
R5
55k
R12
56k
R11
10k
VREF
VEE
GND
VEE
VL
VEE
RF_I
LPC ON/OFF
R14
12.5k
MIRR
50%/30%
30
C3
0.01µ
FOK
R7
13k
RF_O
670mV
31
R9
41k
VC
RF
0.684V for 4.5V or more
0.57V for 3.6V or less
VEE
RFTC
33
R13
1M
C4
1µ
VEE VEE
• APC
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics.
The APC circuit is used to maintain the optical power output at a constant level.
The laser diode current is controlled according to the monitor photodiode output.
• Laser power control
The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations.
The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR.
This signal is then compared with the reference level.
The laser power is controlled by attaching an offset to VL according to the results of comparison with the
reference level.
The reference level is set to 0.57V for the power supply of 3.6V or less and to 0.684V for 4.5V or more.
LPC ON/OFF and LD ON/OFF control is performed with commands.
The laser power control limit can also be switched between ±50% and ±17% with commands.
LPC
LPCL
VL variable range
OFF
—
ON
±50%
Approximately 1.27V ± 625mV
ON
±30%
Approximately 1.27V ± 375mV
Approximately 1.27V
– 21 –
CXA2542AR
Center Voltage Generation Circuit
(The figure below shows a single voltage application; Connect to GND for dual power supplies.)
The maximum current is approximately ±3mA. The output impedance is approximately 50Ω.
VCC
VCC
30k
VC
50
VC
46
30k
VEE
GND
Connected internally to the VEE pin.
– 22 –
CXA2542AR
Focus Servo
6k
0.022µ
FZC
47
54k
FZC
FEO
48
10k
SENS
SELECTOR
FE
23 SENS1
300k
1
FEI
100k
10k
2200p
DFCT
FS4
68k
FDFCT
0.1µ
FOCUS COIL
FE_O
Focus
100k
phase
Compensation
FS3
2
5
FGD
3
50k
100k
FE_M
6
680k
40k
11µ
22µ
0.1µ
ISET
60k
16
50k
FS2
FLB
4
0.1µ
FSET
10
510k
7
SRCH
FS1
Charge
up
0.015µ
4.7µ
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100kΩ resistance and the capacitance connected to Pin 2. When this DFCT prevention circuit is not used,
leave Pin 2 open. The defect switch operation can be enabled and disabled with command.
The capacitor connected between Pin 4 and GND is a time constant to boost the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510kΩ is
connected to Pin 10.
The focus search level is approximately ±1.1Vp-p when using the constants indicated in the above figure. This
level is inversely proportional to the resistance connected between Pin 16 and VEE. However, changing this
resistance also changes the level of the track jump and sled kick as well.
The FZC comparator inverted input is set to 10% of Vcc and VC (Pin 46); (Vcc – VC) × 10%.
∗ 510kΩ resistance is recommended for Pin 10.
– 23 –
CXA2542AR
Tracking and Sled Servo
+
41
–
TEO
100k
BUFFER AMP
150k
0.01µ
0.01µ
42
LPFI
TGH
GAIN
TGL
WINDOW
COMPARATOR
24 SENS2
SENS
SELECTOR
23 SENS1
BALH
BALANCE
WINDOW
COMPARATOR BALL
TM1
680k
SL_M
100k
100k
TDFCT
680k
14
66p
TM6 22µA
45
0.1µ
8.2k
TM5
470p
330k
1k
ATSC
1k
13
22µA
ATSC
TM4 11µA
100k
TZC
TA_M
11
44
TM3
TZC
8
0.033µ
9
SL_P
TM2
3.3µ
43
0.022µ
M
TG1
120k
DFCT
0.047µ 47k
SLED MOTOR
SL_O
15
TE
0.015µ
TE
20k
TGU
TG2
TG2
10k
Tracking Phase
Compensation
82k
22µ
100k
15k
11µA
TRACKING
COIL
90k
TA_O
12
TM7
470k
FSET
10
510k
0.015µ
The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 8 and 9 is a time constant to cut the high-frequency gain when TG2 is
OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance is connected to Pin 10. In the CXA2542AQ, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 11. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 14;
Sled kick peak voltage = TM5 (or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 16 and VEE.
When this resistance is 60kΩ :
TM3 (or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100kΩ) and the capacitance connected to Pin 45.
– 24 –
CXA2542AR
The ISET pin is used to connect external resistance. This external resistance sets the current which
determines the focus search, track jump, and sled kick levels.
• Focus search current
I1 =
I1
VBG
×
R
1
2
I2
(VBG: approximately 1.27V)
I2 = 2I1
FS1
• Track jump current (TM3 and TM4 current)
I=
VBG
×
R
1
2
• Sled kick current (TM5 and TM6 current, when D1 = D0 = 0 during 1X$ commands)
I=
VBG
R
Use external resistance of between 30kΩ and 240kΩ.
Using external resistance outside this range may cause oscillation.
– 25 –
CXA2542AR
Focus OK Circuit
RF
VCC
DEFECT
RF_O
20k
31
C5
0.01µ
×1
44k
25 FOK
VG
30
RF_I
V4
LPC MIRR
15k
56k
0.63V
FOCUS OK AMP
FOCUS OK
COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
V4 is set in V3=V4 to cancel V3 of the RF amplifier voltage VRFO.
The focus OK output is inverted when VRFI – VRFO ≈ –0.51V.
Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK
amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block error rate
degradation brought about by RF envelope defects caused by scratched discs can be prevented.
Defect circuit
After differentiated with the capacitance coupling and then inverted, the RF_O signal is bottom held by means
of the long and short time constants.
The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms.
The long time-constant bottom hold keeps the mirror level prior to the defect and shifts the level.
The long and short time-constant signals are compared to generate the mirror defect detection signal.
Be sure to disable DFCT ($34X) during focus search because the focus drive waveform is muted.
0.068µ
CC1
CC2
26
27
FOK
a
DFCT2
FLIP
FLOP
24 SENS2
RF
×2
43k
b
c
d DFCT1
DEFECT SW
DEFECT AMP
DEFECT BOTTOM
HOLD
30
CB
0.01µ
–0.5V
a
RFO
b
DEFECT
AMP
c
BOTTOM
HOLD (1)
solid line
e
SENS1
f
INT
SENS
SELECTOR
DEFECT COMPARATOR
f
INTERRUPTION
COMPARATOR
d
H
L
H
L
– 26 –
BOTTOM
HOLD (2)
broken line
e
23 SENS1
CXA2542AR
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been inverting amplified.
For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the
rotation cycle envelope fluctuation.
FOK
1V
DEFECT
RF_O
RF
31
51k
MIRROR HOLD AMP
FOK
C5
0.01µ
1.5k
LPC
30
× 1.4
RF_I
G
PEAK &
BOTTOM
HOLD
MIRROR AMP
22k
H
0.033µ
29
CP
×1
I
J
K
MIRR
SENS
SELECTOR
24 SENS2
MIRROR
COMPARATOR
RF_O
0V
G
(RF_I)
0V
H
(PEAK HOLD)
0V
I
(BOTTOM HOLD)
0V
J
K
(MIRROR HOLD)
H
MIRR
L
The DC restored-envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. If the value of C5 is made smaller, the low frequency component of the
RF signal is cut off and the amplification of the signal G gets small. Then, that of the signal J gets also small
and the signal K level becomes low, resulting in the short mirror output pulse width. Accordingly, when on the
disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is
detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal.
– 27 –
CXA2542AR
SENS Selector
FZC
HIGH-Z
DFCT1
DFCT2
TZC
MIRR
BALH
BALL
23 SENS1
24 SENS2
TGH
TGL
FOH
FOL
ATSC
What is output to the SENS1 and SENS2 pins varies according to the address input to the DATA pin.
DATA (Pin 20) 8-bit transfer
ADDRESS
DATA
SENS1
SENS2
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
X
X
X
X
FZC
H
(HIGH-Z)
0
0
0
1
X
X
X
X
DFCT1
DFCT2
0
0
1
0
X
X
X
X
TZC
MIRR
0
1
1
1
0
1
0
1
X
X
X
X
X
X
X
X
H
(HIGH-Z)
H
(HIGH-Z)
DATA (Pin 20) 12-bit transfer
ADDRESS
D11 D10
DATA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SENS1
SENS2
0
0
1
1
0
0
X
X
X
X
X
X
BALH
BALL
0
0
1
1
0
1
X
X
X
X
X
X
TGH
TGL
0
0
1
1
1
0
X
X
X
X
X
X
FOH
FOL
0
0
1
1
1
1
X
X
X
X
X
X
ATSC
H
(HIGH-Z)
Notes)
• 12-bit transfer should be performed during $3XX commands. When 8 bits are transferred, SENS1 and
SENS2 are switched according to the D3 and D2 data.
• SENS1 and SENS2 are switched without latching.
– 28 –
CXA2542AR
Commands
The input data to operate this IC is configured as 8-bit/12-bit data; however, below, this input data is
represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0
and F/$XXX for 12-bit.
Commands for the CXA2542AR can be broadly divided into four groups ranging in value from $0X, $1X, $2X,
$3XX.
1. $0X (FZC at SENS1 pin (Pin 23), H (Hi-Z) at SENS2 pin (Pin 24))
These commands are related to the focus servo control.
The bit configuration is as shown below.
D7
0
D6
0
D5
0
D4
0
D3
FS4
D2
—
D1
FS2
D0
FS1
Four focus related switches exist: FS1, FS2, FS4 and DFCT.
$00
$02
When FS1 = 0, Pin 7 is charged to (22µA – 11µA) × 50kΩ = 0.55V.
If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 5 becomes 0V.
From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 5. This voltage level is obtained by equation 1 below.
(22µA – 11µA) × 50kΩ ×
$03
resistance between Pins 5 and 6
.... Equation 1
50kΩ
The SRCH DOWN speed can be increased by the charge up circuit.
From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 7 decreases with the time as
shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 7 when FS1 goes from 0 → 1
This time constant is obtained with the 50kΩ resistance and an external capacitor.
By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 5)
– 29 –
CXA2542AR
1-1. FS4
This switch is provided between the focus error input and the focus phase compensation, and is in charge of
turning the focus servo ON and OFF.
$00
→ $08
Focus off
Focus on
1-2. Procedure of focus activation
For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 5) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.
A
t
Fig. 3. S-curve
The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and
turning the focus servo switch ON are performed while the focus S-curve transits the point A indicated in Fig.
3. To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, the FZC (Focus Zero Cross) signal is output from the SENS1 pin (Pin 23) as the point A transit signal.
In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
(20ms) (200ms)
$02
($00)
$03
$08
Drive voltage
∗ The broken lines in the figure
indicate the voltage assuming
the signal not in focus.
Focus error
SENS1
(FZC)
The instant when the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart
– 30 –
CXA2542AR
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ↓ ?
Transfer $08
NO
YES
F. OK?
F. OK?
NO
NO
YES
YES
FZC ↓ ?
Transfer $08
NO
YES
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences
2. $1X (DFCT1 at SENS1 pin (Pin 23), DFCT2 at SENS2 pin (Pin 24))
These commands deal with switching TG1/TG2, brake circuit ON/OFF,
and the sled kick output.
The bit configuration is as follows:
0
D6
0
D5
0
D4
1
D3
D2
TG1, TG2 Brake
circuit
ON/OFF ON/OFF
D1
D0
Sled kick
level
D1
(PS1)
D0
(PS0)
Relative
value
D7
Sled kick level
0
0
0
1
±1
±2
1
1
0
1
±3
±4
TG1, TG2, TM7
The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track
jump has been performed actually though a 100-track jump was intended to be done due to the extremely
degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump.
For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to
the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between
the RF envelope and the tracking error is 180° out-of-phase to cut the unneeded portion of the tracking error
and apply braking.
– 31 –
CXA2542AR
[∗B]
[∗A]
Envelope
Detection
RF_I 30
Waveform
Shaping
[∗E]
[∗D]
Waveform
Shaping
TZC 44
D2
(MIRR)
[∗C]
[∗F]
Edge Detection
D Q
[∗G]
BRK
TM7
Low: open
High: make
CK
[∗H]
(Latch)
CXA2542AR
Fig. 6. TM7 movement during braking operation
From inner to outer track
From outer to inner track
[∗A]
[∗B]
[∗C]
("MIRR")
[∗D]
("TZC")
[∗E]
[∗F]
[∗G]
[∗H]
Braking is applied
from here.
0V
Fig. 7. Internal waveform
3. $2X (TZC at SENS1 pin (Pin 23), MIRR at SENS2 pin (Pin 24))
These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7
0
D6
D5
D4
0
1
0
D3
D2
Tracking
control
00
off
01
Servo ON
10
F-JUMP
11
R-JUMP
↓
TM1, TM3, TM4,
– 32 –
D1
D0
Sled
control
00
off
01
Servo ON
10
F-FAST FORWARD
11
R-FAST FORWARD
↓
TM2, TM5, TM6
CXA2542AR
4. $3XX
These commands mainly control the balance and gain control circuit switches used during automatic tracking
adjustment and the bias circuit switch used during automatic focus bias adjustment.
In the initial resetting state, BAL1 to BAL4 switches and TOG1 to TOG4 switches are ON. Also, the IFB1 to
IFB6 switches are ON.
• Balance adjustment
The balance adjustment switches BAL1 to BAL4 can be controlled by setting D6 = 0 and D7 = 0. The switches
are set using D0 to D3.
At this time, SENS1 outputs BALH and SENS2 outputs BALL.
Data is set by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 0 and D7 = 0.
Sending a latch pulse with D6, D7 ≠ 0 does not change the balance switch settings.
START
C.OUT
is the frequency high
enough ?
BAL1 to BAL4
Switch Control
NO
YES
SENS1/2
Balance OK ?
Adjustment Completed
Balance adjustment
• Gain adjustment
The gain adjustment switches TOG1 to TOG4 can be controlled by setting D6 = 1 and D7 = 0. These switches
are set using D0 to D3.
At this time, SENS1 outputs TGH and SENS2 outputs TGL.
In a fashion similar to the method used with the balance adjustment, set the data by specifying switch
conditions D0 to D3 and sending a latch pulse with D6 = 1 and D7 = 0.
START
TOG1 to TOG4
Switch control
SENS1/2
GAIN OK ?
NO
YES
Adjustment Completed
Gain adjustment
– 33 –
CXA2542AR
• Focus bias adjustment
The focus bias adjustment switches IFB1 to IFB6 can be controlled by setting D6 = 0 and D7 = 1. The switches
are set using D0 to D5.
At this time, SENS1 outputs FOH and SENS2 outputs FOL.
Data is set by specifying switch conditions D0 to D5 and sending a latch pulse with D6 = 0 and D7 = 1.
START
IFB1 to IFB6
Switch Control
SENS1/2
BIAS OK ?
NO
YES
Adjustment Completed
Focus bias adjustment method
• TGFL
The tracking gain can be switched by setting D5 with D6 = 1 and D7 = 0.
The tracking gain is GAIN UP with D5 = 1 and NORMAL GAIN with D5 = 0.
The TEO signal level can be made higher by approximately 6dB for GAIN UP.
When the TEO signal level is low and TGH (SENS1 pin) does not go Low during tracking adjustment, the
gain should be raised with the TGFL command for adjustment.
• LPC
The laser power control circuit can be turned ON and OFF by setting D0 with D6 = 1 and D7 = 1.
The circuit is ON with D0 = 1 and OFF with D0 = 0.
• LPCL
The laser power control limit can be switched between ±30% and ±50% by setting D1 with D6 = 1 and D7 = 1.
The control limit is ±30% with D1 = 0 and ±50% with D1 = 1.
• LDON
The laser diode can be turned ON and OFF by setting D2 with D6 = 1 and D7 = 1.
The laser diode is ON with D2 = 1 and OFF with D2 = 0.
– 34 –
CXA2542AR
• ATSC
The anti-shock function can be controlled by setting D3 with D6 = 1 and D7 = 1.
This function is disabled with D3 = 1 and enabled with D3 = 0.
At this time, SENS1 outputs ATSC.
Even if ATSC is disabled, ATSC is output to SENS1.
When an anti-shock signal is generated during the enable status, TG1 and TG2 switch to GAIN UP mode.
(In the Block Diagram, TG1 is set to the
side and TG2 is OFF. Even if TG1 and TG2 are in NORMAL
mode, they switch to GAIN UP mode in conjunction with ATSC.)
When the anti-shock function is not used, Pin 43 (ATSC) should be connected to VC.
• RDFCT2
DFCT2 can be reset by setting D4 with D6 = 1 and D7 = 1.
DFCT2 is reset with D4 = 1.
After a reset, High is held when DFCT1 rises.
During $1X commands, DFCT2 is output from SENS2.
DFCT2 operates even if DFCT is disabled.
Whether or not DFCT rises at the proper timing for the microcomputer can also be confirmed.
• INT
The interruption (scratched disc) countermeasure circuit can be set to the operating status by setting D5 with
D6 = 1 and D7 = 1.
This circuit is enabled when D5 = 1 and disabled when D5 = 0.
Even if DFCT1 does not rise, this circuit is effective for scratched discs which cause MIRR to rise.
When MIRR rises, the DFCT switch is routed through the low-pass filter.
The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking
gain is increased. (including when the gain is increased by ATSC)
Even if DFCT is disabled, the interruption countermeasure circuit operates when INT is enabled.
– 35 –
CXA2542AR
CPU Serial Interface Timing Chart
DATA
D0
D1
tWCK
D2
D3
tWCK
tSU
D4
D5
D6
D7
D0
th
CLK
tCD
1/fck
tD
XLT
tWL
(VCC = 3.0V)
Item
Symbol
Min.
Typ.
Max.
Unit
1
MHz
Clock frequency
fck
Clock pulse width
fwck
500
ns
Setup time
500
ns
500
ns
500
ns
1000
ns
Data transfer interval
tsu
th
tD
tWL
tCD
1000
ns
Low level input voltage
VIL
0.0
(VCC – VEE) × 0.1
V
High level input voltage
VIH
(VCC – VEE) × 0.9
VCC
V
Hold time
Delay time
Latch pulse width
– 36 –
0
0
TRACKING
CONTROL
TRACKING
SLED MODE
– 37 –
ON
FWD MOVE
REV MOVE
1
0
1
0
1
1
ON
FWD JUMP
REV JUMP
1
1
0
0
OFF
0
1
0
1
0
D0
D1
SLED MODE ∗2
SLED
KICK + 2
FS2
SRCH ON
1 = ON
0 = OFF
DATA
1 = ENABLE
0 = DISABLE
0
∗2 SLED MODE
—
D2
BRAKE
TRACKING MODE ∗1
1 = GAIN UP
0 = NORMAL
TG1, TG2
FS4
Focus
1 = ON
0 = OFF
D3
OFF
0
1
0
D4
D1
1
0
0
D5
D2
0
0
0
D6
ADDRESS
DATA (Pin 20) 8-bit transfer
D3
∗1 TRACKING MODE
0
D7
FOCUS
CONTROL
Item
System Control
SLED
KICK + 1
FS2
SRCH UP
1 = UP
0 = DOWN
D0
TZC
DFCT1
FZC
SENS1
MIRR
DFCT2
H
(HIGH-Z)
SENS2
CXA2542AR
0
FOCUS
BIAS
– 38 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
D6
RDFCT2
INT
ATSC
1 = OFF
0 = ON
IFB4
1 = OFF
0 = ON
TOG4
1 = OFF
0 = ON
BAL4
D3
LDON
1 = OFF
0 = ON
IFB3
1 = OFF
0 = ON
TOG3
1 = OFF
0 = ON
BAL3
D2
1 = ENABLE 1 = RESET
1 = DISABLE 1 = ON
0 = DISABLE 0 = NORMAL 0 = ENABLE 0 = OFF
1 = OFF
0 = ON
IFB5
—
—
D4
1 = OFF
0 = ON
IFB6
1 = GAIN UP
0 = NORMAL
TGFL
1 = DISABLE
0 = ENABLE
DFCT
D5
DATA
1 = ON
0 = OFF
LPC
LPCL
1 = ±50%
0 = ±30%
1 = OFF
0 = ON
IFB1
IFB2
1 = OFF
0 = ON
1 = OFF
0 = ON
TOG1
TOG2
1 = OFF
0 = ON
1 = OFF
0 = ON
BAL1
D0
1 = OFF
0 = ON
BAL2
D1
Notes)
• When ATSC is enabled, even if TG1 and TG2 are in NORMAL mode, TG1 and TG2 switch to GAIN UP mode in conjunction with ATSC.
• INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC)
When reset
• SENS1 = FZC
• SENS2 = High (Hi-Z)
• RDFCT2 = 1 (Reset)
• IFB1 to IFB6 = 0 (switch ON)
• TOG1 to TOG4 = 0 (switch ON)
• BAL1 to BAL4 = 1 (switch ON)
• Other data is "0".
0
0
TRACKING
GAIN
Others
0
D8 D7
ADDRESS
D11 D10 D9
E-F
BALANCE
Item
DATA (Pin 20) 12-bit transfer
ATSC
FOH
TGH
BALH
SENS1
H
(HIGH-Z)
FOL
TGL
BALL
SENS2
CXA2542AR
CXA2542AR
Serial Data Truth Table
Serial Data
HEX
FOCUS CONTROL
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
Functions
FS2 FS1
FS4
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes) • FS1
1: OFF
0: ON
• FS2
1: ON
0: OFF
• FS4
In the Block Diagram:
1: SW
side
0: SW
side
BRAK SLD KICK
TG1 Fig. 6 KICK KICK
TG2 D2
+2
+1
TRACKING CONTROL
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 0101
0001 0110
0001 0111
0001 1000
0001 1001
0001 1010
0001 1011
0001 1100
0001 1101
0001 1110
0001 1111
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes) • TG1
In the Block Diagram:
1: SW
side
0: SW
side
• TG2
1: OFF
0: ON
• BRAKE
When D2 in Fig. 6 is:
1: 1
0: 0
• Sled kick level
– 39 –
D1
D0
0
0
1
1
0
1
0
1
Relative value
±1
±2
±3
±4
CXA2542AR
Serial Data
HEX
TM6 TM5 TM4 TM3 TM2 TM1
TRACKING/SLED MODE
0010 0000
0010 0001
0010 0010
0010 0011
0010 0100
0010 0101
0010 0110
0010 0111
0010 1000
0010 1001
0010 1010
0010 1011
0010 1100
0010 1101
0010 1110
0010 1111
Function
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
– 40 –
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Notes) • TM1/TM2
In the Block Diagram:
1: SW
side
0: SW
side
• TM3/TM4/TM5/TM6
1: ON
0: OFF
CXA2542AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 0000 0000
0011 0000 0001
0011 0000 0010
0011 0000 0011
0011 0000 0100
0011 0000 0101
0011 0000 0110
0011 0000 0111
0011 0000 1000
0011 0000 1001
0011 0000 1010
0011 0000 1011
0011 0000 1100
0011 0000 1101
0011 0000 1110
0011 0000 1111
$300
$301
$302
$303
$304
$305
$306
$307
$308
$309
$30A
$30B
$30C
$30D
$30E
$30F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
0011 0001 0000
0011 0001 0001
0011 0001 0010
0011 0001 0011
0011 0001 0100
0011 0001 0101
0011 0001 0110
0011 0001 0111
0011 0001 1000
0011 0001 1001
0011 0001 1010
0011 0001 1011
0011 0001 1100
0011 0001 1101
0011 0001 1110
0011 0001 1111
$310
$311
$312
$313
$314
$315
$316
$317
$318
$319
$31A
$31B
$31C
$31D
$31E
$31F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
0011 0010 0000
0011 0010 0001
0011 0010 0010
0011 0010 0011
0011 0010 0100
0011 0010 0101
0011 0010 0110
0011 0010 0111
0011 0010 1000
0011 0010 1001
0011 0010 1010
0011 0010 1011
0011 0010 1100
0011 0010 1101
0011 0010 1110
0011 0010 1111
$320
$321
$322
$323
$324
$325
$326
$327
$328
$329
$32A
$32B
$32C
$32D
$32E
$32F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
– 41 –
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA2542AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 0011 0000
0011 0011 0001
0011 0011 0010
0011 0011 0011
0011 0011 0100
0011 0011 0101
0011 0011 0110
0011 0011 0111
0011 0011 1000
0011 0011 1001
0011 0011 1010
0011 0011 1011
0011 0011 1100
0011 0011 1101
0011 0011 1110
0011 0011 1111
$330
$331
$332
$333
$334
$335
$336
$337
$338
$339
$33A
$33B
$33C
$33D
$33E
$33F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0011 0100 0000
0011 0100 0001
0011 0100 0010
0011 0100 0011
0011 0100 0100
0011 0100 0101
0011 0100 0110
0011 0100 0111
0011 0100 1000
0011 0100 1001
0011 0100 1010
0011 0100 1011
0011 0100 1100
0011 0100 1101
0011 0100 1110
0011 0100 1111
$340
$341
$342
$343
$344
$345
$346
$347
$348
$349
$34A
$34B
$34C
$34D
$34E
$34F
0011 0101 0000
0011 0101 0001
0011 0101 0010
0011 0101 0011
0011 0101 0100
0011 0101 0101
0011 0101 0110
0011 0101 0111
0011 0101 1000
0011 0101 1001
0011 0101 1010
0011 0101 1011
0011 0101 1100
0011 0101 1101
0011 0101 1110
0011 0101 1111
$350
$351
$352
$353
$354
$355
$356
$357
$358
$359
$35A
$35B
$35C
$35D
$35E
$35F
4 3 2 1 4 3 2 1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
TGFL
IFB SW
6 5 4 3 2 1
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
– 42 –
CXA2542AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 0110 0000
0011 0110 0001
0011 0110 0010
0011 0110 0011
0011 0110 0100
0011 0110 0101
0011 0110 0110
0011 0110 0111
0011 0110 1000
0011 0110 1001
0011 0110 1010
0011 0110 1011
0011 0110 1100
0011 0110 1101
0011 0110 1110
0011 0110 1111
$360
$361
$362
$363
$364
$365
$366
$367
$368
$369
$36A
$36B
$36C
$36D
$36E
$36F
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 0111 0000
0011 0111 0001
0011 0111 0010
0011 0111 0011
0011 0111 0100
0011 0111 0101
0011 0111 0110
0011 0111 0111
0011 0111 1000
0011 0111 1001
0011 0111 1010
0011 0111 1011
0011 0111 1100
0011 0111 1101
0011 0111 1110
0011 0111 1111
$370
$371
$372
$373
$374
$375
$376
$377
$378
$379
$37A
$37B
$37C
$37D
$37E
$37F
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1000 0000
0011 1000 0001
0011 1000 0010
0011 1000 0011
0011 1000 0100
0011 1000 0101
0011 1000 0110
0011 1000 0111
0011 1000 1000
0011 1000 1001
0011 1000 1010
0011 1000 1011
0011 1000 1100
0011 1000 1101
0011 1000 1110
0011 1000 1111
$380
$381
$382
$383
$384
$385
$386
$387
$388
$389
$38A
$38B
$38C
$38D
$38E
$38F
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
– 43 –
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA2542AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 1001 0000
0011 1001 0001
0011 1001 0010
0011 1001 0011
0011 1001 0100
0011 1001 0101
0011 1001 0110
0011 1001 0111
0011 1001 1000
0011 1001 1001
0011 1001 1010
0011 1001 1011
0011 1001 1100
0011 1001 1101
0011 1001 1110
0011 1001 1111
$390
$391
$392
$393
$394
$395
$396
$397
$398
$399
$39A
$39B
$39C
$39D
$39E
$39F
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1010 0000
0011 1010 0001
0011 1010 0010
0011 1010 0011
0011 1010 0100
0011 1010 0101
0011 1010 0110
0011 1010 0111
0011 1010 1000
0011 1010 1001
0011 1010 1010
0011 1010 1011
0011 1010 1100
0011 1010 1101
0011 1010 1110
0011 1010 1111
$3A0
$3A1
$3A2
$3A3
$3A4
$3A5
$3A6
$3A7
$3A8
$3A9
$3AA
$3AB
$3AC
$3AD
$3AE
$3AF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1011 0000
0011 1011 0001
0011 1011 0010
0011 1011 0011
0011 1011 0100
0011 1011 0101
0011 1011 0110
0011 1011 0111
0011 1011 1000
0011 1011 1001
0011 1011 1010
0011 1011 1011
0011 1011 1100
0011 1011 1101
0011 1011 1110
0011 1011 1111
$3B0
$3B1
$3B2
$3B3
$3B4
$3B5
$3B6
$3B7
$3B8
$3B9
$3BA
$3BB
$3BC
$3BD
$3BE
$3BF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
– 44 –
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA2542AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 1100 0000
0011 1100 0001
0011 1100 0010
0011 1100 0011
0011 1100 0100
0011 1100 0101
0011 1100 0110
0011 1100 0111
0011 1100 1000
0011 1100 1001
0011 1100 1010
0011 1100 1011
0011 1100 1100
0011 1100 1101
0011 1100 1110
0011 1100 1111
$3C0
$3C1
$3C2
$3C3
$3C4
$3C5
$3C6
$3C7
$3C8
$3C9
$3CA
$3CB
$3CC
$3CD
$3CE
$3CF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1101 0000
0011 1101 0001
0011 1101 0010
0011 1101 0011
0011 1101 0100
0011 1101 0101
0011 1101 0110
0011 1101 0111
0011 1101 1000
0011 1101 1001
0011 1101 1010
0011 1101 1011
0011 1101 1100
0011 1101 1101
0011 1101 1110
0011 1101 1111
$3D0
$3D1
$3D2
$3D3
$3D4
$3D5
$3D6
$3D7
$3D8
$3D9
$3DA
$3DB
$3DC
$3DD
$3DE
$3DF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1110 0000
0011 1110 0001
0011 1110 0010
0011 1110 0011
0011 1110 0100
0011 1110 0101
0011 1110 0110
0011 1110 0111
0011 1110 1000
0011 1110 1001
0011 1110 1010
0011 1110 1011
0011 1110 1100
0011 1110 1101
0011 1110 1110
0011 1110 1111
$3E0
$3E1
$3E2
$3E3
$3E4
$3E5
$3E6
$3E7
$3E8
$3E9
$3EA
$3EB
$3EC
$3ED
$3EE
$3EF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
– 45 –
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA2542AR
Serial Data
$3XX
HEX
0011 1111 0000
0011 1111 0001
0011 1111 0010
0011 1111 0011
0011 1111 0100
0011 1111 0101
0011 1111 0110
0011 1111 0111
0011 1111 1000
0011 1111 1001
0011 1111 1010
0011 1111 1011
0011 1111 1100
0011 1111 1101
0011 1111 1110
0011 1111 1111
$3F0
$3F1
$3F2
$3F3
$3F4
$3F5
$3F6
$3F7
$3F8
$3F9
$3FA
$3FB
$3FC
$3FD
$3FE
$3FF
BAL SW TOG SW
4 3 2 1 4 3 2 1
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
TGFL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IFB SW
6 5 4 3 2 1
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
INT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RDF
ATSC LDON LPCL LPC DFCT
CT2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Notes) • 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values
of each bit for serial data.
• "—" in the Truth Table indicates that the status does not change.
• TGFL
In the Block Diagram:
1: SW
side
0: SW
side
• ATSC E: enable/D: disable
• DFCT E: enable/D: disable
– 46 –
CXA2542AR
Initial State (resetting state)
ADDRESS
Item
DATA
D7 D6 D5 D4 D3 D2 D1 D0
HEX
FOCUS CONTROL
0
0
0
0
0
0
0
0
$00
TRACKING CONTROL
0
0
0
1
0
0
0
0
$10
TRACKING SLED MODE
0
0
1
0
0
0
0
0
$20
Item
ADDRESS
DATA
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HEX
E-F BALANCE
0
0
1
1
0
0
0
0
0
0
0
0
$300
TRACKING GAIN
0
0
1
1
0
1
0
0
0
0
0
0
$340
FOCUS BIAS
0
0
1
1
1
0
0
0
0
0
0
0
$380
Others
0
0
1
1
1
1
0
1
0
0
0
0
$3D0
The above data means the following operation modes.
FOCUS CONTROL
TRACKING CONTROL
TRACKING SLED MODE
E-F BALANCE
TRACKING GAIN
FOCUS BIAS
Others
: FOCUS OFF, FOCUS SEARCH OFF, FOCUS SEACH DOWN
: TG1-TG2 NORMAL, BRAKE DISABLE, SLED KICK relative level value ±1
: TRACKING OFF, SLED OFF
: BAL1 to BAL4 = 0 (switch ON). DFCT ENABLE
: TOG1 to TOG4 = 0 (switch ON), TGFL NORMAL
: IFB1 to IFB6 = 0 (switch ON)
: INT DISABLE, DFCT2 RESET, ATSC ENABLE, LDON OFF, LPCL ±30%, LPC OFF
– 47 –
CXA2542AR
Notes on Operation
1. Focus OK circuit
1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
2) The equivalent circuit for the output pin (FOK) is shown in the diagram below.
VCC
20k
FOK
25
40k
The FOK and comparator output are as follows:
Output voltage High : VFOKH ≈ near Vcc
Output voltage Low : VFOKL ≈ Vsat (NPN) + VEE
RL
100k
VCC
VEE
VEE
2. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.
3. Focus/Tracking internal phase compensation and reference design material
TRK
FCS
Item
SD
1.2kHz gain
08
1.2kHz phase
08
1.2kHz gain
25
1.2kHz phase
25
2.7kHz gain
25 → 13
2.7kHz phase
25 → 13
Measurement pin
6
13
Conditions
Typ.
Unit
CFLB = 0.1µF
CFGD = 0.1µF
21.5
dB
63
deg
13
dB
–125
deg
26.5
dB
–130
deg
CTGU = 0.1µF
4. Laser Poser Control
The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations.
The laser life is shortened by increasing the laser power when the less light is reflected from the disc.
It is recommended that the typical laser power value is set lower to maintain the laser life.
Take care of the laser maximum ratings when using the laser power control circuit.
– 48 –
CXA2542AR
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
0.5 ± 0.2
B
A
48
(8.0)
24
37
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
S
0.5 ± 0.2
(0.18)
0° to 10°
DETAIL B:SOLDER
DETAIL A
0.18 ± 0.03
0.127 ± 0.04
+ 0.08
0.18 – 0.03
(0.127)
+0.05
0.127 – 0.02
0.1 ± 0.1
DETAIL B:PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 49 –