CXA1372BQ/BS
RF Signal Processing Servo Amplifier for CD Player
Description
The CXA1372BQ/BS is a bipolar IC developed for
RF signal processing (focus OK, mirror, defect
detection, EFM comparator) and various servo
control.
Features
• Dual ±5V and single 5V power supplies
• Low power consumption
• Fewer external parts
• Disc defect countermeasure circuit
• Fully compatible with the CXA1182 for microcomputer
software
Functions
• Auto asymmetry control
• Focus OK detection circuit
• Mirror detection circuit
• Defect detection, countermeasure circuit
• EFM comparator
• Focus servo control
• Tracking servo control
• Sled servo control
CXA1372BQ
48 pin QFP (Plastic)
CXA1372BS
48 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
12
V
• Supply voltage
VCC – VEE
• Operating temperature
Topr
–20 to +75 °C
• Storage temperature
Tstg
–65 to +150 °C
• Allowable power dissipation
PD 457 (CXA1372BQ) mW
833 (CXA1372BS) mW
Recommended Operating Conditions
VCC – VEE
3.6 to 11
VCC – DGND 3.6 to 5.5
V
V
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95927A67-PS
CXA1372BQ/BS
CC1
FOK
EFM
DFCT
MIRR
DGND
SENS
C. OUT
35
34
33
32 31 30
29
28
27
26 25
XRST
CC2
36
ASY
DVcc
Block Diagram
• IIL
↓
• TTL
24 DATA
CB 37
23 XLT
CP 38
• TTL
↓
• IIL
RFI 39
22 CLK
RFO 40
21 LOCK
• IIL DATA REGISTER
• INPUT SHIFT REGISTER
• ADDRESS DECODER
• TTL
↓
• IIL
DVEE 41
20 DIRC
• OUTPUT DECODER
TZC 42
• FS1 to 4
• TG1 to 2
TE 43
TG1
TDFCT 44
ATSC 45
• TRACKING
PHASE COMPENSATION
18 SSTOP
TM1
• BPF
• WINDOW COMPARATOR
FS1
DFCT
• I SET
17 ISET
• F SET
16 FSET
TM6
• FOCUS
PHASE
COMPENSATION
FZC 46
FE 47
• TM1 to 7 • PS1 to 3
19 AVEE
DFCT
TM5
15 SL–
TM4
14 SLO
TM7
FDFCT 48
TM3
13 SL+
TM2
FS4
FS2
FS3
8
9
10
11
12
TAO
TA–
FLB
7
AVCC
FS3
6
TG2
FGD
5
TGU
4
SRCH
3
FE–
2
FEO
1
VC
TG2
–2–
CXA1372BQ/BS
Pin Configuration
DVcc
CC2
CC1
FOK
EFM
ASY
DFCT
MIRR
DGND
SENS
C. OUT
XRST
CXA1372BQ
36
35
34
33
32
31
30
29
28
27
26
25
CB 37
24 DATA
CP 38
23 XLT
RFI 39
22 CLK
RFO 40
21 LOCK
DVEE 41
20 DIRC
TZC 42
19 AVEE
CXA1372BQ
TE 43
18 SSTOP
TDFCT 44
17 ISET
ATSC 45
16 FSET
FZC 46
15 SL–
FE 47
14 SLO
FDFCT 48
1
2
3
4
5
6
7
8
9
10
11
12
VC
FGD
FS3
FLB
FEO
FE–
SRCH
TGU
TG2
AVcc
TAO
TA–
13 SL+
TZC
DVEE
RFO
RFI
CP
CB
DVcc
CC2
CC1
FOK
EFM
ASY
DFCT
MIRR
DGND
SENS
C. OUT
XRST
DATA
XLT
CLK
LOCK
DIRC
AVEE
CXA1372BS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TZC
FE
FDFCT
VC
FGD
FS3
FLB
FEO
14
15
16
17
18
19
20
21
22
23
24
SSTOP
ATSC
13
ISET
TDFCT
12
FSET
11
SL–
10
SLO
9
SL+
8
TA–
7
TAO
6
AVcc
5
TG2
4
TGU
3
SRCH
2
FE–
1
TE
CXA1372BS
–3–
CXA1372BQ/BS
Pin Description
Pin No.
Q
1
Symbol
S
7
VC
I/O
Equivalent circuit
Description
Center voltage input.
For dual power supplies: GND
For single power supply:
(VCC + GND)/2
I
Vcc
147
2
8
FGD
I
48k
2
130k
20µA
Connects a capacitor between this
pin and Pin 3 to cut high-frequency
gain.
VEE
46k
3
9
FS3
I
4
10
FLB
I
5
11
FEO
O
580k
3
40k
The high-frequency gain of the
focus servo is switched through FS3
ON and OFF.
External time constant to boost the
low frequency of the focus servo.
4
Focus drive output.
5
11
17
TAO
O
11
Tracking drive output.
250µA
14
2.5µA
14
20
SLO
Sled drive output.
O
90k
6
12
FE–
147
I
Inverted input for focus amplifier.
6
40k
2.5µA
–4–
CXA1372BQ/BS
Pin No.
Q
S
7
13
Symbol
I/O
Equivalent circuit
Description
147
SRCH
I
External time constant for forming
the focus search waveforms.
7
11µA
3.5µA
50k
110k
8
14
External time constant for selecting
the tracking high-frequency gain.
20k
TGU
I
8
82k
147
9
15
TG2
I
External time constant for selecting
the tracking high-frequency gain.
9
470k
90k
12
18
TA–
147
I
Inverted input for tracking amplifier.
12
3µA
11µA
10k
13
19
SL+
I
15
21
SL–
I
Non-inverted input for sled amplifier.
13
147
Inverted input for sled amplifier.
15
3µA
–5–
22µA
CXA1372BQ/BS
Pin No.
Q
S
16
22
Symbol
I/O
Equivalent circuit
Description
147
FSET
I
Sets the peak frequency of focus
tracking phase compensation.
16
15k
15k
Current is input to determine focus
search, track jump, and sled kick
level.
147
17
23 ISET
I
17
7µA
Limit SW ON/OFF signal detection
for disc innermost track detection.
147
18
24
SSTOP
I
20
26
DIRC
I
Used for 1-track jump. Contains a
47kΩ pull-up resistor.
21
27
LOCK
I
At "Low" sled overrun prevention
circuit operates. Contains a 47kΩ
pull-up resistor.
18
20
47k
21
22
28
CLK
I
22
15µA
Serial data transfer clock input from
CPU. (no pull-up resistor)
147
23
24
Latch input from CPU.
(no pull-up resistor)
23
29
XLT
I
24
30
DATA
I
Serial data input from CPU.
(no pull-up resistor)
25
31
XRST
I
Reset input, reset at "Low".
(no pull-up resistor)
26
32
C. OUT
O
Track number count signal output.
25
20k
147
26
27
27
33
SENS
O
100k
–6–
Outputs FZC, AS, TZC and SSTOP
through command from CPU.
CXA1372BQ/BS
Pin No.
Q
S
29
35
Symbol
MIRR
I/O
Equivalent circuit
O
Description
MIRR comparator output.
(DC voltage: 10kΩ load connected)
147
38
147
29
38
44
CP
I
34
40
CC1
O
Connects MIRR hold capacitor.
Non-inverted input for MIRR
comparator.
20k
DEFECT bottom hold output.
147
147
35
37
35
41
CC2
I
30
36
DFCT
O
Input for DEFECT bottom hold
output with capacitance coupled.
147
DEFECT comparator output.
(DC voltage: 10kΩ load connected)
147
30
34
37
43
CB
I
31
37
ASY
I
Connects DEFECT bottom hold
capacitor.
147
32
32
38
EFM
Auto asymmetry control input.
31
4.8k
EFM comparator output.
(DC voltage: 10kΩ load connected)
O
Current source depending on
power supply
(VCC to DGND)
20k
147
33
33
39
FOK
FOK comparator output.
(DC voltage: 10kΩ load connected)
O
–7–
CXA1372BQ/BS
Pin No.
Q
S
39
45
Symbol
RFI
I/O
Equivalent circuit
Description
Input for RF summing amplifier
output with capacitance coupled.
I
40k
147
39
40
46
RFO
O
RF summing amplifier output.
Check point of eye pattern.
147
40
7µA
147
42
48
TZC
I
Tracking zero-cross comparator
input.
42
75k
147
43
1
TE
I
43
44
2
TDFCT
I
44
470k
Tracking error input.
147
Connects a capacitor for time
constant during defect.
Vcc
470k
45
3
ATSC
Window comparator input for ATSC
detection.
45
I
330k
47P
VEE
46
4
FZC
60k
I
147
Focus zero-cross comparator input.
46
1.2k
47
5
FE
I
48
6
FDFCT
I
147
470k
47
147
Focus error input.
Connects a capacitor for time
constant during defect.
48
–8–
–9–
11
25
O O
11
28
11
Jump output voltage VJUMP2
VTE04
Max. output voltage
25
O O
19
VTE03
Max. output voltage
11
25
O
11
VTE02
Max. output voltage
11
25
O
11
11
27
2C
VTE01
Max. output voltage
∗
Jump output voltage VJUMP1
VTEOF
Feedthrough
00
25
DC voltage gain
GTEO
00
5
03
5
08
O O
5
5
08
O O
02
5
08
O
5
00
5
5
08
08
19, 41
00
FZC threshold value VFZC
VSRCH2
Search output voltage
VFE04
Max. output voltage
VSRCH1
VFE03
Max. output voltage
Search output voltage
VFE02
ment
V2 = 0.5VDC
V2 = –0.5VDC
V2 = 0.5VDC
V2 = –0.5VDC
V2 = 10kHz, 40mVp-p
Difference in gain when
SD = 00 and SD = 25
V2 = 10Hz, –500mVp-p
GTEO = 20 log (Vout/Vin)
∗(VCC + DGND)/2 = SENS
value when E4 is varied.
V1 = –0.5VDC
V1 = 0.5VDC
V1 = –0.5VDC
V1 = 0.5VDC
SG = 10kHz, 40mVp-p
Difference in gain when
SD = 00 and SD = 08
V1 = 10Hz, 100mVp-p
GFEO = 20 log (Vout/Vin)
360
–640
1.2
2.0
11.6
39
360
–640
1.2
2.0
18.0
–24
8
waveform and measurement Min.
Bias condition Measure- Description of output
13.3
50
21.0
–17
19
Typ.
640
–360
–1.2
–2.0
–39
17.6
61
640
–360
–1.2
–2.0
–35
24.0
–8
27
Max.
mV
mV
V
V
V
V
dB
dB
mV
mV
mV
V
V
V
V
dB
dB
mA
mA
Unit
(Ta = 25°C, VCC = 2.5V, VEE = –2.5V, D. GND = –2.5V)
E1 E2 E3 E4 point
method
00
10, 36
SD
O
S1 S2 S3 S4 S5 S6 S7 S8 S9
SW condition
18
17
16
15
14
13
12
11
10
9
8
7
6
5
Max. output voltage
VFEOF
Feedthrough
VFE01
GFEO
DC voltage gain
3
Max. output voltage
IEE
Current consumption
2
FOCUS SERVO
TRACKING SERVO
4
ICC
Symbol
Current consumption
Item
1
No.
Electrical Characteristics
CXA1372BQ/BS
– 10 –
Symbol
25
VSL03
Max. output voltage
27
26
33
VSSTOP
VSENS
VCOUT
VFOKT
SSTOP threshold
value
SENS Low level
COUT Low level
FOK threshold value
33
33
VFOKL
FFOK
Low level voltage
Max. operating frequency
36
37
35
33
27
14
VFOKH
30 ∗
22
VKICK2
Kick output voltage
14
23
VKICK1
Kick output voltage
14
14
14
14
14
14
27
VSL04
∗
27
Max. output voltage
25
25
VSL02
Max. output voltage
O
25
00
VSLOF
Feedthrough
VSL01
25
GSLO
DC voltage gain
Max. output voltage
20
10
ment
V4 = 1Vp-p – 375mVDC
(VCC + DGND)/2 = value
between Pins 39 and 40
when V4 is varied.
∗(VCC + DGND)/2 = SENS
value when E1 is varied.
V5 = –1.0VDC
V5 = 1.0VDC
V5 = –1.0VDC
V5 = 1.0VDC
V5 = 10kHz, 100mVp-p
Difference in gain when
SD = 00 and SD = 25
V5 = 10Hz, 20mVp-p
Open loop gain
∗(VCC + DGND)/2 = SENS
value when E2 is varied.
∗(VCC + DGND)/2 = SENS
value when E3 is varied.
–25
0
26
–26
Typ.
45
2.2
–400 –356
–40
450
–750
2.0
2.0
50
–20
7
–45
waveform and measurement Min.
method
Bias condition Measure- Description of output
E1 E2 E3 E4 point
∗
10
27
SD
VTZC
O
S1 S2 S3 S4 S5 S6 S7 S8 S9
SW condition
TZC threshold value
ATSC threshold value VATSC2
ATSC threshold value VATSC1
Item
High level voltage
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
TRACKING
SERVO
SLED SERVO
FOK
No.
–1.8
–330
–2.0
–2.0
–10
750
–450
–2.0
–2.0
–34
20
45
–7
Max.
kHz
V
V
mV
V
V
mV
mV
mV
V
V
V
V
dB
dB
mV
mV
mV
Unit
CXA1372BQ/BS
– 11 –
VDFCT1
VDFCT2
DEFM1
DEFM2
VEFMH
Min. input operating
voltage
Max. input operating
voltage
Duty 1
Duty 2
High level output
voltage
52
VEFM2
FDFCT2
Max. operating
frequency
54
FDFCT1
Min. operating
frequency
Max. input operating
voltage
VDFCTL
Low level output
voltage
VEFM1
VDFCTH
High level output
voltage
Min. input operating
voltage
O
VMIR2
Max. input operating
voltage
53
31
O
VMIR1
Min. input operating
voltage
VEFML
30
FMIR
Max. operating
frequency
O
O
O O
O O
A
A
32
32
31
30
30
30
30
30
29
29
29
29
VMIRL
Low level voltage
ment
29
S1 S2 S3 S4 S5 S6 S7 S8 S9
E1 E2 E3 E4 point
V4 = 750kHz
V4 = 750kHz, 0.7Vp-p
V4 = 750kHz,
0.7Vp-p + 0.25VDC
V4 = 750kHz, 0.7Vp-p
V4 = 50Hz + 375mVDC
(square wave)
V4 = 0.8Vp-p + 375mVDC
V4 = 10kHz – 0.4VDC
V4 = 800mVp-p – 0.4VDC
V4 = 10kHz
1.0Vp-p – 0.4VDC
1.8
1.2
0
50
0.12
–1.2
100
Vp-p
Vp-p
V
V
mV
mV
Vp-p
kHz
kHz
V
V
Vp-p
Vp-p
kHz
V
V
Unit
–50
50
0.5
1
–2.0
0.3
–2.0
Max.
Vp-p
0
Typ.
1.8
2.5
1.8
1.8
30
1.8
waveform and measurement Min.
method
Bias condition Measure- Description of output
VMIRH
SD
High level voltage
SW condition
Symbol
Item
Low level output
voltage
51
50
49
48
47
46
45
44
43
42
41
40
39
38
MIRROR
DEFECT
EFM
No.
CXA1372BQ/BS
CXA1372BQ/BS
Electric Characteristics Measurement Circuit
A
DVcc
0.01µ
DGND
1M
10k
10k
1k
DGND
Vcc DGND
10k
35
34
33
32
31
30
29
28
27
26
CC2
CC1
FOK
EFM
ASY
DFCT
MIRR
DGND
SENS
C. OUT
10k
36
DVcc
DGND
3300P
38 CP
40 RFO
CLK
22
CLK
LOCK
21
DIRC
20
SSTOP 18
E2
GND
GND
240k
44 TDFCT
FSET 16
510k
0.1µ
AC
ISET 17
43 TE
V2
A
AVEE 19
42 TZC
5.1k
SL– 15
E3
60k
45 ATSC
46 FZC
SLO 14
47 FE
SL+ 13
S7
E4
GND
FLB
FEO
FE–
SRCH
TGU
TG2
AVcc
TAO
TA–
1
2
3
4
5
6
7
8
9
10
11
100k
12
1000P
100k
A
S2
S1
S5
S4
200k
S3
200k
GND
GND
13k
130
AVcc
GND
GND
– 12 –
+
V5
AC
0.033µ
13k
GND
FS3
GND
FGD
48 FDFCT
AC
130 S6
V1
0.1µ
+
VC
GND
GND
130
13k
GND
+
XLT
41 DVEE
A
GND
23
AC
0.1µ
DVEE
AC V3
GND
GND
XLT
39 RFI
V4
+
DATA
DATA 24
E1
1000P
Vcc GND GND AVEE Vcc Vcc
37 CB
DGND
25
XRST
A
10k
10k
S8
S9
DGND DGND DGND Vcc Vcc Vcc
3300P
CXA1372BQ/BS
Description of Functions
Focus Servo
1.2k
56k
FZC
FZC
46
FE
10k
47
22k
2200p
DFCT
FE
470k
20k
48k
FEO
Focus Phase
Compensation
48
FS4
FDFCT
0.1µ
FOCUS COIL
5
100k
FGD
2
FS2
0.1µ
FE–
40k
46k
6
3
FS3
40k
580k
11µ
120k
22µ
10k
FS3
ISET 120k
17
50k
FS1
FLB
4
0.1µ
FSET
16
510k
DGND
SRCH
7
0.01µ
4.7µ
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 20kΩ and 48kΩ resistance;
however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the
internal 470kΩ resistance and the capacitance connected to Pin 48. When this DFCT countermeasure circuit is
not used, leave Pin 48 open.
When FS3 is ON, the high-frequency gain can be cut by forming a low-frequency time constant through a
capacitor connected between Pins 2 and 3 and the internal resistor.
The capacitor connected between Pin 4 and GND is a time constant to boost the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510kΩ is
connected to Pin 16.
The focus search level is approximately ±1.1Vp-p when using the constants indicated in the above figure. This
level is inversely proportional to the resistance connected between Pin 17 and GND. However, changing this
resistance also changes the level of the track jump and sled kick as well.
The FZC comparator inverted input is set to 2% of VCC and VC (Pin 1); (VCC – VC) × 2%.
∗ 510kΩ resistance is recommended for Pin 16.
– 13 –
CXA1372BQ/BS
Tracking Sled Servo
100k
0.022µ
TZC
42
18
SSTOP
SSTOP
TZC
100k
1k
100k
SLED MOTOR
SLO
M
14
0.047µ ATSC
45
0.015µ
1k
ATSC
22µA
1k
BPF
10k
43
TE
DFCT
470k
22k
TDFCT
TG1
TM1
TGU
8
20k
TG2 TG2
0.033µ
66P
Tracking
Phase
Compensation
10k
3.3µ
SL+
22µ
TM2
12
TM3
TG1
10k
13
TM4
680K
680k
44
0.1µ
TM5 22µA
11µA
100k
8.2k
15
TM6
TE
120k
SL–
82k
TA–
15k
100k
11µA
90k
TAO
TRACKING
COIL
11
TM7
9
470k
FSET
16
510k
0.01µ
The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 8 and 9 is a time constant to cut the high-frequency gain when TG2 is
OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance connected to Pin 16.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 ( or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and
GND. When this resistance is 120kΩ:
TM3 ( or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
This current value is almost inversely proportional to the resistance and the variable range is approximately 5
to 40µA at TM3.
SSTOP is the ON/OFF detection signal for the limit SW of the linear motor's innermost track.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (470kΩ) and the capacitor connected to Pin 44.
TM-1 was ON at DFCT in the CXA1082 and CXA1182, but it does not operate in the CXA1372.
– 14 –
CXA1372BQ/BS
Focus OK circuit
VCC
RFO
20k
40
RF signal
C5
0.01µ
RFI
54k
×1
VG
39
33 FOK
15k
92k
0.625V
FOCUS OK AMP
FOCUS OK
COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 39 from Pin 40 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output reverses when VRFI – VRFO ≈ –0.37V.
Note that, C5 determines the time constants of the HPF for the EFM comparator and mirror circuit and the LPF
of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block
error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented.
EFM comparator
EFM comparator changes RF signal to a binary value. The asymmetry generated due to variations in disc
manufacturing cannot be eliminated by the AC coupling alone. Therefore, the reference voltage of EFM
comparator is controlled through 1 and 0 that are in approximately equal numbers in the binary EFM signals.
VC
AUTO ASYMMETRY
CONTROL AMP
100k
ASY
20k
×6
C8
Vcc
40k
RFI
R8
40k
R9
31
AUTO ASYMMETRY
BUFFER
DGND = 0V
32
39
C9
CMOS
BUFFER
CXD2500
EFM
EFM COMPARATOR
As this comparator is a current SW type, each of the High and Low levels is not equal to the power supply
voltage. A feedback has to be applied through the CMOS buffer.
R8, R9, C8, and C9 form a LPF to obtain (VCC + DGND)/2V. When fc (cut-off frequency) exceeds 500Hz, the
EFM low-frequency components leak badly, and the block error rate worsens.
– 15 –
CXA1372BQ/BS
DEFECT circuit
After inversion, RFI signal is bottom held by means of the long and short time constants. The long timeconstant bottom hold keeps the mirror level prior to the defect.
The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms, and this is
differentiated and level-shifted through the AC coupling circuit.
The long and short time-constant signals are compared to generate at mirror defect detection signal.
0.033µ
CC1
34
RFO 40
a
×2
b
CC2
35
c
e
30 DFCT
d
DEFECT AMP
DEFECT BOTTOM
HOLD
37
CB
a
RFO
b
DEFECT
AMP
c
BOTTOM
HOLD (1);
Solid line CC1
e
DEFECT
DEFECT COMPARATOR
0.01µ
d
H
L
– 16 –
BOTTOM
HOLD (2);
Dotted line CC2
CXA1372BQ/BS
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the
rotation cycle envelope fluctuation.
RFO
MIRROR HOLD AMP
0.033µ
38
39
RFI
× 2.2
G
PEAK &
BOTTOM
HOLD
H
CP
×1
I
J
K
MIRROR AMP
29
20k
MIRROR
COMPARATOR
MIRR
DGND
RFO
0V
G
(RFI)
0V
H
(PEAK HOLD)
0V
I
(BOTTOM HOLD)
0V
J
K
(MIRROR HOLD)
H
MIRR
L
Through differential amplification of the peak and bottom hold signals H and I, mirror output can be obtained by
comparing an envelope signal J (demodulated to DC) to signal K for Which peak holding at a level 2/3 that of
the maximum was performed with a large time constant. In other words, mirror output is low for tracks on the
disc and high for the area between tracks (the MIRR areas). In addition, a high signal is output when a defect
is detected. The mirror hold time constant must be sufficiently large in comparison with the traverse signal.
– 17 –
CXA1372BQ/BS
Commands
The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by
2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F.
Commands for the CXA1372 can be broadly divided into four groups ranging in value from $0X to $3X.
1. $0X (“FZC” at SENS (Pin 27))
These commands are related to focus servo control.
The bit configuration is as shown below.
D7
0
D6
0
D5
0
D4
0
D3
FS4
D2
FS3
D1
FS2
D0
FS1
Four focus-servo related switches exist: FS1 to FS4 corresponding to D0 to D3, respectively.
$00
$02
When FS1 = 0, Pin 7 is charged to (22µA – 11µA) × 50kΩ = 0.55V.
If FS2 = 0, this voltage is no longer transferred, and the output at Pin 5 becomes 0V.
From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 5. This voltage level is obtained by equation 1 below.
(22µA – 11µA) × 50kΩ ×
$03
resistance between Pins 5 and 6
50kΩ
Equation 1
....
From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 7 decreases with the time as
shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 7 when FS1 gose from 0 → 1
This time constant is obtained with the 50kΩ resistance and an external capacitor.
By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03 (Voltage at Pin 5)
– 18 –
CXA1372BQ/BS
1-1. FS4
This switch is provided between the focus error input (Pin 47) and the focus phase compensation, and is in
charge of turning the focus servo ON and OFF.
$00
→ $08
Focus OFF ← Focus ON
1-2. Procedure of focus activation
For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 5) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.
A
t
Fig. 3. S-curve
The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and
turning the focus servo switch ON are performed when the focus S-curve transits the point A indicated in Fig. 3.
To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 27) as the point A transit signal.
Focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
(20ms) (200ms)
$02
($00)
$03
$08
Drive voltage
∗ The broken lines in the figure
indicate the voltage assuming
the signal is not in focus.
Focus error
SENS pin
(FZC)
The instant the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart
– 19 –
CXA1372BQ/BS
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ↓ ?
Transfer $08
NO
YES
F. OK ?
F. OK ?
NO
NO
YES
YES
Transfer $08
FZC ↓ ?
NO
YES
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences
1-3. SENS (Pin 27)
The output of the SENS pin differs depending on the input data as shown below.
$0X: FZC
$1X: AS
$2X: TZC
$3X: SSTOP
$4X to 7X: HIGH-Z
2. $1X (“AS” at SENS (Pin 27))
These commands deal with switching TG1 and TG2 ON/OFF.
The bit configuration is as follows
D7
D6
D5
D4
D3
D2
D1
0
0
0
1
ANTI
Break
TG2
SHOCK circuit
ON/OFF ON/OFF
D0
TG1
TG1, TG2
The purpose of these switches is to switch the tracking servo gain Up/Normal. The brake circuit (TM7) is to
prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually
though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by
the servo motor exceeding the linear range after a 100 or 10-track jump.
When the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc
and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the
tracking error is 180˚out-of-phase to cut the unneeded portion of the tracking error and apply braking.
– 20 –
CXA1372BQ/BS
[∗A]
[∗B]
Waveform
Shaping
Envelope
Detection
RFI 39
[∗D]
Tracking error
(TZC) 42
D2
[∗E]
Waveform
Shaping
(MIRR)
[∗C]
[∗F]
DQ
[∗G]
BRK
TM7
Low: open
High: make
CK
[∗H]
Edge Detection
(Latch)
Fig. 6. TM7 operation (brake circuit)
From inner to outer track
From outer to inner track
[∗A]
[∗B]
[∗C]
("MIRR")
[∗D]
("TZC")
[∗E]
[∗F]
[∗G]
[∗H]
Braking is
applied from
here.
0V
Fig. 7. Internal waveform
3. $2X (“TZC” at SENS (Pin 27))
These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Tracking
control
00: OFF
01: Servo ON
10: F-JUMP
11: R-JUMP
↓
TM1, TM3, TM4
– 21 –
Sled
control
00: OFF
01: Servo ON
10: F-FAST FORWARD
11: R-FAST FORWARD
↓
TM2, TM5, TM6
CXA1372BQ/BS
DIRC (Pin 20) and 1 Track Jump
Normally, an acceleration pulse is applied for a 1-track jump. Then a deceleration pulse is given for a specified
time observing the tracking error from the moment it passes point 0, and tracking servo is turned ON again.
For the 100-track jump to be explained in the next item, as long as the number of tracks is about 100 there is
no problem. However a 1-track jump must be performed here, which requires the above complicated
procedure. For the 1-track jump in CD players, both the acceleration and deceleration take about 300 to
400µs. When software is used to execute this operation, it turns out as shown in the flow chart of Fig. 9.
Actually, it takes some time to transfer data.
Deceleration
Pulse waveform
Acceleration
Tracking error
Fig. 8. Pulse waveform and tracking error of 1-track jump
TR: REV
$2C transfer latch
SL: OFF
TZC ↓ ?
AAAA
AAAA
SL: OFF
TZC ↓ ?
NO
YES
Latch
Execute
NO
YES
Execute
DIRC = L
Timer (0.3ms)
$25 transfer latch
SL: OFF
TR: FWD
$28 transfer only
AAA
AAA
TR: REV
$2C transfer latch
Execute
TR: FWD
SL: OFF
Timer (0.3ms)
TR: ON
SL: ON
DIRC = H
Execute
Fig. 9. 1-track jump not using DIRC (Pin 20)
TR: ON
SL: ON
Fig. 10. 1-track jump with DIRC (Pin 20)
The DIRC (Direct Control) pin was provided in this IC to facilitate the 1-track jump operation. Conduct the
following process to perform 1-track jump using DIRC (normal High).
(a) Acceleration pulse is output. ($2C for REV or $28 for FWD).
(b) With TZC ↓ (or TZC ↑), set DIRC to Low. (SENS Pin 27 outputs "TZC"). As the jump pulse polarity is
inverted, deceleration is applied.
(c) Set DIRC to High after a specific time.
Both the tracking servo and sled servo are switched ON automatically.
As a result, the track jump turns out as shown in the flow chart of Fig. 10 and the two serial data transfers
can be omitted.
– 22 –
CXA1372BQ/BS
4. $3X
This command selects the focus search and sled kick levels.
D0, D1 ..... Sled, NORMAL feed, high-speed feed
D2, D3 ..... Focus search level selection
Focus search level
D7 D6 D5 D4
0
0
1
1
Sled kick level
Relative
value
D3
(PS4)
D2
(PS3)
D1
(PS2)
D0
(PS1)
0
0
0
0
±1
0
1
0
1
±2
1
0
1
0
±3
1
1
1
1
±4
– 23 –
CXA1372BQ/BS
Parallel Direct Interface
1. DIRC
$28 latch
$2C latch
XLT
DIRC
ON
FWD JUMP
OFF
REV JUMP
OFF
ON
TRACK SERVO
ON
SLED SERVO
ON
OFF
OFF
2. LOCK (Sled overrun prevention circuit)
LOCK
SLED SERVO
ON
TG1, TG2
ON
OFF
OFF
TRACKING GAIN
UP
DOWN
– 24 –
CXA1372BQ/BS
CPU Serial Interface Timing Chart
D0
DATA
D1
tWCK
D2
D3
tWCK
tSU
D4
D5
D6
D7
th
CLK
1/fck
tD
XLT
tWL
(DVCC – DGND = 4.5 to 5.5V)
Item
Symbol
Min.
Typ.
Max.
Unit
1
MHz
Clock frequency
fck
Clock pulse width
fwck
500
ns
Setup time
tsu
th
tD
tWL
500
ns
500
ns
1000
ns
1000
ns
Hold time
Delay time
Latch pulse width
System Control
Data
Address
Item
D3
D7 D6 D5 D4
Focus control
0
0
0
FS4
0 Focus
ON
Tracking
control
0
0
0
1 Anti-shock
Tracking mode 0
0
1
0
0
0
1
PS4
1 Focus
search + 2
Select
D2
D1
FS3
Gain
Down
Brake
ON
∗
Tracking mode 2
D0
FS2
Search
ON
FS1
Search
Up
TG2
Gain set ∗1
TG1
Sled mode ∗3
PS3
Focus
search + 1
PS2
Sled kick + 2
SENS
output
FZC
A. S
TZC
PS1
Sled kick + 1
SSTOP
∗1 Gain set
TG1 and TG2 can be set independently.
When the anti-shock is at 1 (00011xxx), both TG1 and TG2 are inverted when the internal anti-shock is at High.
∗2 Tracking mode
∗3 Sled mode
D3
D2
D1
D0
OFF
0
0
OFF
0
0
ON
0
1
ON
0
1
FWD JUMP
1
0
FWD MOVE
1
0
REV JUMP
1
1
REV MOVE
1
1
– 25 –
CXA1372BQ/BS
Serial Data Truth Table
Hex.
Serial data
FS = 4 3 2 1
FOCUS CONTROL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
AS = 0
TRACKING CONTROL
TG = 2 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AS = 1
TG = 2 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIRC = 1 DIRC = 0
TM = 654321
654321
TRACKING MODE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
000000
000010
010000
100000
000001
000011
010001
100001
000100
000110
010100
100100
001000
001010
011000
101000
– 26 –
001000
001010
011000
101000
000100
000110
010100
100100
001000
001010
011000
101000
000100
000110
010100
100100
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
DIRC = 1
654321
000011
000011
100001
100001
000011
000011
100001
100001
000011
000011
100001
100001
000011
000011
100001
100001
GND
SSTOP
GND
SPIND-D
GND
SLED-D
GND
FOCUS-D
GND
TRACK-D
TD
GND
SPD
FD
SLD
R1
R1
R1
GND
C23
C10
C26
R10
GND
C27
GND
R6
C28
R7
GND
C9
RF
C15
C16
C12
LDON
C14
FE
CC1
5
TGU
TG2
AVCC
TA0
TA–
8
9
10
11
12
R14
R13
R12
GND
R4 R3
34
28
27
26
25
C.OUT
XRST
29
SENS
MIRR
31
30
ASY
32
33
DFCT
EFM
36
35
DGND
DFCT
PCM
MIRR
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
GND
MD2
MDS
LOCK
NC
VCOO
5
6
7
8
CXD2500AQ
DOUT
MDP
4
NC
NC
NC
VPCO
VCKI
FILO
FILI
PCO
13
14
15
16
17
18
19
20
AVDD
GND
GND
C4M
57
43
42
41
RFCK
GFS
XPLCK
MNT3
45
MNT2
44
46
MNT1
C2PO
49
48
47
MNT0
50
52
51
VSS
APTL
APTR
54
53
XTAI
55
56
XTAO
XTSL
FSTT
58
59
60
61
62
63
64
XRAOF
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
200p
1M
RF
AVDD
23
24
CLTV
22
AVSS
VSS
21
PDO
12
TEST
11
10
VCOI
EMPH
MON
3
9
WFCK
FSW
2
C16M
SBSO
SCOR
FOK
1
GTOP
UGFS
XPLCK
GFS
RFCK
XRAOF
DOUT
WFCK
GND
GND GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
13 14 15 16 17 18 19 20 21 22 23 24
GND
SRCH
FE–
FEO
7
6
CXA1372BQ
CC2
FOK
FS3
3
FLB
FGD
4
DVCC
VC
2
SL0
1
FDFCT
SL+
C17
GND GND
VCC
48 47 46 45 44 43 42 41 40 39 38 37
FZC
SL–
GND
GND
MIRR
BIAS
FE
C11
ATSC
FSET
VDD
CLKO
ASYI
TE
XLTO
ASYO
TE
C13
TDFCT
ISET
MUTE
DATO
ASYE
GND
VCC
DVEE
DIRC
GND
GND
RF
TE
SSTOP
SQCK
SEIN
PSSL
FE
WDCK (48)
TZC
AVEE
SUBQ
CLOK
RV2
CP
GND
GND
LRCK (64)
VO
RFO
SCOR
CNIN
NC
GND
GND
LOCK
GFS
VDD
LRCK (48)
VSS
CB
CLK
XLAT
VDD
GND
RFI
XLT
DATA
DATA (48)
VCC
CLK
DATA
XRST
BCLK (48)
C2PO
XLT
XRST
SENS
DATA (64)
MUTE
DATA
SENS
MUTE
BCLK (64)
BCLK
RV1
GND
FOK
SQCK
DATA
GND
EXCK
XUGF
LRCK
GND GND GND
GND
LDON
SQSO
GTOP
WDCK
– 27 –
DEMP
GND
GND
Application Circuit
GND
MNT3
MNT2
MNT1
MNT0
GND
CXA1372BQ/BS
CXA1372BQ/BS
Notes on Operation
1. Connection of the power supply pin
Vcc
VEE
VC
dual ±5V power supplies
+5V
–5V
0V
single 5V power supplies
+5V
0V
VC
2. FSET pin
The FSET pin determines the cut-off frequency fc for the focus and tracking high-frequency phase compensation.
3. ISET pin
ISET current = 1.27V/R
= Focus search current
= Tracking jump current
= 1/2 sled kick current
4. The tracking amplifier input is clamped at 1VBE to prevent overinput.
5. FE (focus error) and TE (tracking error) gain changing method
(1) High gain: Resistance between FE pins (Pins 5 and 6) 100kΩ → Large
Resistance between TA pins (Pins 11 and 12) 100kΩ → Large
(2) Low gain: A signal, whose resistance is divided, is input to FE and TE.
FE
TE
6. Input voltage of microcomputer interface Pins 20 to 25, should be set as follows.
VIH VCC × 90% or more
VIL VCC × 10% or less
7. Focus OK circuit
(1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
(2) The equivalent circuit of FOK output pin is as follows.
VCC
20k
FOK
33
50k
RL
100k
VCC
DGND
FOK comparator output is:
Output voltage High: VFOKH ≈ near Vcc
Output voltage Low: VFOKL ≈ Vsat (NPN) + DGND
DGND
– 28 –
CXA1372BQ/BS
8. Mirror Circuit
(1) The equivalent circuit of MIRR output pin is as follows.
Vcc
MIRR
29
20k
VEE
RL
DGND
DGND
MIRR comparator output is:
Output voltage High: VMIRH ≈ VCC – Vsat (LPNP)
Output voltage Low: VMIRL ≈ near DGND
9. EFM Comparator
(1) Note that EFM duty varies when the CXA1372 Vcc differs from that of DSP IC (such as the CXD2500).
(2) The equivalent circuit of the EFM output pin is as follows.
4.8k
50
EFM
32
RL
700µA∗
2mA∗
DGND
∗ When the power supply current between Vcc and DGND is 5V.
EFM comparator output is:
Output voltage High: VEFMH ≈ VCC – VBE (NPN)
Output voltage Low: VEFML ≈ VCC – 4.8 (kΩ) × 700 (µA) – VBE (NPN)
– 29 –
TRACKING
FOCUS
Mode
5
5
11
0C
0C
25
O
O
1.2kHz gain
1.2kHz phase
11
11
11
25
25
13
25
13
O
O
O
1.2kHz phase
2.7kHz gain
2.7kHz phase
1.2kHz gain
5
O
ment
waveform and measurement Min.
method
When CFLB = 0.1µF
Bias condition Measure- Description of output
E1 E2 E3 E4 point
08
5
SD
08
O
S1 S2 S3 S4 S5 S6 S7 S8 S9
SW condition
O
Symbol
1.2kHz phase
1.2kHz gain
Item
Standard Circuit Design Data for Focus/Tracking Internal Phase Compensation
–130
26.5
–125
13
63
16
63
21.5
Typ.
Max.
deg
dB
deg
dB
deg
dB
deg
dB
Unit
CXA1372BQ/BS
– 30 –
CXA1372BQ/BS
Example of Representative Characteristics
FOCUS frequency characteristics
40
180
35
135
G – Gain [dB]
90
G
45
25
0
20
φ
15
–45
10
–90
NORMAL
GAIN DOWN
5
0
φ – Phase [degree]
CFLB = 0.1µ
CFGD = 0.1µ
30
–135
–180
101
102
103
104
105
f – Frequency [Hz]
Tracking frequency characteristics
180
40
120
30
G
60
10
0
φ
–60
0
NORMAL
GAIN UP
–10
–20
101
–120
–180
102
103
f – Frequency [Hz]
– 31 –
104
105
φ – Phase [degree]
G – Gain [dB]
CTGU = 0.033µ
20
CXA1372BQ/BS
Package Outline
Unit: mm
CXA1372BQ
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
48
13
13.5
37
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
SONY CODE
QFP-48P-L04
EIAJ CODE
∗QFP048-P-1212-B
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
CXA1372BS
+ 0.1
0.05
0.25 –
48PIN SDIP (PLASTIC) 600mil
+ 0.4
43.2 – 0.1
25
15.24
+ 0.3
13.0 – 0.1
48
1
0° to 15°
24
0.5 MIN
3.0 MIN
0.5 ± 0.1
0.9 ± 0.15
+ 0.4
4.6 – 0.1
1.778
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SDIP-48P-02
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SDIP048-P-0600-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
5.1g
JEDEC CODE
– 32 –