CXA3117AN IF Amplifier for M-ary FSK Pagers Description The CXA3117AN is a low current consumption FM IF amplifier which employs the newest bipolar process. It is suitable for M-ary FSK pagers. Features • Low current consumption: 1.1mA (typ. at VCC = 1.4V) • Low voltage operation: VCC = 1.1 to 4.0V • Small package 24-pin SSOP • Second mixer and oscillator • Needless of IF decoupling capacitor • Reference power supply for operational amplifier and comparator • Bit rate filter with variable cut-off • Misoperation prevention function for continuous data • RSSI function • IF input, VCC standard • Quick charge by the detector output sense method 24 pin SSOP (Plastic) Structure Bipolar silicon monolithic IC Applications • M-ary FSK pagers • Double conversion pagers Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation 7.0 V VCC Topr –20 to +75 °C Tstg –65 to +150 °C PD 417 mW Operating Condition Supply voltage VCC 1.1 to 4.0 V MIX IN GND REG OUT REG CONT LVA OUT NRZ OUT CHARGE B.S. AUDIO L.C. OUT CHG OFF RSSI Block Diagram and Pin Configuration 24 23 22 21 20 19 18 17 16 15 14 13 RSSI LEVEL COMP LVA GND REG MIX CHARGE QUAD_DET MIX OUT VCC IF IN TH CONT 7 8 9 10 11 12 FIL SW 6 C3 5 C2 4 C1 3 QUAD 2 FILTER FSK REF 1 OSC OUT IF_LIM OSC IN OSC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97220A8Z CXA3117AN Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description VCC 1 OSC IN 15k 1.4V 300 1 72 15k 2 2 OSC OUT Connects the external parts of crystal oscillator circuit. A capacitor and crystal oscillator are connected to these pins and VCC. 0.7V GND VCC 1.5k 3 3 MIX OUT Mixer output. Connect a 455kHz ceramic filter between this pin and IF IN. 1.3V GND 4 VCC Power supply. VCC 1.5k 5 IF IN 1.4V 20k 20k 1.5k 5 IF limiter amplifier input. GND VCC 6 TH CONT — Determines the level comparator threshold value. Threshold value can be adjusted by inserting the resistor between Pin 6 and VCC. Normally, short to VCC. 6 25k GND VCC 7 FSK REF 0.2V Connects the capacitor that determines the low cut-off frequency for the entire system. 72 7 GND –2– CXA3117AN Pin No. Symbol Pin voltage Equivalent circuit Description VCC 20k 8 QUAD 1.4V 22k Connects the phase shifter of FM detector circuit. 8 20p GND VCC 9 10 11 C1 C2 C3 0.2V Connects the capacitor that determines the LPF cut-off. 9 35k 10 11 50k GND 12 72 Switches the LPF cut-off. Cut-off is decreased by setting this pin high. (Applied voltage range: –0.5V to +7.0V) 20k 12 FIL SW — 140k GND VCC 7k 13 RSSI 0.1V 7k RSSI circuit output. 13 70k GND 14 72 20k 14 CHG OFF Sets off the quick charge circuit current. The charge current is off by setting Pin 18 low and Pin 14 high. — 100k GND –3– CXA3117AN Pin No. Symbol Pin voltage Equivalent circuit Description 15 15 19 20 L.C. OUT NRZ OUT LVA OUT 72 19 — — — Level comparator, NRZ comparator and LVA comparator outputs. They are open collectors. (Applied voltage range: –0.5V to +7.0V) 20 GND VCC 72 16 AUDIO 0.2V Level comparator and NRZ comparator inputs. The filter circuit output is connected. 16 72 GND 17 72 Controls the battery saving. Setting this pin low suspends the operation of IC. (Applied voltage range: –0.5V to +7.0V) 20k 17 B.S. — 140k GND 20k Controls the speed of the quick charge circuit. Set this pin high to execute the quick charge. (Applied voltage range: –0.5V to +7.0V) 18 18 CHARGE — 100k GND VCC 21 REG CONT — Output for internal constant-voltage source amplifier. Connect the base of PNP transistor. (Current capacity: 100µA) 72 21 GND VCC 22 REG OUT 1.0V 78k Constant-voltage source output. Controlled to maintain 1.0V. 1k 22 22k GND 23 GND — Ground –4– CXA3117AN Pin No. Symbol Pin voltage Equivalent circuit Description VCC 2k 4.16k 4.16k 24 MIX IN 1.4V Mixer input. 24 GND Electrical Characteristics (VCC = 1.4V, Ta = 25°C, Fs = 21.7MHz, FMOD = 1.6kHz, FDEV = 4.8kHz, AMMOD = 30%) Item Symbol Conditions Min. Typ. Max. Unit Current consumption ICC Measurement circuit 1, V2 = 1.0V 0.7 1.1 1.35 mA Current consumption ICCS Measurement circuit 1, V2 = 0V — 6 10 µA AM rejection ratio AMRR Measurement circuit 2, 30k LPF 25 — — dB NRZ output saturation voltage VSATNRZ Measurement circuit 4, Vin = 0.3V — — 0.4 V NRZ output leak current ILNRZ Measurement circuit 3, Vin = 0.1V — — 5.0 µA NRZ hysteresis width VTWNRZ Measurement circuit 3, Vin = 0.1 to 0.3V 0 10 20 mV VB output current IOUT Measurement circuit 5 100 — — µA VB output saturation voltage VSATVB Measurement circuit 5 — — 0.4 V REG OUT voltage VREG Output current 0µA 0.95 1.00 1.05 V LVA operating voltage VLVA Measurement circuit 6, V1 = 1.4 to 1.0V 1.05 1.10 1.15 V LVA output leak current ILLVA Measurement circuit 6, V1 = 1.0V — — 5.0 µA LVA output saturation voltage VSATLVA Measurement circuit 7 — — 0.4 V Detector output voltage VODET Measurement circuit 2 50 63 80 mVrms Logic input voltage high level VTHBSV — 0.9 — — V Logic input voltage low level VTLBSV — — — 0.35 V Limiting sensitivity VIN (LIM) Measurement circuit 2, Data filter fc = 2.4kHz — –108 — dBm Detector output level ratio deviation to level comparator window width VLCWR When Pin 6 is shorted to Vcc –15 0 +15 % Level comparator output saturation voltage VSATLC Measurement circuit 9 — — 0.4 V Level comparator output leak current ILLC Measurement circuit 8 — — 5.0 µA RSSI output offset VORSSI Measurement circuit 10 — 150 300 mV Mixer input resistance RINLIM — 1.6 2.0 2.4 kΩ Mixer output resistance ROUTMIX — 1.2 1.5 1.8 kΩ IF limiter input resistance RINLIM — 1.2 1.5 1.8 kΩ –5– CXA3117AN Electrical Characteristics Measurement Circuit Vin 10p to 120p 1.8µ 1000p 1 2 22 21 20 19 3 4 5 6 18 17 7 8 16 15 14 13 24 23 22 21 20 19 9 11 12 1 2 22p 3 4 10 VCC 15p VCC V1 1.4V Measurement circuit 1 24 23 22 21 20 19 1 3 4 2 5 6 18 17 7 8 6 16 15 14 8 9 10 11 12 1200p 7 1µ 8.2k V1 1.4V Measurement circuit 2 50µA V2 1V 100k 5 V2 1V 16 15 14 13 24 23 22 21 20 19 9 11 12 1 3 4 10 2 5 6 18 17 16 15 14 13 8 9 10 11 12 7 Vin VCC 13 18 17 1200p 1200p V2 24 23 V2 1V Vin VCC V1 1.4V Measurement circuit 3 V1 1.4V Measurement circuit 4 –6– CXA3117AN 100µA GND V3 0.5V V2 1V 24 23 22 21 20 19 1 3 4 2 VCC 5 6 18 17 7 8 V2 1V 100k 16 15 14 13 24 23 22 21 20 19 18 17 16 15 14 13 9 11 12 1 4 5 6 8 9 10 11 12 16 15 14 13 9 11 12 10 2 3 VCC V1 1.4V 7 V1 1.4 to 1.0V GND Measurement circuit 5 50µA V2 1V 24 23 22 21 20 1 3 4 2 VCC Measurement circuit 6 5 19 18 6 7 V2 1V 17 16 15 8 9 10 14 13 11 12 24 23 22 21 20 19 1 3 4 2 Measurement circuit 7 V2 1V 24 23 22 21 20 19 1 3 4 2 VCC 5 6 7 8 10 V1 1.4V Measurement circuit 8 50µA 100P V2 1V 13 18 17 16 15 14 8 9 10 11 12 7 6 18 17 Vin 0.2V VCC V1 1.4V 5 100k Vin 0.1V 24 23 22 21 20 1 3 4 2 5 19 18 6 7 15 14 9 10 11 12 8 VCC V1 1.4V V1 1.4V Measurement circuit 9 Measurement circuit 10 –7– 13 17 16 VCC GND GND Application circuit GND SMA L1 1.8µH RF 1 –8– XTAL C4 22p OSC 2 GND C5 15p MIX 23 REG GND C6 10µ C3 GND 1000p 24 C1 10p to 120p C7 10µ 3 22 21 VB_ REG GND 4 C8 0.01µ 20 18 S3 17 GND C10 1µ DISC (100p + 1000p) C11 1100p GND 9 S2 11 12 GND (1200p + 220p) C13 1420p S1 RSSI 13 FIL_SW CHG_ OFF 14 RSSI GND C14 100p GND GND C12 680p 10 R7 6.8k L.C. OUT 15 6 8 AUDIO FILTER 7 LEVEL COMP 16 R8 100k QUAD_DET NRZ_ CHARGE BS COMP CHARGE 19 R6 100k S4 GND LEVEL IF_LIM LVA CERAFIL 5 NRZ R5 100k GND AUDIO Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. GND LVA C9 0.01µ REG PNP R4 220 CXA3117AN CXA3117AN Application Note 1) Power Supply The CXA3117AN, with the built-in regulator, is designed to permit stable operation at the wide range of supply voltage from 1.1 to 4.0V. Decouple the wiring to VCC (Pin 4) as close to the pin as possible. 2) Oscillator Input Oscillator input method a) Using Pins 1 and 2, input self-excited oscillation signal through the composition of a Colpitts type crystal oscillator circuit. Connect the capacitors attached to the crystal and Pin 2 to VCC. b) Directly input a local oscillation signal to Pin 1. 1 2 1 3 2 Ceramic filter 3 Ceramic filter VCC From local signal Fig. 1 3) Mixer The mixer is of double-balance type. Pin 24 is the input pin. Input though a suitable matching circuit. The input impedance is 2.0kΩ. Pin 3 serves as the output pin for the mixer, and a load resistance of 1.5kΩ is incorporated. 4) IF Filter The filter to be connected between this mixer output and the IF limiter amplifier input should have the following specifications. Connect the ground pin of the IF filter to VCC. I/O impedance : 1.5kΩ ±10% Bandwidth : Changes according to applications. 5) IF Limiter Amplifier The gain of this IF limiter amplifier is approximately 100dB. Take notice of the following points in making connection to the IF limiter amplifier input pin (Pin 5). a) Wiring to the IF limiter amplifier input (Pin 5) should be as short as possible. b) As the IF limiter amplifier output appears at QUAD (Pin 8), wiring to the ceramic discriminator connected to QUAD should be as short as possible to reduce the interference with the mixer output and IF limiter amplifier input. 3 4 6 5 7 8 VCC Wire as short and apart as possible As short as possible Fig. 2 –9– 9 CXA3117AN 6) Quick Charge In order to hasten the rising time from when power is turned on, the CXA3117AN features a quick charge circuit. Therefore, the quick charge circuit eliminates the need to insert a capacitor between the detector output and the LPF as is the case with conventional ICs, but a capacitor should be connected to Pin 7 to determine the average signal level during steady-state reception. The capacitance value connected to Pin 7 should be chosen such that the voltage does not vary much due to discharge during battery saving. Connect a signal for controlling the quick charge circuit to Pin 18. Setting this pin high enables the quick charge mode, and setting this pin low enables the steady-state reception mode. Quick charge is used when the power supply is turned on. The battery saving must be set high at the time. Connect Pin 18 to GND when quick charge is not being used. Power supply to the IC (Pin 4) Quick charge (Pin 18) 5ms Battery saving control (Pin 17) 1ms A 1ms A A T2 T1 T3 T4 Fig. 3 Example when the Pin 7 REF capacitance value is 1µF T1 in Fig. 3: 2-level data setting time after quick charge When the input frequency offset is within ±4.8kHz: 0ms T2 in Fig. 3: 4-level data setting time after quick charge When the input frequency offset is within ±1.6kHz or less: 0ms When the input frequency offset is within ±3kHz or less: 500ms or less T3 in Fig. 3: 4-level data is obtained T4 in Fig. 3: 2-level data is obtained – 10 – CXA3117AN 7) Detector The detector is of quadrature type. To perform phase shift, connect a ceramic discriminator to Pin 8. The phase shifting capacitor for the quadrature detector is incorporated. The FM (FSK) signal demodulated with the detector is output to AUDIO (Pin 16) through the internal primary LPF. The AUDIO output is the anti-phase output to the NRZ OUT. The CDBM455C50 (MURATA MFG. CO., LTD.) ceramic discriminator is recommended for the CXA3117AN. For the 2-level system, the CDBM455C28 can also be used. 9 8 7 6.8k Ceramic discriminator CDBM455C50 VCC Fig. 4 The detector output level is changed according to the resistance value connected to Pin 8. 8) Filter Buffer, Level Comparator and NRZ Comparator The LPF circuit is built in this IC. The LPF output is connected internally to the NRZ comparator, level comparator and quick charge circuit. 19 16 15 L. C. LPF 0.2V DET 7 Fig. 5 Using the LPF, remove noise from the demodulated signal and input the signal to the above three circuits. – 11 – CXA3117AN 8)-1. LPF Constant The data filter cut-off (fc) is expressed with the following equation. fc1 = 1 2πC11R fc2 = 1 2π 1 ,Q= C12 C13 R2 C12 C13 C11 to C13: External capacitance (Pin 9 to Pin 11) R: IC internal resistance R is approximately 55kΩ ± 20% when Pin 12 is low. The table below shows the example of constants to data rate. Capacitance (pF) fc (Hz) Data rate — — 430 512bps (2 levels) 950 1200bps (2 levels) 1900 2400bps (2 levels) 1000 1600bps (2 levels) 2000 3200bps (2 levels) 1000 3200bps (4 levels) 2000 6400bps (4 levels) H Pin 12 filter switch L 6800 H L H L H L 1500 Pin 9 Pin 10 Pin 11 Pin 9 Pin 10 Pin 11 1100 680 1420 1100 680 1420 8)-2. Comparator Output The level comparator and the NRZ comparator shape the waveform of this input signal and output it as a square wave. The comparator output stage is for open collector. Thus, if the CPU is of CMOS type and the supply voltage is different, a direct interface as illustrated in the figure below can be implemented. VCC 1.4V VCC CMOS power supply 4 (15) CMOS IC 19 Comparator output Fig. 6 – 12 – CXA3117AN 8)-3. Level Comparator Output The level comparator characteristics are as shown in the figure below. Therefore, a high signal is output at the bit border even if the input signal is a ±4.8kHz signal. This high output interval varies according to the frequency response of the bit rate filter, and widens as the cut-off frequency becomes lower. The decoder avoids this high interval when processing data. Input signal Output H L –4.8 –1.6 f0 +1.6 Level comparator output +4.8 Input frequency deviation [kHz] 9) REG CONT Controls the base bias of the external transistors. 10) LVA OUT This pin goes high (open) when the supply voltage becomes low. Since the output is an open collector, it can be used to directly drive CMOS device. The setting voltage of the LVA is 1.10V (typ.), and it possesses a hysteresis with respect to the supply voltage. The hysteresis width is 10mV (typ.). 11) B.S. Operation of the CXA3117AN can be halted by setting this pin low. This pin can be connected directly to CMOS device. The current consumption during battery saving is 10µA or less (at 1.4V). B.S. 17 Fig. 7 – 13 – CXA3117AN 12) M-ary (M = 2- or 4-level) FSK Demodulation System 12)-1. Output Waveform Polarity discrimination output and MSB comparator output are used to demodulate the 4-level waveform shown below. [4-level FSK demodulating waveform] +4.8kHz +1.6kHz 01 00 10 11 01 10 00 –1.6kHz –4.8kHz [NRZ OUT] Polarity discrimination output (When the input frequency is higher than the local frequency) POS 0 0 1 1 0 1 0 (The polarity can be inverted by setting the local frequency higer than the input frequency.) NEG [L.C. OUT] MSB comparator output 1.6kHz 1 0 0 1 1 0 0 4.8kHz The 4-level FSK demodulating data is divided into an NRZ OUT and L.C. OUT shown above. Here, the NRZ OUT corresponds to a conventional NRZ comparator output. The L.C. OUT is made comparing the demodulated waveform amplitude to the IC internal reference voltage levels. When the threshold value of L.C. OUT is not appropriate to the detector output, the resistance value on Pin 8 should be varied for the detector output level adjustment or the resistor should be inserted between Pin 6 and VCC for the level comparator threshold value adjustment. For the 2-level FSK demodulation, it corresponds to a conventional NRZ comparator output. 6 R VCC – 14 – CXA3117AN 12)-2. 4-level Signal and Threshold Value For Sony pager ICs, the demodulated signal is optimally matched to the NRZ comparator threshold value by the curve correction operation described in 13) as shown in the figure below. (operation point correction using a feedback loop filter) Level comparator 1 Offset correction circuit NRZ comparator Detector output Level comparator 2 Operation point correction (The comparator threshold value is fixed.) The level comparator threshold value can be adjusted by varying the detector output level, which is achieved by varying the discriminator dumping resistance. (AC gain adjustment) Level comparator threshold value 1 NRZ threshold value = Demodulated signal average voltage Level comparator threshold value 2 AC gain adjustment – 15 – CXA3117AN 12)-3. Offset Amount and Threshold Value Immediately after power-on when the REF capacitor is not charged with the correction voltage, if the input frequency has an offset, some time is required to correct this offset. In addition, the times required to obtain 2-level and 4-level data differ according to the offset amount. a) 2-level signals In the case of 2-level signals, correct data is obtained when the offset amount is smaller than the detector output amplitude. This is 75mV or less when the detector output level is 150mVp-p which corresponds to within ±4.8kHz when converted to a frequency by the S curve. Thus, 2-level data is obtained without an operation point correction time lag when the frequency offset is within ±4.8kHz. NRZ threshold value offset b) 4-level signals In the case of 4-level signals, correct data is obtained when the offset amount is less than 1/3 of the detector output amplitude (during ±4.8kHz DEV). This is 25mV or less when the detector output level is 150mVp-p which corresponds to ±1.6kHz or less when converted to a frequency by the S curve, . Thus, 4level data is obtained without an operation point correction time lag when the frequency offset is within ±1.6kHz. Level comparator threshold value 1 NRZ threshold value offset Level comparator threshold value 2 As shown above, 4-level signals have an allowable offset range 1/3 that of 2-level signals. When the offset exceeds this allowable range, time is required to determine the operation point and obtain correct data through feedback. Also, even if the offset is within the allowable range, the output pulse duty changes until the offset is 0. – 16 – CXA3117AN 13) Principle of Quick Charge Operation BUF in Fig. 8 is the detector buffer amplifier and COMP is the level comparator or the NRZ comparator. The CXA3117AN has a feedback loop from the comparator input to the input circuit of the detector output buffer. This equalizes the average value of the comparator input voltage to the reference voltage, with the quick charge circuit of CHG being set in the feedback loop. Switching the current of the quick charge circuit enables reduction of the rise time. In this block, CHG is a comparator which compares input voltages and outputs a current based on this comparison. The current on CHG is switched between high and low at Pin 18. When the power is turned on, switch the current to high to increase the charge current at C in Fig. 8 and shorten the time constant. During steady-state reception mode, switch the current to low, lengthening the charge time constant and allowing for stable data retrieval. Also, controlling Pin 14 can make the current off. This is effective when the same data are received continuously. AUDIO BUF 16 LPF COMP 19 CHG FSK REF 7 Reference voltage C Fig. 8 13)-1. Slow Charge Mode , Quick Charge Mode During slow charge mode and Quick Charge Mode, if the RF system frequency is deviated, etc., and the demodulated output has an offset voltage, feedback is applied to correct this offset voltage. Here, feedback is applied so that the average value of the audio output voltage matches the internal regulator voltage. This feedback shifts the S curve up and down in a parallel manner. S curve Offset S curve f0 Input signal f0 When the RF system frequency is deviated, there is no correction so an offset occurs. Input signal Reference voltage Reference voltage During slow charge mode, the S curve shifts to correct the offset. – 17 – CXA3117AN 14) S Curve Characteristics Even if the IF IN input signal frequency is deviated, the feedback is applied to the AUDIO operating point so as to match it to the comparator reference voltage by the quick charge operation shown in Fig. 8. Therefore, this feedback must be halted in order to evaluate the S curve characteristics. To execute the evaluation, measure the average voltage on Pin 16 first and input this voltage to Pin 7 from the external power supply. 15) Control Pins The function controls are as shown below. Pin No. 12 14 17 18 Symbal FIL SW CHG OFF B.S. CHARGE Function Data filter cut-off control Input high fc: Low fc: High∗ Input low Pin 7 charge current Battery saving mode Pin 7 charge speed control control control Quick charge Slow charge off IC operation∗ ∗ Slow charge∗ Slow charge operation Sleep Note) Pin 14 control should be performed with Pin 18 low. When each function is not controlled externally, set it to the state with an asterisk (∗). 16) Misoperation Prevention Function for Continuous Data The offset to the comparator threshold value of the detector output is canceled with the feedback loop indicated in the paragraph 13). This operation assumes that “0” and “1” are in equal numbers in the data. The offset is occurred when the “0” or “1” data are received continuously. In this case, setting Pin 14 high to make the charge current off prevents the offset occurrence. Without using this function, the stability for the same data continuously received depends on the capacitance value on Pin 7 shown in the paragraph 13). When this capacitance value is increased, the data is demodulated more stably; however, it takes more time for the IC to rise. If this function is not used, be sure to connect Pin 14 to GND. Reception signal Sync part Data CHG OFF H (Pin 14) L Fig. 9 – 18 – Sync part Data CXA3117AN 17) REF Capacitance Value and Charge Time, Hold Time The REF capacitance is the feedback loop time constant of the S curve. This determines the detector output low frequency cut-off, IC rise characteristics and operating voltage hold characteristics during battery saving. When the REF capacitance is reduced: 1. The detector output low frequency cut-off becomes higher. 2. The IC rise characteristics become faster. 3. The operating voltage hold characteristics during battery saving become shorter. Of these, 1 has little effect on FSK, so a capacitance value that matches the used system should be selected in consideration of 2 and 3. 17)-1. Example of IC Rise Characteristics Immediately After Power-on [s] 1.0 When the REF capacitance is 1µF 0.5 0 –3 f0 +3 [kHz] Offset frequency and T2 (after power-on until 4-level data is obtained) 17)-2. Example of Operating Voltage Hold Characteristics When the REF capacitance is 1µF, the S curve hold voltage variation is a value that has no effect on the rise of the 4-level data after 5 minutes of battery saving as shown below. Offset voltage after 5 minutes of battery saving: 10mV or less – 19 – CXA3117AN 18) Sensitivity Adjustment Method The constants shown in the Application Circuit diagram are for the standard external parts. However, adjustment may be necessary depending on the conditions of use, characteristics of external parts, and the RF system circuit and decoder connected to the IF IC, etc. Adjust the sensitivity according to the following procedures. a) MIX IN matching When using a matching circuit between the RF system circuit and MIX IN of the CXA3117N, adjust the trimmer to obtain the optimal sensitivity while monitoring the AUDIO output. b) Local input level The mixer circuit gain is dependent on the local signal input level to OSC IN. The input level to OSC IN should be set as high as possible within the range of –6 to +2dBm as shown in the graph of "Local input level vs. Mixer gain characteristics". However, care should be taken as raising the input level above +2dBm will cause the sensitivity to drop. When creating the local signal using the internal oscillator circuit, the oscillation level varies according to the external capacitances attached to Pins 1 and 2 and the characteristics of the used crystal. Therefore, be sure to adjust the external capacitance values attached to Pins 1 and 2 according to the crystal characteristics. OSC 1 2 C1 C2 VCC C1 and C2 have the following range in the figure above. C1 ≥ C2 C1 = C2 to C1 = 5C2 As for the ratio of C1 to C2, the oscillation stabilizes as C1 approaches equality with C2. The oscillation level decreases as the C1 and C2 values become larger, and increases as the C1 and C2 values become smaller. Use a FET probe to confirm the local input level. c) LPF constant The data filter cut-off may need to be changed depending on the characteristics of the connected decoder. Adjust the capacitance values of Pins 9 to 12 while checking the incoming sensitivity including the decoder. If the capacitance values are too large, the detector output waveform will deviate at high data rates, causing the sensitivity to drop. Conversely, if the capacitance values are too small, the LPF will be easily affected by noise, causing the sensitivity to drop. Adjust capacitance values of Pins 9 to 12 so that the capacitance value described in "16) LPF Constant" becomes smaller. – 20 – CXA3117AN d) Detector output level The NRZ comparator and level comparator threshold values are fixed for the CXA3117AN. In the case of 4level signals, the relationship between the level comparator threshold value and the detector output level affects the sensitivity. The detector output level can be adjusted by the resistance attached to Pin 8. Increasing the resistance value also increases the output level, and vice versa. The Pin 8 resistance value differs according to the ceramic discriminator attached to Pin 8. When the discriminator is changed to a different type, the resistance value must be adjusted. Adjust the resistance value while monitoring the level comparator output waveform or the sensitivity including the decoder. e) Quick charge circuit The CXA3117AN has a feedback circuit that corrects the detector output operation point in order to correct the IF frequency deviation. When the IF frequency deviation amount is large, correction takes time and may lower the sensitivity. Adjust the oscillator frequency of the local oscillator so that the center frequency of the signal input to Pin 5 (IF IN) is as close to 455kHz as possible. 19) CXA3117AN Standard Board Description • Outline This board contains the external parts shown in the Application Circuit in order to evaluate CXA3117AN operation. • Features The following CXA3117AN basic operations can be checked. 1) Varying the data filter cut-off 2) Battery saving and other mode switching 3) NRZ output and level comparator output pins • Method of use 1) Input the CXA3117AN supply voltage Vcc = 1.4V. The CXA3117AN operates with a single power supply. 2) The CXA3117AN uses a 21.245kHz crystal. Input the RF signal from the RF pin and use the CXA3117AN in the condition where IF = 455kHz. 3) Set the mode switches. • Mode switch setting Mode switches S1, S2, S3 and S4 are provided in four locations in the board. Each basic operation can be confirmed by switching these mode switches while referring to the board layout. See the table in 15) Control Pins for the mode switching. • Device specifications See these Specifications for the IC specifications. The ICs for this evaluation board are ES specification. • Circuit diagram The circuit diagram is the same as the Application Circuit diagram in these Specifications. – 21 – CXA3117AN 19)-1. Standard Board Layout RF S2 PNP S3 S4 VCC GND 24 13 1 12 XTAL CERAFIL DISC S1 3117 EVALUATION BOARD 19)-2. Mode Switch Description Quick charge Sleep H IC operation L Slow charge operation H Slow charge off B. S. CHG-OFF L fc: High H fc: Low S1 CHARGE S2 High L S3 Slow charge S4 Low FIL SW – 22 – CXA3117AN 19)-3. List of Standard Board Parts VALUE PART# REMARKS (MANUFACTURE) NOTE (RIVER) E12 series 1/8W TZ03P450FR169 (MURATA PRODUCTS) TRIMMER CAPACITOR DD100 series temperature characteristics type B (MURATA PRODUCTS) CERAMIC CAPACITOR E12 series (high dielectric constant type) Resistor 220 R4 8.7k R7 100k R5 R6 R8 Capacitor 10 to 120p C1 15p C5 22p C4 100p C14 1000p C3 1200p C11 C12 C13 0.01µ C8 C9 1µ C10 25V 1µ (SHIN-EI TUSHIN KOGYO CO., LTD.) 10µ C6 C7 25V 10µ (SHIN-EI TUSHIN KOGYO CO., LTD.) L1 EL0405 (TDK Products) ELECTROLYTIC CAPACITOR E6 series Inductor 1.8µH Active Component PNP 2SA1015 (TOSHIBA CORPORATION) XTAL KSS 2B (KINSEKI, LTD.) Crystal 21.245MHz – 23 – E12 series 2.5mm pitch (Lead Pitch) CXA3117AN Ceramic Filter CFWS455D (MURATA PRODUCTS) 455kHz 1.5kΩ DISC CDBM455C50 (MURATA PRODUCTS) 455kHz S1, S2, S3, S4 ATE1D-2M3-10 (FUJISOKU CORPORATION) ON – ON (1 poles) RF HRM300-25 (HIROSE ELECTRIC CO., LTD.) SMA CONNECTOR ×2 Mac 8 test pin ST-1-3 (Mac eight) L = 10mm 0.8φ ×6 Mac 8 test pin LC-2-G (Mac eight) CERAFIL Ceramic Discriminator Switch Connector Pin – 24 – CXA3117AN Example of Representative Characteristics Mixer input audio response and RSSI characteristics S+N+D 0 1000 RSSI 800 RF 21.7MHz LOCAL 21.245MHz –6dBm Audio 1.6kHz CW Dev. 4.8kHz 0dB = 63.1mVrms VCC = 1.4V T = 25°C –20 –30 600 400 –40 200 –50 0 RSSI [mV] Audio response [dB] –10 S/N –60 –120 –110 –100 –90 –80 –70 –60 Mixer input level [dBm] –50 –40 –30 –20 Mixer I/O characteristics and 3rd intercept point Current consumption characteristics –20 1.3 –30 Output level [dBm] Current consumption [mA] 1.4 1.2 1.1 1.0 fO –40 –50 fO = 21.7MHz fLO = 21.245MHz –6dBm –60 0.9 –70 f1 + f2 1.0 2.0 3.0 Supply voltage [V] 4.0 –80 –60 – 25 – –50 f1 = 21.725MHz f2 = 21.750MHz The I/O level is for the values read at I/O pin with the spectrum analyzer –40 –30 –20 –10 Mixer input level [dBm] 0 CXA3117AN Local input level vs. Mixer gain characteristics Mixer gain [dB] 10 5 fRF 21.7MHz –60dBm fLO 21.245MHz 0 0.01µ 1 –5 50 –20 –15 –10 –5 Local input level [dBm] 0 5 Variable cut-off characteristics of audio filter Pin 12 voltage L H 0 Response [dB] –10 –20 –30 –40 –50 –60 100 200 500 1k 2k 5k Input frequency [Hz] 10k Level comparator characteristics 2.0 Comparator output voltage [mV] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 150 200 250 Comparator input voltage [mV] – 26 – 300 CXA3117AN Level comparator threshold value [mV] Level comparator threshold value control characteristics (Output low high switching level) Representative example using typical sample 300 250 210 200 150 Typical value when Pin 6 is shorted to Vcc 100 0.5 0 1.0 1.5 2.0 Pin 6 current [µA] 2.5 3.0 NRZ comparator characteristics Comparator output voltage [V] 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 160 180 200 220 240 Comparator input voltage [mV] 260 LVA characteristics LVA comparator output voltage [V] 1.2 1.0 0.8 0.6 0.4 0.2 0 1.05 1.10 1.15 Supply voltage [V] – 27 – 1.20 CXA3117AN Quick charge circuit output current characteristics Fast mode 0.5 50 Pin 7 215mV fixed Slow mode on 0 30 0 Slow mode off –0.3 –30 –0.5 –50 80 120 160 200 240 280 Pin 11 input Pin 16 voltage [mV] 320 fast current [µA] slow current [µA] 0.3 360 RSSI output voltage temperature characteristics RSSI output voltage characteristics [mV] 800 700 600 500 400 300 : –20°C : 0°C : 25°C : 50°C : 75°C 200 100 –120 –110 –100 –90 –80 –70 –60 RF input level [dBm] – 28 – –50 –40 –30 –20 CXA3117AN Detector output level and level comparator threshold value vs. Temperature characteristics 4.8kHz Dev. detector output level Detector output level and level comparator threshold value [mV] 100 Level comparator threshold value for positive side 50 1.6kHz Dev. detector output level 0 Level comparator threshold value for negative side –50 :H :L –100 –20 0 25 50 Temperature [°C] – 29 – 75 L H CXA3117AN Package Outline Unit: mm 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 0.1 24 13 ∗5.6 ± 0.1 7.6 ± 0.2 A 1 12 b 0.13 M 0.5 ± 0.2 (0.15) (0.22) 0.1 ± 0.1 DETAIL B : SOLDER b=0.22 ± 0.03 + 0.03 0.15 – 0.01 + 0.1 b=0.22 – 0.05 + 0.05 0.15 – 0.02 0.65 B DETAIL B : PALLADIUM 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-24P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP024-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 30 –