SONY CXA1977R

CXA1977R
10-bit 20MSPS A/D Converter
Description
The CXA1977R is a 10-bit 20MSPS 2-step parallel
type A/D converter for video signal processing.
This A/D converter operates on +5V power
supplies. The analog signal can be converted to the
digital signal by using this IC in conjunction with the
Sample-and-hold IC.
48 pin LQFP (Plastic)
Features
• Maximum operating speed : 20MSPS (Min.)
• Resolution
: 10-bit
• Low power dissipation
: 160mW (Typ.)
• Wide-band analog input
: 10MHz
• Low input capacitance
: 50pF (Typ.)
• Built-in digital correction
(Compensation within ±16LSB)
• TTL input
• TTL output
• Output code : binary/2'S complement/1'S complement
Function
10-bit 20MSPS 2-step parallel type A/D converter
Structure
Bipolar silicon monolithic IC
Applications
High resolution video signal processing
N.C.
VREFBS
VREFB
VREF3
VREF2
VREF1
VREFT
VREFTS
N.C.
N.C.
DVCC3
DVCC3
Block Diagram
36
35
34
33
32
31
30
29
28
27
26
25
24 PS
N.C. 38
23 ENABLE
VINL 39
22 CLK
N.C. 41
MATRIX
AVCC 42
H-COMPARATOR
CLK BUFFER
VINH 40
L-ENCORDER
L-COMPARATOR
N.C. 37
21 MINV
20 LINV
19 N.C.
18 DVCC3
N.C. 43
H-ENCODER
AGND 44
17 DGND2
DVCC2 45
16 DGND1
UNDER 46
OVER/UNDER
OUTPUT BUFFER
FINE OUTPUT
BUFFER
15 DVCC1
CORRECTION
COARSE OUTPUT
BUFFER
OVER 47
14 DGND1
13 N.C.
D3
D4
8
9
10
11
12
(MSB) D9
D2
7
D8
D1
6
D7
5
D6
4
D5
3
N.C.
2
DGND1
1
(LSB) D0
DGND1 48
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94326-PS
CXA1977R
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
DVcc1
0 to +6
V
DVcc2
0 to +6
V
DVcc3
0 to +6
V
AVcc
0 to +6
V
• Analog input voltage
VINH
AGND to AVcc + 0.3
V
VINL
AGND to AVcc + 0.3
V
• Reference voltage
VREFT
AGND to AVcc + 0.3
V
VREFB
AGND to AVcc + 0.3
V
• Digital input voltage
CLK
DGND1 – 0.5 to DVcc1
V
MINV
DGND1 – 0.5 to DVcc1
V
LINV
DGND1 – 0.5 to DVcc1
V
PS
DGND1 – 0.5 to DVcc1
V
ENABLE
DGND1 – 0.5 to DVcc1
V
• Digital output voltage
Vo
DGND1 – 0.5 to +3.6
V
(Vo: The voltage is applied to the output pin for high impedance output.)
• Storage temperature
Tstg
–65 to 150
°C
950
mW
• Allowable power dissipation PD
(On a fiber-glass epoxy board: 40mm × 40mm, t = 0.8mm)
Recommended Operating Conditions
• Supply voltage
• Analog input voltage
• Reference voltage
• Digital input voltage
DVcc1
DVcc2
DVcc3
AVcc
AGND
DGND1
DGND2
VINH
VINL
VREFT
VREFB
VIH
VIL
• Clock width
tPWH
tPWL
• Operating temperature
Topr
Min.
+4.6
+4.6
+4.6
+4.6
Typ.
+5
+5
+5
+5
0
0
0
+2
+2
+3.9
+1.9
+2
+4
+2
Max.
+5.25
+5.25
+5.25
+5.25
+4
+4
+4.1
+2.1
+0.8
25
24
–20
+85
–2–
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
ns
ns
°C
CXA1977R
Pin Description
Pin No.
1 to 5
8 to 12
Symbol
I/O
Pin voltage
Equivalent circuit
Description
45 DVCC2
D0 to D9
Digital output
D0 (LSB) to
D9 (MSB)
O
1 D0 to 5 D4
8 D5 to 12 D9
46 UNDER
46
UNDER
O
TTL
47 OVER
Underflow output
16 DGND1
Overflow output
200k
47
OVER
O
17 DGND2
15
DVCC1
45
DVCC2
6, 14,
16, 48
—
+5V
(typ.)
Digital power supply
DGND1
—
GND
Digital ground
DVCC3
—
+5V
(typ.)
Digital power supply
DGND2
—
18
25
26
17
Digital negative
power supply
GND
44
20
AGND
LINV
Analog negative
power supply
—
I
DVCC1
15
ENABLE 23
TTL
400k
100k
100k
PS 24
MINV 21
21
MINV
I
LINV 20
DGND2 17
16
DGND1
23
ENABLE
This input can invert
output form of D0 to
D8. In open
condition, this pin
turns to high level
input. (For details,
refer to the Output
Formula Chart.)
This input can invert
output form of D9
(MSB). In open
condition, this pin
turns to high level
input. (For details,
refer to the Output
Formula Chart.)
3-state control.
Turns to enable
when low is input.
In open condition,
this pin turns to high
level input.
I
–3–
CXA1977R
Pin No.
Symbol
I/O
Pin voltage
Equivalent circuit
Description
DVCC1
15
400k
ENABLE 23
100k
100k
PS 24
24
PS
I
TTL
MINV 21
LINV 20
DGND2 17
16
Power save input.
Power save
condition is entered
when high level is
input. In open
condition, this pin
turns to high level
input.
DGND1
DVCC1
15
20k
22
CLK
I
30k
30k
TTL
Clock input
CLK 22
DGND2 17
16
DGND1
29
VREFTS
—
130
+4V
30
VREFT
I
31
VREF1
—
VREFTS 29
Reference voltage
sense (Top)
Reference voltage
force (Top)
VREFT 30
VREF1 31
+3.5V
VREF2 32
32
VREF2
—
+3.0V
33
VREF3
—
+2.5V
VREF3 33
VREFB 34
VREFBS 35
130
34
VREFB
I
Reference voltage
force (Bottom)
+2V
35
VREFBS
—
AGND 44
–4–
Reference voltage
sense (Bottom)
CXA1977R
Pin No.
Symbol
I/O
Pin voltage
Equivalent circuit
Description
42 AVCC
11.2k
39
VINL
I
+2V to +4V
11.2k
VREF
VINL 39
Analog input
(Lower comparator
input)
44 AGND
42 AVCC
26k
40
VINH
I
+2V to +4V
26k
VREF
VINH 40
Analog input
(Upper comparator
input)
44 AGND
42
7, 13,
19, 27
28, 36,
37, 38,
41, 43
AVCC
N.C.
N.C.
—
—
—
+5V (Typ.)
Analog power supply
—
Open.
Not connected to
internal circuit, but
connection to DGND
(digital ground) is
recommended.
—
Open.
Not connected to
internal circuit, but
connection to AGND
(analog ground) is
recommended.
–5–
CXA1977R
Electrical Characteristics
(Ta = 25°C, DVCC1, 2, 3, AVCC = +5V, AGND, DGND1, 2 = 0V, VREFB = +2V, VREFT = +4V)
Item
Resolution
Symbol
Measurement conditions
n
Min.
Typ.
Max.
Unit
10
10
10
bit
DC characteristics
EIL
VIN = +2 to +4V
–2.0
+2.0
LSB
EDL1
VIN = +2 to +2.5V
–0.8
LSB
EDL2
VIN = +2.5 to +4V
–1
+0.8
+2∗1
Analog input current
IIN
VIN = +4V
0
60
µA
Analog input capacitance
CIN
VIN = +3V + 0.07Vrms
50
pF
Analog input band width
BW
–1dB
10
MHz
Integral linearity error
Differential linearity error
LSB
Analog input
Reference voltage input
Reference current
IREF
–16
–10
–7
mA
Reference resistance
RREF
120
200
280
Ω
EOT
1
10
25
mV
EOB
1
10
25
mV
Offset voltage
Reference voltage
VREF1
3.5
V
VREF2
3.0
V
VREF3
2.5
V
Digital input
Digital input voltage
VIH
V
VIL
IIH1
Digital input current
2
∗2
IIL1
IIH2
∗3
DVCC1
= 5.25V
IIL2
0.8
V
VIH = 2.7V
–10
+10
µA
VIL = 0.5V
–200
0
µA
VIH = 2.7V
–10
+10
µA
VIL = 0.5V
–20
0
µA
Digital input characteristics
2
pF
Switching characteristics
Maximum operating speed
Clock pulse width
Sampling delay
Output delay time
3-state output disable time
3-state output enable time
Fc
20
MSPS
tPWH
tPWL
tSH
tSL
tDLH
tDHL
tPHZ
tPLZ
tPZH
tPZL
25
ns
24
ns
∗4
∗4 CL = 20pF
∗6
∗5
∗7
–6–
–2
1
5
ns
–15
–1
2
ns
10
30
ns
10
30
ns
250
ns
400
ns
500
ns
500
ns
CXA1977R
Item
Symbol
Measurement conditions
Min.
Typ.
2.7
3.4
Max.
Unit
Digital output
V
VOH
IOH = –300µA
VOL
IOL = +500µA
IOZ
DVCC1, 2 = 5.25V, VO = 3.6V
Differential gain error
DG
0.5
%
Differential phase error
DP
NTSC 40IRE mod. ramp,
Fc = 14.3MSPS
0.3
deg
Fc = 20MSPS
FIN = 1kHz
55
dB
Fc = 20MSPS
FIN = 1MHz
53
dB
Fc = 20MSPS
FIN = 2MHz
52
dB
Fc = 20MSPS
FIN = 7.5MHz
49
dB
Digital output voltage
Leak current during output off
DVCC1, 2 = 4.6V
–20
0.5
V
75
µA
Dynamic characteristics
SNR
SNR
Power supply
DVCC1 current
DVCC2 current
DVCC3 current
AVCC current
Power dissipation Pd = A + B
A = (IDVCC1 + IDVCC2 + IDVCC3
+ IAVCC) × 5V
B = | IREF | × 2V
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
IDVCC1
IDVCC2
IDVCC3
IAVCC
DVCC1 = +5V
∗8 During power save
6.0
9.9
14.0
mA
4.3
7.3
12.0
mA
DVCC2 = +5V
∗8 During power save
0.05
0.16
0.30
mA
0
0
27
mA
DVCC3 = +5V
∗8 During power save
8.1
14.7
21.1
mA
0.34
0.55
1.13
mA
0.5
3.2
6.0
mA
0
20
50
µA
87
160
239
mW
37
59
98
mW
AVCC = +5V
∗8 During power save
Pd
∗8 During power save
+1 < EDL2 ≤ +2 (LSB) is two and under.
CLK input
MINV, LINV, ENABLE, and PS inputs
Refer to Timing Diagram (1)
Refer to Timing Diagram (2)
The load is a bi-state totem-pole output delay time test load circuit.
The load is a 3-state output test load circuit.
When PS and ENABLE inputs are in high level.
–7–
CXA1977R
Bi-state Totem-pole Output Delay Time Test Load Circuit
Test point
Output from the IC under test
CL
Note 1)
CL = 20pF
3-state Output Test Load Circuit
Test point
VCC
Test condition
S1
S2
tPZL
Close
Open
tPZH
Open
Close
tPLZ
tPHZ
Close
Close
3.9k
S1
Output from the IC under test
CL
Note 1)
1kΩ
Note 2)
S2
CL = 20pF
Note 1) CL includes probe capacitance and parasitic capacitance in Test Board.
Note 2) All diodes are IS2076.
Error Rate Test Circuit
(Threshold level)
DIP SW
B
SG1
VIN
(FC/2) – 1kHz
SG2
FC
CXA1977R
LATCH
A
CLK
DIVIDER
FC/2
–8–
ADDER
A+B
=C
C
LATCH
C
A>C
COMPA- A
RATOR
COUNTER
CXA1977R
Notes on Operation
1. Analog ground (AGND)
Keep analog ground surface on PCB as wide as possible with impedance and resistance as low as
possible.
2. Digital ground (DGND1, DGND2)
Upon mounting to PCB keep ground surface as wide as possible with impedance and resistance as low as
possible.
Moreover, a common analog and digital ground immediately near ADC will help obtain characteristics
smoothly.
3. Digital positive power supply (DVcc1, DVcc2, DVcc3)
Connect to the digital ground with a ceramic capacitor over 0.1µF and as close to the pins as possible.
Insert a ceramic capacitor between DVcc2 and DGND1 of TTL output power supply as shortly as possible
because noise tends to occur.
4. Analog positive power supply (AVcc)
Connect to the analog ground on PCB with a ceramic capacitor over 0.1µF as close to the pin as possible.
5. Reference voltage (VREFTS, VREFT, VREF1, VREF2, VREF3, VREFB, VREFBS)
These pins provide reference voltage to upper and lower comparators. Voltage between VREFT and
VREFB corresponds to input dynamic range.
There is a 200Ω resistance between VREFT and VREFB. By applying 2V to both pins a current of about
10mA flows. When the reference voltage is made unstable by the clock, ADC characteristics are adversely
affected. Connect VREFT and VREFB to the analog ground on PCB by means of a tantalum capacitor
over 10µF and a ceramic capacitor over 0.1µF respectively. Also, connect each of VREF1, VREF2 and
VREF3 to the analog ground on PCB using a ceramic capacitor over 0.1µF. This will provide stability to the
characteristics of high frequency. Strictly speaking on reference voltage VREFT side and VREFB side
there is a respective about 10mV offset.
When there is no problem with the usage of those offset voltages, voltage is applied directly to VREFT,
VREFB. In case the reference voltage is to be strictly applied, adjust to obtain an offset voltage of 0V,
keeping VREFTS and VREFBS as sense pins and VREFT and VREFB as force pins to form a feedback
loop circuit.
For details, see the Standard Circuit.
6. Analog input (VINH, VINL)
VINH is the input pin for the upper comparator while VINL is the input pin for the lower comparator.
Keep the input signal level within the level between VREFT and VREFB.
As this IC's analog input capacitance stands at about 50pF, it is necessary to drive with an buffer amplifier
having sufficient driving capability. Also, when driving is done with the buffer amplifier of a low output
impedance, as A/D converter input capacitance is large, ringing is generated and settling time grows
longer. Here a small resistance of about 5 to 30Ω is connected in series between the buffer amplifier and
each of A/D converter's VINH and VINL, as a dumping resistance. This eliminates ringing and shortens
settling time. Also keep wiring between buffer amplifier and A/D converter as short as possible.
–9–
CXA1977R
7. Clock input (CLK)
TTL input. Clock line wiring should be the shortest possible while distanced from other signal lines to avoid
affecting them.
This IC is 2-step parallel type A/D converter. Accordingly an external sample-and-hold circuit (SH) is
necessary. However the timing between this SH circuit output waveform (A/D converter analog input
waveform) and the A/D converter clock timing requires attention. In the relation between A/D converter
clock and the A/D converter analog input signal, with the timing TH of the rising edge of A/D converter
clock, the upper comparator compares the input signal and the reference voltage to latch the results. After
that, with the timing TL of the falling edge of A/D converter clock, the lower comparator compares the input
signal and reference signal to latch the results. (Strictly speaking, the sampling delay tSH is in TH and the
sampling delay tSL is in TL.)
In this A/D converter, the lower comparator features a length of ±32mV (±16LSB) redundance in relation to
the upper comparator. At the timing when the lower comparator compares input signal and reference
signal to latch at the timing TL, it is necessary to have the SH output settling performed. But at the timing
when the upper comparator compares input signal and reference voltage to latch at the timing TH, as long
as the SH output is within the ±32mV range to the final settling value, digital correction applies, A/D
conversion precisely occurs. As seen from the above, A/D converter clock rise and fall timing versus SH
output waveform should be duly considered. For the clock high level time tPWH and low level time tPWL, set
to a value in excess of the time indicated for the respective operating conditions.
Output data is synchronously with the clock rising edge.
For details on timing, refer to the Timing Chart.
8. MINV input (MINV)
Digital output polarity inversion control pin of D9 (MSB).
TTL input. At open, turns to high level input.
For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.
9. LINV input (LINV)
Digital output polarity inversion control pin of D8 to D0 (LSB).
TTL input. At open, turns to high level input.
For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.
10. Output enable (ENABLE)
3-state control pin of digital output (D0 to D9, UNDER, OVER)
TTL input. At open, turns to high level input. At that time digital output turns all to high impedance.
11. Power save input (PS)
Power save control pin of internal circuit.
TTL input. At open, turns to high level input.
To set to power save mode, turn both PS and ENABLE to high level input.
– 10 –
CXA1977R
12. Digital output (D0 to D9)
Output pin of D9 (MSB) to D0 (LSB).
TTL output.
Output data polarity inversion is executed by means of MINV and LINV signals, and they can output in
binary, 1'S complement and 2'S complement.
Also, by turning ENABLE signal to high level, the output can be turned into high impedance output.
However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V
or more must not be applied to prevent the distruction of IC.
For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. For
the timing, refer to the Timing Chart.
13. Overflow output (OVER)
When the input signal exceeds VREFT, overflow signal is output.
MINV and LINV have no effect on this pin.
Also by turning ENABLE signal to high level, the output can be turned into high impedance output.
However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V
or more must not be applied to prevent the distruction of IC.
For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.
For the timing, refer to the Timing Chart.
14. Underflow output (UNDER)
When the input signal turns below VREFB, underflow signal is output.
MINV and LINV have no effect on this pin.
Also by turning ENABLE signal to high level, the output can be turned into high impedance output.
However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V
or more must not be applied to prevent the distruction of IC.
For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.
For the timing, refer to the Timing Chart.
– 11 –
CXA1977R
15. TTL to CMOS interface
In general, VOH of TTL is approximately 3.7V without load, and it is guaranteed to be 2.7V (Min.). However,
it is not enough for VOH of TTL to drive VIH of CMOS,because VIH of CMOS is 3.5V (Min.)
TTL
VOH (Min.) = 2.7V
VOL (Max.) = 0.5V
CMOS
VIH (Min.) = 3.5V (= 0.7VDD)
VIL (Max.) = 1.5V (= 0.3VDD)
When TTL output of ADC is made a connection with CMOS logic circuit, pull-up resistance (Rp) is used.
(See chart below). The value of Rp is usually from a few thousand ohm to scores of thousand ohm. The Rp
(min.) is decided by Supply voltage of CMOS (VDD) and IOL of ADC (= +500µA), while the Rp (max.) is
decided by required propagation delay (positive edge) and load capacitance. When Vcc is larger than VDD,
it is necessary to pay attention to input equivalent circuit of CMOS, because it may happen that VIH goes
over the absolute maximum ratings of CMOS and it brings about LATCH-UP to CMOS circuit.
VCC
VDD
Rp
ADC
CMOS
– 12 –
1 (OPEN)
LINV
– 13 –
0
1
2
3
:
512
:
1019
1020
1021
1022
1023
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 (OPEN)
1 (OPEN)
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
:
0 0 0 0 0 0 1 1 1 1 1 1
:
1 0 1 1 0 0 1 0 0 0 0 0
1 1 0 0 0 0 1 0 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 0 1 0 0 0 0 0
1 1 1 1 1 0 1 0 0 0 0 0
0
0
0
0
OF: OVER FLOW
UF: UNDER FLOW
:
0 1 0 0 0 0 0
:
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
0 1 1 1 1 1 1
1
0
0
0
0: VOLTAGE LEVEL-LOW
1: VOLTAGE LEVEL-HIGH
Z: HIGH IMPEDANCE
4V
:
:
:
:
:
:
:
:
:
:
2V
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
1 1 1 1 0 0 0 0 0 0 0 0
:
0 1 0 0 0 0 0 1 1 1 1 1
0 0 1 1 0 0 0 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 1 1
0 0 0 1 0 0 0 1 1 1 1 1
0 0 0 0 1 0 0 1 1 1 1 1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
:
0 0 0 0 0 0 0 1 1 1 1 1
:
1 0 1 1 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
1
1 1 1 1 0
1
1
1
1
OF 9 8 7 6 5 4 3 2 1 0 UF
OF 9 8 7 6 5 4 3 2 1 0 UF
OF 9 8 7 6 5 4 3 2 1 0 UF
OF 9 8 7 6 5 4 3 2 1 0 UF
(LSB) (MSB)
(LSB)
(LSB) (MSB)
(MSB)
(LSB) (MSB)
1 (OPEN)
MINV
OUTPUT
0
ENABLE
Output Formula Chart
Z
Z
Z
Z
:
Z
:
Z
Z
Z
Z
Z
—
—
1
(OPEN)
CXA1977R
CXA1977R
Timing Chart (1)
N+1
N
Sample-and-hold output
TH
TL
N+2
tSH
tSL
1.5V
A/D clock
tPWH
A/D digital output
tPWL
1/FC
DATA
N–1
1.5V
DATA N
DATA N + 1
tDLH
tDHL
TH is the timing of latching result for the comparator of VIN and VREF in the upper comparators.
TL is the timing of latching result for the comparator of VIN and VREF in the lower comparators.
Timing Chart (2)
ENABLE signal
(Low-level enabling)
3V
1.5V
1.5V
4.5V
Waveform 1
Note)
0.3V
1.5V
VOL
1.5V
tPZH
Waveform 2
Note)
0V
tPLZ
tPZL
Output waveform of 3-state
enable and disable time∗.
(∗ Enable time = tPZL/tPZH,
disable time = tPLZ/tPHZ)
tPHZ
VOH
1.5V
1.5V
0V
0.3V
Notes) Waveform 1 indicates the output waveform when internal conditions are set to obtain a low level
output, with the exception of when output is disabled by means of the ENABLE signal.
Waveform 2 indicates the output waveform when internal conditions are set to obtain a high level
output, with the exception of when output is disabled by means of the ENABLE signal.
– 14 –
CXA1977R
VREFT
VREFB
Standard Circuit
VREFB
VREFT
C5
0.1µ
C6
0.1µ
C8
0.1µ
C7
0.1µ
C10
10µ
C4
10µ
C12
0.1µ
C14
0.1µ
C13
0.1µ
R1 50
DVCC3
N.C.
DVCC3
N.C.
VREFT
VREFTS
VREF1
VREF2
VREF3
VREFB
37 N.C.
VREFBS
N.C.
36 35 34 33 32 31 30 29 28 27 26 25
PS 24
PS
38 N.C.
ENABLE 23
39 VINL
CLK 22
CLK
40 VINH
MINV 21
MINV
41 N.C.
LINV 20
LINV
42 AVCC
N.C. 19
ENABLE
VIN
C1
0.1µ
44 AGND
DGND2 17
45 DVCC2
DGND1 16
46 UNDER
DVCC1 15
9
10 11 12
D8
D4
8
D8
D3
D7
D1
D2
7
D7
DGND1
6
D6
D4
5
D6
D3
4
D5
D2
3
N.C.
D1
2
D0
(LSB)
1
D0
48 DGND1
OVER
C9
0.1µ
DGND1 14
D5
47 OVER
UNDER
C11
0.1µ
DVCC3 18
43 N.C.
D9 (MSB)
C3
0.1µ
N.C. 13
5V
D9
R2 50
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 15 –
CXA1977R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
25
A
13
48
(0.22)
0.5 ± 0.2
(8.0)
24
37
12
1
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
1.5 – 0.1
+ 0.08
0.18 – 0.03
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER/PALLADIUM
PLATING
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 16 –