CXB1581Q Fibre Channel Transmitter Description The CXB1581Q is a transmitter IC with a built-in PLL for high-speed serial data transmission. It can be used together with the receiver IC CXB1582Q as a chip set, and 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit operation can be selected. 80 pin QFP (Plastic) Features • Conforms to ANSI X3T11 Fibre channel standard • Supports GLM (Gigabaud Link Module) interface • Built-in PLL for synthesizing a low-jitter clock • Single 3.3V power supply or dual 3.3V/5V power supply (for 5V TTL interface) operation can be selected. • Low power consumption: 830mW (Typ.) when operating with a single 3.3V power supply • 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit operation can be selected. • Test pattern (±K28.5) generation circuit Applications Fibre channel 1062.5Mbaud and 531.25Mbaud communications NC LBEN SDSEL SDDIS R_FLT LDALM VEEG VCCG VCCG CLR∗ VCCP VCCP REXT VEEP1 VEEP1 VEEP2 LPF_B LPF_A Pin Configuration TCLKSEL∗ ECLKSEL∗ Structure Bipolar silicon monolithic IC 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VEEE 61 40 NC 39 ALTSEL∗ VEEE 62 EXCLK∗ 63 38 TPGEN EXCLK 64 SDIN∗ 65 37 PPSEL 36 SDRSEL SDIN 66 35 BYTSEL VCCE 67 34 TBC_IN VCCE 68 33 VCCG SDOUT∗ 69 32 VEEG SDOUT 70 31 TX19 VCCE 71 LBOUT∗ 72 30 TX18 29 TX17 LBOUT 73 28 TX16 VCCE 74 27 TX15 VCCE 75 26 TX14 PSOUT∗ 76 25 TX13 PSOUT 77 24 TX12 VEEE 78 23 TX11 TBC_OUT VCCT3 VCCT5 TX09 FAULT VCCG VEET LKDT∗ TX08 9 10 11 12 13 14 15 16 17 18 19 20 TX06 8 TX07 7 TX05 6 TX04 5 TX03 4 TX02 3 TX00 2 TX01 1 VEET 21 VEEG VEEG 22 TX10 TJMON2 80 VCCG TJMON1 79 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95912A64-ST CXB1581Q Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V) Item Symbol Max. Unit –0.3 4 V VCCG – 2, or –0.3 VCCG + 5, or 5.5 V Min. Typ. Supply voltage (excluding VCCT5) VCC Supply voltage for TTL output VCCT5 TTL DC input voltage VI_T –0.5 5.5 V ECL DC input voltage VI_E VCC – 2 VCC V ECL differential input voltage VIS_E –2 2 V TTL output current (High level) IOH_T –20 0 mA TTL output current (Low level) IOL_T 0 20 mA ECL output current IO_E –30 0 mA Operating ambient temperature Ta –55 70 °C Storage temperature Tstg –65 150 °C Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V) During single 3.3V power supply operation Item Symbol Min. Typ. Max. Unit 3.3 3.465 V 70 °C Supply voltage (including VCCT5) VCC 3.135 Ambient temperature Ta 0 During dual 3.3V/5V power supply operation (VCCT3 open) Item Symbol Min. Typ. Max. Unit Supply voltage (excluding VCCT5) VCC 3.135 3.3 3.465 V Power supply for TTL output VCCT5 4.75 5 5.25 V Ambient temperature Ta 70 °C –2– 0 CXB1581Q SDDIS LBEN SDSEL TPGEN ALTSEL∗ SDRSEL BYTSEL Block Diagram SDIN SDOUT 1 0 SDIN∗ SDOUT∗ LBOUT 53.125Mbaud TX00 to 09 10 LBOUT∗ 10 Parallel Data Input Buffer P/S Converter 531.25 or 1062.5Mbaud 53.125Mbaud TX10 to 19 10 1 0 PSOUT R Q RSFF S FAULT 10 PSOUT∗ PPSEL TBC_EN TBC_IN 53.125MHz LPF_A 53.125MHz PLL LPF_B 531.25 or 1062.5MHz TBC OUT 1 0 REXT LKDT∗ –3– LDALM TCLKSEL∗ EXCLK∗ R_FLT ECLKSEL∗ EXCLK CXB1581Q Pin Description Pin No. Type Typical pin I/O voltage Equivalent circuit Description 1, 21, VEEG 32, 49 Power supply 0V — Negative power supplies for internal logic gate. 2, 20, 33,50, VCCG 51 Power supply 3.3V — Positive power supplies for internal logic gate. Power supply 0V — Negative power supplies for TTL output. 3, 4 Symbol VEET VCCT5 VCCT3 5 LKDT∗ TTL output LKDT∗ TTL level PLL lock detection signal output. This pin outputs low level when the PLL is locked to TBC_IN and operating normally, and high level when the PLL is not operating normally. VEET VCCT5 VCCT3 6 FAULT TTL output TTL level FAULT FAULT signal output. This pin is used for the FAULT signal in the GLM standard. This pin outputs high level at the rising edge of LDALM and low level at the falling edge of R_RLT. (See Table 3.) VEET VCCT5 VCCT3 7 TBC_OUT TTL output TTL level TBC_OUT VEET –4– Transmission byte clock output (53.125MHz). This clock is generated by frequency-dividing the transmission bit clock (1.0625GHz or 531.25MHz). CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCT5 8 VCCT3 VCCT3 Power 3.3V or open supply VCCG VEET VCCT5 9 VCCT5 Power supply VCCT3 3.3V or 5V VCCG Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; leave open when using the IC with a dual 3.3V/5V power supply. Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; to 5V when using the IC with a dual 3.3V/5V power supply. VEET VCCG 10 to 19 TX00 to 09 TTL input TTL level Parallel data inputs (Byte_0). TX00 to 09 VEET VEET VCCG 22 to 31 TX10 to 19 TTL input TTL level Parallel data inputs (Byte_1). TX10 to 19 VEET VEET –5– CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 34 TBC_IN TTL input TTL level Transmission byte clock input (53.125MHz). TBC_IN VEET VEET VCCG 35 BYTSEL TTL input TTL level Byte selection. (See Table 2.) BYTSEL VEET VEET VCCG 36 SDRSEL TTL input TTL level Serial data transmission rate selection. Setting this pin to low level selects 531.25Mbaud mode and to high level selects 1.0625Gbaud mode. SDRSEL VEET VEET VCCG 37 PPSEL TTL input TTL level Ping-Pong mode selection. (See Table 2 and the Timing Charts.) PPSEL VEET VEET –6– CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 38 TPGEN TTL input TTL level TPGEN VEET VEET VCCG 39 ALTSEL∗ TTL input TTL level ALTSEL∗ VEET 40, 41 NC VEET Test pattern generation control. Inputting high level to this pin generates positive or alternating disparity K28.5 (one of the 8B10B conversion codes) as the serial transfer data. Alternating disparity selection. The test pattern generated when TPGEN is set to high level becomes alternating disparity K28.5 if this pin is set to low level, and positive disparity K28.5 if this pin is set to high level. No connection. Open VCCG 42 TTL ECLKSEL∗ input TTL high level or 3.3V External clock selection. When this pin is set to low level, the clock input to EXCLK is used as the transmission bit clock. ECLKSEL∗ VEET VEET VCCG 43 TCLKSEL∗ TTL input TTL high level or 3.3V Transmission bit clock output selection. When this pin is set to low level, the transmission bit clock is output from PSOUT. (See Table 1.) TCLKSEL∗ VEET VEET –7– CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 44 SDSEL TTL input TTL level SDIN selection. When this pin is set to high level, the data input to SDIN is output unmodified from SDOUT. SDSEL VEET VEET VCCG 45 LBEN TTL input TTL level Loop-back enable. When this pin is set to high level, LBOUT functions as the serial data output. (See Table 1.) LBEN VEET VEET VCCG 46 SDDIS TTL input TTL level SDOUT disable. Setting this pin to high level fixes SDOUT to low level and SDOUT∗ to high level. (See Table 1.) SDDIS VEET VEET VCCG 47 R_FLT TTL input TTL level Reset FAULT. FAULT output goes to low level at the falling edge of this signal. (See Table 3.) R_FLT VEET VEET –8– CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCG 48 LDALM TTL input TTL lebel Laser diode alarm signal input. FAULT output goes to high level at the rising edge of this signal. (See Table 3.) LDALM VEET VEET VCCG 52 CLR∗ TTL input TTL high level or 3.3V Internal counter clear. Setting this signal to low level clears the internal counter. CLR∗ VEET 53, 54 VCCP Power supply VEET 3.3V Positive power supplies for internal PLL. — VCCP 55 REXT External part connection pin — REXT VEEP2 Connects the resistor which determines the VCO center frequency. Connect a 4.7kΩ resistor between this pin and VEEP1. (See Notes on Operation and Fig. 1.) 56, 57 VEEP1 Power supply 0V — Negative power supplies for internal PLL. 58 VEEP2 Power supply 0V — Negative power supply for internal PLL. –9– CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCP 59 LPF_A External part connection pin LPF_A External loop filter connection. (See Notes on Operation and Fig. 1.) LPF_B — VEEP2 VEEP1 VCCP LPF_A 60 LPF_B External part connection pin External loop filter connection. (See Notes on Operation and Fig. 1.) LPF_B — VEEP2 61, 62, VEEE 78 Power supply VEEP1 VCCE 64 63 EXCLK EXCLK∗ ECL input (differen -tial) VCCG EXCLK Open VCCE – 1.3V EXCLK∗ VEEE VEEG VCCE 66 65 SDIN SDIN∗ ECL input (differen -tial) Negative power supplies for ECL I/O. — 0V External clock inputs. When ECLKSEL∗ is set to low level, the clock input to these pins is used as the transmission bit clock. EXCLK is biased to become low level when left open. VCCG SDIN VCCE – 1.3V ECL level SDIN∗ VEEE VEEG – 10 – Serial data inputs. When SDSEL is set to high level, the data input to these pins is output unmodified from SDOUT. CXB1581Q Pin No. Symbol 67, 68, 71, 74, VCCE 75 Type Typical pin I/O voltage Equivalent circuit Description Power supply 3.3V — Positive power supplies for ECL I/O. VCCE 70 69 SDOUT SDOUT∗ ECL output (differen -tial) SDOUT ECL level SDOUT∗ VEEE Serial data outputs for transmission. The serial data order is TX00 → TX19 for 1GHz mode and TX00 → TX09 (Byte_0) or TX10 → TX19 (Byte_1) for 531MHz mode. VCCE 73 72 LBOUT LBOUT∗ ECL output (differen -tial) LBOUT ECL level LBOUT∗ Serial data outputs for loop-back test. VEEE VCCE 77 76 PSOUT PSOUT∗ ECL output (differen -tial) PSOUT ECL level PSOUT∗ Parallel/serial conversion outputs. These outputs are enabled when SDSEL is high level. (See Table 1.) VEEE VCCE TJMON1 79 80 TJMON1 TJMON2 Test pin Junction temperature measurement. Open TJMON2 VEEE – 11 – CXB1581Q Description of Operation Tables TCLKSEL∗ SDSEL LBEN SDDIS SDOUT LBOUT PSOUT L L L L Serialized Data Fixed to Low Trans. Bit Clock L L L H Fixed to Low Fixed to Low Trans. Bit Clock L L H L Serialized Data Serialized Data Trans. Bit Clock L L H H Fixed to Low Serialized Data Trans. Bit Clock L H L L SDIN Fixed to Low Trans. Bit Clock L H L H Fixed to Low Fixed to Low Trans. Bit Clock L H H L SDIN SDIN Trans. Bit Clock L H H H Fixed to Low SDIN Trans. Bit Clock H L L L Serialized Data Fixed to Low Fixed to Low H L L H Fixed to Low Fixed to Low Fixed to Low H L H L Serialized Data Serialized Data Fixed to Low H L H H Fixed to Low Serialized Data Fixed to Low H H L L SDIN Fixed to Low Serialized Data H H L H Fixed to Low Fixed to Low Serialized Data H H H L SDIN SDIN Serialized Data H H H H Fixed to Low SDIN Serialized Data Table 1. ECL Output Selection Table SDRSEL BYTSEL PPSEL L L L 531Mbaud, Byte0 selected Trans. Byte Clock L L H 531Mbaud, Byte0 selected Fixed to Low L H L 531Mbaud, Byte1 selected Trans. Byte Clock L H H 531Mbaud, Byte1 selected Fixed to Low H L L 1062.5Mbaud, Ping-Pong OFF Trans. Byte Clock H L H 1062.5Mbaud, Ping-Pong ON Trans. Byte Clock H H L 1062.5Mbaud, Ping-Pong OFF Fixed to Low H H H 1062.5Mbaud, Ping-Pong ON Fixed to Low Operation mode TBC_OUT Table 2. Operation Mode Selection Table – 12 – CXB1581Q LDALM R_FLT FAULT L H→L L L→H L H H→L L H L L→H H L H→L L L→H L H H L→H H H H→L L Table 3. FAULT Function Table Timing Charts Tp_TBC Tl_TBC Th_TBC 2.0V 1.5V 0.8V Tir_TBC TBC_IN Ts Tif_TBC Th 2.0V VALID VALID 1.5V 0.8V Tir_TX Tif_TX TX00 to 19 or TX00 to 09 during Ping-Pong mode Ts VALID Th VALID TX10 to 19 during Ping-Pong mode – 13 – 1.5V CXB1581Q Electrical Characteristics DC Characteristics (under the recommended operating conditions) Item Symbol Min. TTL high level input voltage aVIH_T TTL low level input voltage VIL_T TTL high level input current IIH_T TTL low level input current IIL_T Typ. Max. Unit Conditions 2 5.5 V 0 0.8 V 20 µA VIH = VCC –400 µA VIL = 0 2.2 V IOH = –0.4mA 2.6 V IOH = –0.4mA 0.5 V IOL = 2mA 0.5 V IOL = 4mA TTL high level output voltage Single 3.3V power supply VOH-T Dual 3.3V/5V power supply TTL low level output voltage Single 3.3V power supply VOL_T Dual 3.3V/5V power supply ECL high level input voltage VIH_E VCC – 1.17 VCC – 0.88 V ECL low level input voltage VIL_E VCC – 1.81 VCC – 1.48 V 200 1000 mV VOH_E VCC – 1.05 VCC – 0.81 V 50Ω terminated to VCC – 2V ECL low level output voltage VOL_E VCC – 1.81 VCC – 1.55 V 50Ω terminated to VCC – 2V mV 50Ω terminated to VCC – 2V ECL differential input voltage VIS_E ECL high level output voltage ECL output amplitude VOS_E 650 Output pins open Current consumption Single 3.3V power supply ICC Dual 3.3V/5V power supply 250 313 mA 237 13 297 17 mA mA Power consumption Single 3.3V power supply Dual 3.3V/5V power supply AC coupling input 3.3V power supply 5V power supply (VCCT5) Output pins open PD 0.83 1.1 W 0.85 1.12 W – 14 – CXB1581Q AC Characteristics (under the recommended operating conditions) Item Symbol Min. Typ. Max. Unit Conditions TX00 to 19 rise time Tir_TX 4.8 ns 0.8 to 2.0V TX00 to 19 fall time Tif_TX 4.8 ns 2.0 to 0.8V TBC_IN rise time Tir_TBC 2.4 ns 0.8 to 2.0V TBC_IN fall time Tif_TBC 2.4 ns 2.0 to 0.8V Tor_T 3.5 ns 0.8 to 2.0V, CL = 10pF 3.2 ns 0.6 to 2.2V, CL = 10pF 3.5 ns 2.0 to 0.8V, CL = 10pF 3.2 ns 2.2 to 0.6V, CL = 10pF TTL output rise time Single 3.3V power supply Dual 3.3V/5V power supply TTL output fall time Single 3.3V power supply Tof_T Dual 3.3V/5V power supply ECL output rise time Tor_E 400 ps 20 to 80%, CL ≤ 2pF ECL output fall time Tof_E 400 ps 20 to 80%, CL ≤ 2pF TBC_IN cycle Tp_TBC 18.2 22.2 ns TBC_IN low time Tl_TBC 6 ns TBC IN high time Th_TBC 6 ns TX setup time Ts 1.8 ns TX hold time Th 1.8 ns Deterministic jitter (p-p) DJ 0.02 0.07 Ul ±K28.5 serial data output Random jitter (p-p) RJ 0.18 0.23 Ul Serial data output 18.8 – 15 – CXB1581Q Electrical Characteristics Measurement Circuit (See Fig. 3 Power Supply Circuits regarding the power supply.) II_T A Measurement device TTL_IN TTL_OUT VI_T V Vo_T Io_T (a) TTL I/O DC characteristics measurement circuit Measurement device Pulse generator TTL_IN Probe TTL_OUT Oscilloscope CL CL = 10pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E A Measurement device ECL_IN ECL_OUT VI_E 50Ω V VO_E VCCE – 2V (c) ECL I/O DC characteristics measurement circuit VCCE – 2V 50Ω Pulse generator VCCE – 2V Measurement device ECL_IN ECL_IN∗ 50Ω ECL_OUT Oscilloscope ECL_OUT∗ 50Ω 50Ω 50Ω Transmission Line VCCE – 2V VCCE – 2V CL ≤ 2pF (input capacitance of the measurement instrument and floating capacitance) (d) ECL I/O AC characteristics measurement circuit VCCE – 2V Measurement device 26.5625MHz Pulse pattern generator 50Ω TBC_IN 53.125MHz SDOUT Oscilloscope 1.0625Gbps 20 53.125MBPS Triger TX00 to 19 SDOUT∗ 50Ω VCCE – 2V (e) Jitter characteristics measurement circuit – 16 – CXB1581Q Notes on Operation 1. Clock synthesizer (PLL) The CXB1581Q has a built-in PLL-based clock synthesizer for generating the serial data transmission frequency clock (transmission bit clock) from TBC_IN. This clock synthesizer requires an external loop filter and an external resistor which determines the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the IC pins (Pins 55, 59 and 60) which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. In addition, resistor R3 should have a small temperature coefficient to reduce the temperature dependence of the VCO oscillation frequency. 55 56 57 58 R3 60 59 R1 R2 C1 R1: 1.5kΩ R2: 1.5kΩ R3: 4.7kΩ C1: 0.01µF Fig. 1. External Part Circuit and Recommended Constants – 17 – CXB1581Q 2. ECL input circuit The ECL differential input pins (excluding EXCLK) of the CXB1581Q are biased to VBB (VCC – 1.3V) via an 18kΩ resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 18kΩ 160Ω 160Ω 3.3V ECL output buffer ECL differential input buffer (a) ECL differential signal from 3.3V ECL output buffer VCC = GND, VEE = –4.5V 0.01µF 0.01µF 330Ω ECL100K output buffer VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 18kΩ 330Ω ECL differential input buffer VEE (b) ECL differential signal from ECL100K output buffer 0.01µF VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 50Ω TRANS. LINE 0.01µF 50Ω 18kΩ 50Ω ECL differential input buffer VTT (VCC – 2V) (c) ECL differential signal from 50Ω transmission line VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 50Ω TRANS. LINE 50Ω 0.01µF 18kΩ 0.01µF 18kΩ VTT (VCC – 2V) ECL differential input buffer (d) ECL single signal from 50Ω transmission line Fig. 2. ECL Input Circuits – 18 – CXB1581Q 3. Power supply Power can be supplied to the CXB1581Q by either a single 3.3V power supply or a dual 3.3V/5V power supply. When a TTL output high level of 2.2V is sufficient (for example, when only interfacing with a 3.3V CMOS), use a single 3.3V power supply. When a TTL output high level of greater than 2.2V is required (for example, when interfacing with a 5V TTL/CMOS), use a dual 3.3V/5V power supply. VCCT5 VCCT3 VCCE VCCG 3mH 3.3V 22µF 3mH 0.1µF 22µF VEET VCCP VEEE 0.1µF 22µF VEEG 0.1µF VEEP1 VEEP2 (a) Single 3.3V power supply VCCT5 VCCE VCCG VCCP 3mH 5.0V 22µF 0.1µF VEET 22µF 3.3V VEEE 0.1µF VEEG (b) Dual 3.3V/5V power supply Fig. 3. Power Supply Circuits – 19 – 22µF 0.1µF VEEP1 VEEP2 CXB1581Q Example of Representative Characteristics Jitter transfer (1.0625GHz operation) 5 R1 = R2 = 1.5kΩ 0 Jitter transfer [dB] –5 R1 = R2 = 1.0kΩ –10 –15 –20 C1 = 0.01µF R3 = 4.7kΩ Ta = 27°C –25 101 102 103 104 105 Modulation frequency [MHz] 106 107 108 RJ temperature characteristics (SDOUT, 1.0625GHz operation) 15 RJ [ps-RMS-] 14 13 12 11 R1 = R2 = 1.5kΩ C1 = 0.01µF R3 = 4.7kΩ TBC_IN: 53.125MHz 10 –20 0 20 40 Ta [°C] – 20 – 60 80 CXB1581Q Exampe of RJ measurement (SDOUT, 1.0625GHz operation) R1 = R2 = 1.5kΩ C1 = 0.01µF R3 = 4.7kΩ Ta = 27°C RJ = 12.1ps (RMS) [50ps/div] [200mV/div] Eye pattern (SDOUT, 1.0625GHz operation) R1 = R2 = 1.5kΩ C1 = 0.01µF R3 = 4.7kΩ Ta = 27°C [200ps/div] – 21 – CXB1581Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 0.1 41 40 80 21 (15.0) 61 + 0.15 0.3 – 0.1 20 ± 0.12 M 0° to 10° 0.5 ± 0.2 1 0.65 + 0.15 0.1 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-80P-L03 LEAD TREATMENT SOLDER PLATING EIAJ CODE LQFP080-P-1414 LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.6g JEDEC CODE – 22 –