CXA7000R LCD Driver Description The CXA7000R is a driver IC developed for use with Sony polycrystalline silicon TFT LCD panels. It supports 10-bit digital input, and the input data is analog demultiplexed into 6 phases and output. The CXA7000R can directly drive an LCD panel, and the VCOM setting circuit and precharge pulse waveform generator are also on-chip. 64 pin LQFP (Plastic) Features • Supports 10-bit input • Supports signals up to XGA • Low output deviation by on-chip output offset cancel circuit • On-chip timing generator with ECL • VCOM voltage generation circuit • Precharge pulse waveform generation circuit Applications LCD projectors and other video equipment Absolute Maximum Ratings (VSS = 0V) • Supply voltage VCC 16 V VDD 5.5 V • Operating temperature Topr –20 to +70 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1250 mW Recommended Operating Conditions • Supply voltage VCC 15.0 to 15.5 VDD 4.75 to 5.25 • Operating temperature Topr –20 to +70 V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01821A22 CXA7000R SL_DAT DIRC F/H_CNT VREF_O VREF_I VDD5 PS GND GND PRG SID_LV PRG_LV SID_OUT VCC15 VCOM_OFST VCOM_OUT Block Diagram 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCOM_Gen. SID_Gen. TEST 49 Vref Gen. STATUS 50 32 PVCC 31 SH_OUT1 Line inv. D_IN9 51 30 NC Offset Cancel D_IN8 52 29 SH_OUT2 Line inv. S/H D_IN7 53 S/H S/H 28 NC Offset Cancel D_IN6 54 S/H S/H S/H S/H S/H S/H 27 SH_OUT3 Line inv. D_IN5 55 26 GND Offset Cancel GND 56 25 PGND D/A GND 57 S/H S/H S/H S/H S/H S/H 24 PGND Line inv. D_IN4 58 23 GND Offset Cancel D_IN3 59 22 SH_OUT4 S/H D_IN2 60 S/H S/H Line inv. 21 NC Offset Cancel D_IN1 61 20 SH_OUT5 Line inv. D_IN0 62 19 NC Offset Cancel MCLK 63 18 SH_OUT6 FRP CAL_PLS 8 SHST POSCNT0 POSCNT1 POSCNT2 POSCNT3 SHTEST GND 9 10 11 12 13 14 15 16 DCFBOFF 7 GND 6 CAL_H 5 CAL_L 4 SIG_OFST 3 SIG.C 2 17 PVCC NC 1 FRP Offset Cancel Control GND TG MCLKX 64 –2– CXA7000R Pin Description Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD 50k 1 FRP I High: ≥2.0V Low: ≤0.8V 192 1 LCD panel AC drive inversion timing input. High: inverted Low: non-inverted See the Timing Chart. GND VDD 50k 2 SHST I High: ≥2.0V Low: ≤0.8V 192 2 GND VDD 3 4 5 6 POSCNT0 POSCNT1 POSCNT2 POSCNT3 50k 3 I High: ≥2.0V Low: ≤0.8V 4 192 5 6 Internal sample-and-hold timing circuit reset pulse input. This pin is also used as the offset cancel level insertion timing input. A reset is applied to the internal timing generator at the falling edge. Output phase adjustment. The output phase is adjusted in MCLK period units when SL_DAT is high, and in 1/2 MCLK period units when SL_DAT is low. GND VDD VCC 20µ 30k 11 SIG.C I 1 to 5.0V 11 Signal center voltage (inversion folded voltage) adjustment input. The SH_OUT output center voltage can be adjusted in the range from 7.0 to 8.0V. GND VDD VCC 10µ 30k 12 SIG_OFST I 0 to 5.0V 12 GND Output signal offset adjustment from signal center voltage. The SH_OUT output 100% white level (at 3FF input) voltage can be adjusted in the range from 0 to 1V from the center voltage. VCC 40µ 13 14 CAL_L CAL_H I/O 3.0 to 6.0V 9.0 to 12.0V 1k 145 13 14 GND –3– Level output for canceling the offset between channels. Connect the CAL_L and CAL_H, between ICs when using two CXA7000R. CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD 24k 16 DCFBOFF I Offset cancel function off. Normally connect to GND to use with the offset cancel function on. High (offset cancel function off) when open. 24k 145 GND 16 GND PVCC 18 18 20 22 27 29 31 20 300 SH_OUT6 to SH_OUT1 22 O 1.5 to 13.5V 27 300 29 Demultiplexed output of AC inverse driven video signals. Can be connected directly to the LCD panel. 31 GND VCC 80µ 100k 33 VCOM_OUT O 500 145 5.0 to 8.0V 33 500 LCD panel common voltage output. Can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c – 2V by VCOM_OFST. GND VDD VCC 80µ 2k 34 VCOM_OFST I 0 to 5.0V 34 100 LCD panel common voltage adjustment. VCOM_OUT can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c – 2V by inputting 0 to 5V. GND VCC 100k 0.2p 36 SID_OUT O 145 36 1.5 to 13.5V 100k 0.2p GND –4– Precharge waveform output. These pins cannot directly drive the LCD panel, so input to the LCD panel with an external buffer. CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD VCC Precharge level setting. Adjusts the SID_OUT and SID_OUTX output potential. PRG_LV is reflected when the PRG input pin (Pin 60) is high, and SID_LV is reflected when PRG is low. 29µ 37 38 PRG_LV SID_LV I 1.0 to 5.0V 50k 37 50k 38 GND VDD VCC 100k 39 PRG I 10k High: ≥2.0V Low: ≤0.8V 39 50µ Timing pulse input for switching the Pin 36 output levels. (See PRG_LV (Pin 37) and SID_LV (Pin 38).) GND VDD 70µ 44 VREF_I I 3.2V 10µ 44 1k 33.3k Internal D/A converter reference voltage input. Normally connect directly to VREF_O. 280µ GND VDD 2k 45 VREF_O O 45 3.2V 20k 20µ Reference voltage output. Normally connect directly to VREF_I, and connect to GND through a 0.5 to 1.0µF capacitor. 12.4k GND VDD 50k 46 F/H_CNT I High: ≥2.0V Low: ≤0.8V Open: Low 192 46 200k SH_OUT output timing selection. High: SH_OUT1 to SH_OUT3 and SH_OUT4 to SH_OUT6 are output at different timing. Low: SH_OUT1 to SH_OUT6 are output at the same timing. GND VDD 50k 47 DIRC I High: ≥2.0V Low: ≤0.8V 192 47 GND –5– Scan direction setting. High: output as a time series in ascending order of output pin symbol (in order from SH_OUT1 to SH_OUT6) Low: output in descending order CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD 50k 48 SL_DAT I High: ≥2.0V Low: ≤0.8V Open: Low Digital input mode switch setting. High: when using master/slave mode two CXA7000R. Low: when using normal mode one CXA7000R. 192 48 200k GND VDD 50k 200k 50 STATUS I High: ≥2.0V Low: ≤0.8V 192 50 GND Master/slave setting when using two CXA7000R. High: master IC. Offset cancel level is output. Low: slave IC. This pin is left open (high) when using one CXA7000R. VDD 51 to 55 58 to 62 50k D_IN9 to D_IN0 I 192 High: ≥2.0V Low: ≤0.8V 51 to 55 Digital data input. 58 to 62 GND VDD 63 64 MCLK MCLKX I PECL differential (amplitude 0.4V or more between VDD to 2V) or TTL input 140k 8k 140k 100µ 60k 1k 63 1k 64 60k Dot clock input. PECL differential input or TTL input. For TTL input, input to MCLK and connect MCLKX to GND through a capacitor. GND VDD 70k 42 PS I 5V Test. Normally connect to VDD. 42 180k 30µ GND 24, 25 PGND GND Power GND. 17, 32 PVCC 15.5V Power VCC. 35 VCC15 15.5V 15V power supply. 43 VDD5 5V 5V power supply. –6– CXA7000R Pin No. Symbol I/O Standard voltage level 8, 9, 15, 23, 26, GND 40, 41, 56, 57 Equivalent circuit Description GND. GND NC. These pins are not connected to anything. 10, 19, 21, 28, NC 30 VDD 20k 20k 20k 250k 7 SHTEST I 2.5V 20k Test. Leave open. 192 7 250k 10µ 10µ GND VDD 1µ 2k 192 49 TEST O 49 1.7 to 3.2V 20µ GND –7– DAC output monitor test. Normally connect to VDD. CXA7000R 48 MCLKX 34 33 VCC15 SID_OUT PRG_LV SID_LV PRG GND GND PS VDD5 VREF_I VREF_O F/H_CNT 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PVCC SH_OUT1 270p NC SH_OUT2 270p NC SH_OUT3 270p GND PGND PGND GND SH_OUT4 270p NC SH_OUT5 270p NC SH_OUT6 270p PVCC A 16 DCFBOFF MCLK 35 GND D_IN0 36 CAL_H D_IN1 37 CAL_L D_IN2 38 SIG_OFST D_IN3 39 SIG.G D_IN4 40 NC GND 41 GND GND 42 GND D_IN5 43 SHTEST D_IN6 A POSCNT3 D_IN7 44 POSCNT2 D_IN8 45 POSCNT1 D_IN9 46 POSCNT0 STATUS 47 SHST TEST FRP VDD DIRC SL_DAT A VCOM_OUT 47p VCOM_OFST VDD 1µ VCC Electrical Characteristics Measurement Circuit VCC VCC 15.5V –8– VDD 5V CXA7000R Electrical Characteristics No. Item Symbol 1 Digital input resolution n 2 Digital input setup time TS 3 Digital input hold time 4 Measurement points Measurement conditions Min. Typ. Max. Unit — 10 — bit SHST and D_IN[9:0] minimum setup time relative to MCLK input. 2 — — ns TH SHST and D_IN[9:0] minimum hold time relative to MCLK input. 3 — — ns MCLK input frequency range 1 fMCLK1 SL_DAT: 5V; maximum frequency at which the internal timing generator and D/A converter operate normally. 60 — 100 MHz 5 MCLK input frequency range 2 fMCLK2 SL_DAT: 0V; maximum frequency at which the internal timing generator and D/A converter operate normally. 30 — 80 MHz 6 VREF_I input voltage range VVREF_I VREF_I input voltage range at which the D/A converter operate normally. 2.7 3.2 3.5 V 7 VREF_O output VVREF_O voltage range Measure the VREF_O (Pin 45) voltage. 3.1 3.2 3.3 V 8 SH_OUT amplitude Measure the SH_OUT1 voltage 4.39 difference at D_IN[9:0]: 000h and 3FFh. 4.5 4.64 V 9 SH_OUT minimum amplitude Lower the VREF_I voltage and adjust the amplitude; minimum amplitude at which SH_OUT1 can be output at D_IN[9:0]: 000h and 3FFh. — — 150 — V/µs VSHOUTp-p VOUT1 VOUTMINp-p VOUT1 3.9 V SROUT VOUT1 to VOUT6 Load capacitance = 270pF; measure slew rate at 10 to 90% of output waveform rise and fall when D_IN[9:0] 150 is varied from 000h to 3FFh and from 3FFh to 000h. SH_OUT 11 minimum output voltage VMIN VOUT1 to VOUT6 Minimum voltage at which sampleand-hold outputs VOUT1 to VOUT6 can be output. 1.5 — — V SH_OUT 12 maximum output voltage VMAX VOUT1 to VOUT6 Maximum voltage at which sampleand-hold outputs VOUT1 to VOUT6 can be output. — — 13.5 V Output deviation 13 between DOUT1 channels 1 VOUT1 to VOUT6 Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 200h. — 3 10 mVp-p Output deviation 14 between DOUT2 channels 2 VOUT1 to VOUT6 Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 000h or 3FFh. — 10 40 mVp-p Output deviation 15 DIC1 between ICs 1 VOUT1 to VOUT6 Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 200h. (when using two CXA7000R) — 10 — mVp-p 10 SH_OUT slew rate –9– CXA7000R No. Item Measurement Symbol points Output deviation 16 DIC2 between ICs 2 Measurement conditions Min. Typ. Max. Unit VOUT1 to VOUT6 Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 000h or 3FFh. (when using two CXA7000R) — 20 — mVp-p 17 SID output gain 1 ASID1 VSID_LV VSID PRG: 0V; measure VSID_LV and VSID at FRP: 0V, and VSID_LV at FRP: 5V. Calculate as ASID1 = VSID/VSID_LV. 1.9 2 2.1 times 18 SID output gain 2 ASID2 VPRG_LV VSID PRG: 5V; measure VPRG_LV and VSID at FRP: 0V, and VPRG_LV at FRP: 5V. Calculate as ASID2 = VSID/VPRG_LV. 1.9 2 2.1 times VSID Load capacitance = 47pF, PRG: 0V; input a repeating high/low pulse to FRP (Pin 1), and apply DC input voltage so that VSID is 4V/10V. Measure slew rate at 10 to 90% of output waveform rise and fall. 27 50 — V/µs VOUT1 VOUT1 center voltage when SIG.C (Pin 11) is varied from 0 to 5V. 7 — 8 V SH_OUT offset 21 VSIGOFST adjustable range VOUT1 D_IN[9:0]: 3FFh, FRP: 0V; value obtained by subtracting VOUT1 from VOUT1 center voltage when SIG_OFST (Pin 12) is varied from 0 to 5V. 0 — 1 V 22 VCOM VCOM adjustable range VCOM VCOM_OUT voltage when VCOM_OFST (Pin 34) is varied from 0 to 5V. Vc – 2.5 — Vc V 23 VDD current consumption IDD IVDD IDD = IVDD — 52 — mA 24 VCC current consumption ICC IVCC1 IVCC2 ICC = IVCC1 + IVCC2 — 18 — mA Current consumption in 25 IPS power saving mode IVDD IVCC1 IVCC2 GND (Pin 42), ICC = IVDD + IVCC1 + IVCC2 — 28 — mA 19 SID output slew rate 20 Signal center VSIG adjustable range SRSID 26 Differential linearity error 27 Integral linearity ILE error DLE — VVREF_I = 3.2V –0.5 0.7 LSB — VVREF_I = 3.2V –1.5 0.4 LSB – 10 – CXA7000R Description of Operation The flow of internal operations is described below. The digital signals input to D_IN0 to D_IN9 are internally D/A converted into approximately 1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 6 phases is amplified by a factor of three times, inverted at the signal center potential according to FRP, and output. The output level relative to the digital input changes according to the following settings. A: SIG_OFST voltage B: VREF_I voltage VCC C: SIG.C voltage B A Signal Center A 1023 C B 512 0 GND Digital IN SH_OUT 1. Digital input block The CXA7000R can be set to master/slave mode, single mode and left/light inversion. This makes it possible to support various systems. In master/slave mode, the even and odd data is internally selected respectively and input to the D/A converter. 2. D/A converter block The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a maximum 1.5Vp-p with respect to input data of 000h to 3FFh. 3. Sample-and-hold (S/H) block The D/A converter outputs are input to the sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3 ... SH_OUT6. For reverse scan, this order is inverted and the signals are output in descending order. Connect the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown on the following pages. These pulses are not output and are used only inside the IC. – 11 – CXA7000R Master/slave mode Selector D_IN1 D_IN[9:0] D D DAC L 10bit D_IN2 H D DAC_O D S/H STATUS MCLK MCLK/2 D_IN[9:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 MCLK D_IN1 D_IN2 DAC_O 0 1 2 3 4 1 1 5 6 3 7 8 5 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 7 9 11 13 15 17 19 21 23 25 27 3 DIRC: H SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 F/H_CNT: L SH3A_1_6 CH1 to CH6 simultaneous output timing F/H_CNT: H SH3B_1_3 CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing SH3B_4_6 DIRC: L SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 F/H_CNT: L SH3A_1_6 CH1 to CH6 simultaneous output timing F/H_CNT: H SH3B_1_3 CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing SH3B_4_6 – 12 – CXA7000R Single mode DAC 10bit D_IN[9:0] D_IN1 DAC_O D_IN2 D D D S/H MCLK D_IN[9:0] –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MCLK D_IN1 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 D_IN2 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 –1 0 DAC_O 1 DIRC: H SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 CH1 to CH6 simultaneous output timing F/H_CNT: L SH3A_1_6 F/H_CNT : H SH3B_1_3 CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing SH3B_4_6 DIRC: L SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 F/H_CNT: L SH3A_1_6 CH1 to CH6 simultaneous output timing F/H_CNT: H SH3B_1_3 CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing SH3B_4_6 – 13 – CXA7000R 4. Timing generator (TG) block The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse and output deviation cancel circuit. The various operating modes can be designated by the pin settings. The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and MCLKX input period as 1clk. SHST FRP 30clk or more 1µs or more The CXA7000R can select various operating modes according to the timing generator block settings. These settings are described below. • SL_DAT (Pin 48) Operation mode selection. Master/slave mode is selected which is common with digital input of two ICs when set to high level, and single mode is selected with one IC when set to low level. In case of the former, connect 10-bit input as short as possible between two ICs and select which data of odd or even is obtained by STATUS (Pin 50). • DIRC (Pin 47) Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending order (SH_OUT1 to SH_OUT6) when set to low level. Also, the output is varied as shown below in combination with STATUS (Pin 50). D_IN[9:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SL_DAT: L DIRC: L SL_DAT: H DIRC: H SH_OUT1: 6 SH_OUT2: 5 SH_OUT3: 4 SH_OUT4: 3 SH_OUT5: 2 SH_OUT6: 1 SH_OUT1: 1 SH_OUT2: 2 SH_OUT3: 3 SH_OUT4: 4 SH_OUT5: 5 SH_OUT6: 6 DIRC: L DIRC: H STATUS: L SH_OUT1: 11 SH_OUT2: 9 SH_OUT3: 7 SH_OUT4: 5 SH_OUT5: 3 SH_OUT6: 1 SH_OUT1: 2 SH_OUT2: 4 SH_OUT3: 6 SH_OUT4: 8 SH_OUT5: 10 SH_OUT6: 12 STATUS: H SH_OUT1: 12 SH_OUT2: 10 SH_OUT3: 8 SH_OUT4: 6 SH_OUT5: 4 SH_OUT6: 2 SH_OUT1: 1 SH_OUT2: 3 SH_OUT3: 5 SH_OUT4: 7 SH_OUT5: 9 SH_OUT6: 11 – 14 – CXA7000R • F/H_CNT (Pin 46) SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same timing. When set to high level, SH_OUT1 to SH_OUT3 and SH_OUT4 to SH_OUT6 are output at phases offset by 1/2 clock period from each other. SH_OUT4 to 6 SH_OUT4 to 6 SH_OUT1 to 3 SH_OUT1 to 3 GND GND F/H_CNT: H F/H_CNT: L • Output phase setting The phase of each SH_OUT output can be adjusted by POSCNT[3:0] (Pins 3 to 6). The phase can be set in 16 ways by 4-bit digital input. The output phase shifts backward by the clock period units when SL_DAT is high or 1/2 clock period units when SL_DAT is low each time this setting is increased by one bit. – 15 – CXA7000R 5. Calibration level generator block The CXA7000R has a built-in offset cancel circuit and generates the reference with a calibration level generator in order to minimize the deviation between channels at the center level. The 200h output level is generated at both the AC output high and low sides respectively when STATUS (Pin 50) is high level, and these levels are DC output from CAL_H and CAL_L and at the same time, these are used internally. When STATUS (Pin 50) is low level, CAL_H and CAL_L are input pins and the external offset cancel level is input. The 200h data is forcibly inserted into the video signal while the video blanking period SHST pulse is low level, and feedback is applied so that the output levels of all SH_OUT channels conform to CAL_H and CAL_L during this period. Video signal replacement period SHST FRP 200ns CAL_PLS (internal pulse) Offset cancel operation 000h 200h SH_OUT Signal center Delayed by sample-and-hold 200h 000h 6. SID signal generator block This circuit generates the precharge signal waveform used by the LCD panel. The voltage input from PRG_LV (Pin 37) and SID_LV (Pin 38) is switched by the PRG pulse (Pin 39). The PRG_LV voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 36) is inverted when FRP is high, and non-inverted when FRP is low. SID_OUT cannot directly drive the precharge signal input of the LCD panel, so they should be connected via a buffer having sufficient current supply capability. 7. VCOM potential generator block This block sets the DC common potential for the LCD panel. VCOM_OFST (Pin 33) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C. – 16 – CXA7000R Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, Ta = 25°C) Input data vs. SH_OUT voltage VREF_I voltage vs. SH_OUT voltage white-black amplitude 14 4.7 <Measurement conditions> SIG.C = 3.75V SIG_OFST = 3.6V 4.6 12 FRP = High SH_OUT voltage [V] SH_OUT white-black amplitude voltage [V] 4.8 4.5 4.4 4.3 4.2 4.1 10 8 6 FRP = Low 4 2 3.9 0 000h 3.8 2.8 2.9 3.0 3.1 VREF_I voltage [V] 3.2 3.3 200h 300h Input data (10 bits) 3FFh 12 8.5 11 <Measurement conditions> SIG_OFST = 3.6V 8.0 10 SH_OUT voltage [V] SH_OUT center voltage [V] 100h SIG_OFST voltage vs. SH_OUT voltage SIG.C voltage vs. SH_OUT center voltage 9.0 7.5 7.0 6.5 6.0 FRP = High 9 8 7 6 5 5.5 4 <Measurement conditions> SIG.C = 3.75V FRP = Low DATA = 200h 3 5.0 2.5 3.0 3.5 4.0 SIG.C voltage [V] 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SIG_OFST voltage [V] 4.5 VCOM_OFST voltage vs. VCOM_OUT voltage 7.5 <Measurement conditions> SIG.C = 3.75V 7.0 VCOM_OUT voltage [V] <Measurement conditions> SIG.C = 3.75V SIG_OFST = 3.6V 4.0 6.5 6.0 5.5 5.0 4.5 0.0 1.0 2.0 4.0 3.0 VCOM_OFST voltage [V] 5.0 – 17 – CXA7000R SID_LV voltage vs. SID_OUT voltage PRG_LV voltage vs. SID_OUT voltage 16 16 <Measurement conditions> SIG.C = 3.75V <Measurement conditions> SIG.C = 3.75V 14 12 SID_OUT voltage [V] SID_OUT voltage [V] 14 FRP = High 10 8 6 FRP = Low 12 FRP = High 10 8 6 FRP = Low 4 4 2 2 0 0 0 1 2 3 0 4 SID_LV voltage [V] 1 2 PRG_LV voltage [V] – 18 – 3 4 CXA7000R Application Circuit 1 (to SVGA Panel) VDD 20kΩ DSD CXD3526GG Buffer 1 VDD 1µF 20kΩ PRG 45 RGT 2 VDD 0.1µF 20kΩ 10Ω 20kΩ 0.1µF VDD 10Ω 0.1µF VCC 1Ω 47µF ROUT3 81 ROUT2 35 ROUT1 78 ROUT0 113 CLKOUT 28 D_IN4 10Ω D_IN3 10Ω D_IN2 10Ω D_IN1 10Ω D_IN0 10Ω MCLK MCLKX VCOM_OUT 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10Ω VDD 10Ω 1Ω NC 7 Vsig1 5 Vsig2 3 Vsig3 1Ω SH_OUT2 NC 1Ω SH_OUT3 GND PGND LCD Panel LCX026 PGND GND 1Ω SH_OUT4 NC NC Vsig4 4 Vsig5 6 Vsig6 1Ω SH_OUT6 PVCC 0.1µF 2 1Ω SH_OUT5 47µF 1µF OPEN FRP 118 SHST 119 VCOM_OFST VCC15 SID_OUT PRG_LV SID_LV GND PRG GND PS VDD5 VREF_I VREF_O 25 CXA7000R 57 FRP 0.1µF 56 PVCC SH_OUT1 DCFBOFF ROUT4 80 26 GND GND 10Ω 27 55 CAL_H GND 54 CAL_L D_IN5 28 SIG.C D_IN6 10Ω 29 53 SIG_OFST 10Ω 52 NC D_IN7 30 GND 10Ω 51 GND D_IN8 SHTEST 10Ω POSCNT3 ROUT5 79 D_IN9 31 POSCNT2 ROUT6 36 10Ω 32 50 POSCNT1 ROUT7 40 PVCC 49 POSCNT0 STATUS ROUT8 39 47µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TEST SHST 10kΩ F/H_CNT VDD 24 COM VDD DIRC SL_DAT VDD ROUT9 38 Psig VDD 1µF 0.1µF 20kΩ VDD PVCC VCC VDD 0.1µF 20kΩ 15.5V 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 19 – CXA7000R Application Circuit 2 (to XGA Panel) VDD 20kΩ DSD CXD3526GG Buffer 1 VDD 1µF 20kΩ PRG 45 RGT 2 VDD 0.1µF 20kΩ 10Ω 20kΩ 0.1µF VDD 10Ω 0.1µF VCC 1Ω 47µF ROUT3 81 ROUT2 35 ROUT1 78 ROUT0 113 CLKOUT 28 10Ω D_IN3 10Ω D_IN2 10Ω D_IN1 10Ω D_IN0 10Ω MCLK MCLKX VCOM_OUT VCOM_OFST VCC15 SID_OUT PRG_LV SID_LV PRG GND GND PS VDD5 VREF_I 56 25 CXA7000R 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 0.1µF 1 FRP FRP 118 SHST 119 VREF_O 26 10Ω 2 10Ω 3 4 5 6 7 8 PVCC NC 3 Vsig1 5 Vsig3 7 Vsig5 9 Vsig7 1Ω SH_OUT2 NC 1Ω SH_OUT3 GND PGND PGND GND 1Ω SH_OUT4 NC 1Ω SH_OUT5 11 Vsig9 NC 1Ω SH_OUT6 13 Vsig11 PVCC 0.1µF 9 10 11 12 13 14 15 16 1Ω SH_OUT1 47µF DCFBOFF ROUT4 80 D_IN4 55 GND GND 10Ω 27 CAL_H GND 28 54 CAL_L D_IN5 29 53 SIG_OFST 10Ω 52 SIG.C D_IN6 NC D_IN7 10Ω 30 GND 10Ω 51 GND D_IN8 SHTEST 10Ω POSCNT3 ROUT5 79 D_IN9 31 POSCNT2 ROUT6 36 10Ω 32 50 POSCNT1 ROUT7 40 PVCC 49 POSCNT0 ROUT8 39 47µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TEST STATUS SHST 10kΩ F/H_CNT VDD 31 COM VDD DIRC SL_DAT VDD ROUT9 38 Psig VDD LCD Panel LCX029 OPEN 0.47µF VDD 0.47µF VDD 1µF 0.1µF SID_OUT PRG_LV SID_LV PRG GND GND PS VDD5 VREF_I VREF_O F/H_CNT PVCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 23 59 22 60 21 61 20 62 19 63 18 64 17 1 FRP 0.1µF 24 58 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PVCC 1Ω SH_OUT1 NC 4 Vsig2 6 Vsig4 8 Vsig6 1Ω SH_OUT2 NC 1Ω SH_OUT3 GND PGND PGND GND 1Ω SH_OUT4 10 Vsig8 NC 1Ω SH_OUT5 12 Vsig10 NC 1Ω SH_OUT6 14 Vsig12 PVCC 47µF 0.1µF DCFBOFF MCLKX 25 CXA7000R 57 GND MCLK 56 CAL_H D_IN0 26 CAL_L D_IN1 27 55 SIG_OFST D_IN2 54 SIG.C D_IN3 28 NC GND D_IN4 53 GND GND 29 GND D_IN5 30 52 SHTEST D_IN6 51 POSCNT3 D_IN7 31 POSCNT2 D_IN8 32 50 POSCNT1 D_IN9 49 POSCNT0 TEST STATUS SHST 10kΩ DIRC SL_DAT VDD VDD VDD VCOM_OUT VDD VDD VCOM_OFST VCC 47µF VCC15 20kΩ VDD OPEN 20kΩ 0.1µF 0.47µF VDD 0.47µF 20kΩ PVCC 15.5V 0.1µF VCC VDD 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 20 – CXA7000R VDD Application Circuit 3 (to SXGA Panel) 20kΩ DSD CXD3511Q VDD Buffer 1µF 20kΩ PRG 161 RGT 136 10Ω 0.1µF 1Ω R1OUT0 111 CLKOUT 47 10Ω D_IN2 10Ω D_IN1 10Ω D_IN0 10Ω MCLK MCLKX VCOM_OUT VCOM_OFST VCC15 SID_OUT PRG_LV SID_LV PRG GND GND VDD5 VREF_I PS VREF_O CXA7000R 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 0.1µF 1 FRP FRP 157 SHST 159 F/H_CNT 25 10Ω 2 10Ω 3 4 5 6 7 8 PVCC NC 3 Vsig1 5 Vsig3 7 Vsig5 9 Vsig7 1Ω SH_OUT2 NC 1Ω SH_OUT3 GND PGND PGND GND 1Ω SH_OUT4 NC 1Ω SH_OUT5 11 Vsig9 NC 1Ω SH_OUT6 13 Vsig11 PVCC 0.1µF 9 10 11 12 13 14 15 16 1Ω SH_OUT1 47µF DCFBOFF R1OUT1 112 D_IN3 26 56 GND R1OUT2 113 10Ω 55 CAL_H R1OUT3 116 D_IN4 27 CAL_L GND 10Ω 28 54 SIG_OFST D_IN5 29 53 SIG.C 10Ω 52 NC D_IN6 GND D_IN7 10Ω 30 GND 10Ω 51 SHTEST D_IN8 POSCNT3 10Ω 31 POSCNT2 D_IN9 32 50 POSCNT1 10Ω GND R1OUT4 117 PVCC 49 POSCNT0 R1OUT5 118 32 COM 47µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TEST STATUS SHST 10kΩ R1OUT6 119 COMR 21 COML VCC VDD DIRC SL_DAT VDD R1OUT7 120 2 20kΩ 0.1µF VDD 10Ω 47µF R1OUT8 121 Psig VDD 0.1µF 20kΩ VDD R1OUT9 122 1 VDD LCD Panel LCX028 OPEN 0.47µF VDD 0.47µF VDD 1µF 0.1µF R2OUT2 103 R2OUT1 99 R2OUT0 98 10Ω D_IN3 10Ω D_IN2 10Ω D_IN1 10Ω D_IN0 MCLK MCLKX VCOM_OUT SID_OUT SID_LV PRG GND GND PS VDD5 VREF_I VREF_O PRG_LV 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 FRP 0.1µF 25 CXA7000R 57 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PVCC 1Ω SH_OUT1 NC 4 Vsig2 6 Vsig4 8 Vsig6 1Ω SH_OUT2 NC 1Ω SH_OUT3 GND PGND PGND GND 1Ω SH_OUT4 10 Vsig8 NC 1Ω SH_OUT5 12 Vsig10 NC 1Ω SH_OUT6 14 Vsig12 PVCC 47µF 0.1µF DCFBOFF R2OUT3 104 56 GND R2OUT4 105 D_IN4 26 CAL_H GND 10Ω 55 CAL_L GND 27 SIG_OFST D_IN5 28 54 SIG.C 10Ω 53 NC D_IN6 GND D_IN7 10Ω 29 GND 10Ω 30 52 SHTEST R2OUT5 106 D_IN8 51 POSCNT3 R2OUT6 107 10Ω 31 POSCNT2 R2OUT7 108 D_IN9 32 50 POSCNT1 R2OUT8 109 10Ω 49 POSCNT0 STATUS R2OUT9 110 PVCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TEST SHST 10kΩ F/H_CNT VDD VDD VDD VDD DIRC SL_DAT VDD VCOM_OFST VCC 47µF VCC15 20kΩ VDD OPEN 20kΩ 0.1µF 0.47µF VDD 0.47µF 20kΩ PVCC 15.5V 0.1µF VCC VDD 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 21 – CXA7000R Notes on Operation The CXA7000R has high power consumption, so be sure to take the following radiation measures. • Use four-layer substrate. • GND lines connected to Pins 8, 9, 24, 25, 40, 41, 56 and 57 should be as thick as possible. – 22 – CXA7000R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 16 1 0.5 b 0.13 M + 0.2 1.5 – 0.1 0.1 0.1 ± 0.1 0.5 ± 0.2 0˚ to 10˚ 0.125 ± 0.04 b = 0.18 ± 0.03 DETAIL B: PALLADIUM DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT PALLADIUM PLATING EIAJ CODE P-LQFP64-10x10-0.5 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 23 – Sony Corporation