CXB1455R VGA/SVGA/XGA 24-bit Transmitter Description The CXB1455R is the IC which transmits the 24-bit VGA/SVGA/XGA definition moving picture based on the GVIF (Gigabit Video Interface) technology. 48 pin LQFP (Plastic) Features • 1 chip transmitter for serial transmission of 24-bit color VGA/SVGA/XGA picture • On-chip PLL synthesizer • On-chip differential cable driver • TTL/CMOS compatible interface • Supports 1 pixel/shift clock mode with 1 chip and 2 pixel/shift clock mode with 2 chips • Single 3.3V power supply • Low power consumption • 48-pin plastic QFP package (7mm × 7mm) Structure Bi-CMOS IC 4.2 0 to +85 –65 to +150 333 V °C °C mW V GND CE LPFA LPFB CKPOL SDATAP SDATAN GNDT REXT VCCA Recommended Operating Condition Supply voltage 3.3 ± 0.3 GNDA Block Diagram and Pin Configuration VDD Application Gigabit video interface Absolute Maximum Ratings • Power supply VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD 36 35 34 33 32 31 30 29 28 27 26 25 GND 37 24 VDD REFREQ 38 23 R0 22 R1 CNTL 39 Cable Driver PLL DE 40 21 R2 SFTCLK 41 20 R3 HSYNC 42 19 R4 18 R5 B7 44 17 R6 B6 45 16 R7 P/S Converter VSYNC 43 B5 46 15 G0 B4 47 14 G1 VDD 48 13 GND B1 B0 8 9 10 11 12 VDD B2 7 G2 B3 6 G3 5 G4 4 G5 3 G6 2 G7 1 GND Encoder Fig. 1. Block Diagram and Pin Configuration Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98Y03B03 CXB1455R Pin Description Power Supply/Ground Symbol Pin No. Description VDD 12, 24, 36, 48 Logic power supply; connected to 3.3V ± 0.3V GND 1, 13, 25, 37 Logic ground; connected to 0V VCCA 34 Analog power supply; connected to 3.3V ± 0.3V GNDA 35 Analog ground; connected to 0V GNDT 32 Transmission ground; connected to 0V Digital Signal Symbol Pin No. Type Equivalent Circuit Description Shift clock, for the data TTL in 1 fetch at rising or falling edge SFTCLK 41 RED (7 to 0) 16, 17, 18, 19, 20, 21, 22, 23 GRN (7 to 0) 6, 7, 8, 9, 10, 11, 14, 15 BLU (7 to 0) 44, 45, 46, 47, 2, 3, 4, 5 HSYNC 42 TTL in 1 Hsync data VSYNC 43 TTL in 1 Vsync data CNTL 39 TTL in 1 Panel control data DE 40 TTL in 1 Data enable VDD TTL in 1 Pixel data. 1 pixel/shift clock input. TTL-IN GND VDD CE 26 TTL in 2 Chip enable TTL-IN CKPOL 29 TTL in 2 SFTCLK polarity GND VCCA SDATAP SDATAP/N 30, 31 Tx Serial output and Refclk request input SDATAN VDD GNDT GNDA –2– GND CXB1455R Symbol Pin No. Type Description Equivalent Circuit VDD REFREQ 38 TTL out Refclk request detection flag TTL-OUT GND Special Symbol Pin No. Description Equivalent Circuit VCCA REXT 33 SDATAP/N output current trimming. Connect to the external resistor. REXT VDD GNDA GND VCCA LPFA LPFB LPFA/B 27, 28 External loop filter VDD GNDA GND –3– CXB1455R Electrical Characteristics Table 1. Absolute Maximum Ratings Item Symbol Min. Supply voltage VCC TTL DC input voltage Typ. Max. Unit –0.3 4.2 V VI_T –0.5 6.5 V TTL H level output current IOH_T –20 0 TTL L level output current IOL_T 0 20 mA ' mA Serial output pin voltage Vsdout VCC–1.2 VCC + 0.5 V Ambient temperature Ta –55 120 °C Storage temperature Tstg –65 150 °C Remarks Under bias Table 2. Recommended Operating Conditions Item Symbol Supply voltage (Includes VDD and VccA) VCC Ambient temperature Min. Typ. Max. Unit 3.0 3.3 3.6 V 85 °C Ta 0 Conditions Table 3. DC Characteristics (Under the recommended operating conditions. See Table 2.) Item Symbol Min. Typ. Max. Unit Conditions TTL High level input voltage VIH_T 2 5.5 V TTL Low level input voltage VIL_T 0 0.8 V TTL High level input current IIH_T 1.0 µA VIN = VCC TTL Low level input current IIL_T µA VIN = 0 CE, CKPOL High level input voltage VIH_C VCC – 0.5 5.5 V CE, CKPOL Low level input voltage VIL_C 0 0.5 V CE, CKPOL High level input current IIH_C 1.0 µA VIN = VCC CE, CKPOL Low level input current IIL_C –1.0 µA VIN = 0 TTL High level output voltage VOH_T 2.4 V IOH = –8mA TTL Low level output voltage VOL_T 0.4 V IOL = 8mA SDATA High level output current IOH_SD –0.1 0 +0.5 mA SDATA Low level output current IOL_SD 14.5 15.7 17 mA SDATA High level output voltage VIH_SD VCC – 0.55 SDATA Low level output voltage Supply current V VIL_SD GRAYSCALE WORSTCASE –1.0 ICC VCC – 0.76 V mA 44.0 61.0 77.0 50.0 71.0 92.0 –4– mA REXT = 4.7kΩ Common mode voltage @65MHz See Fig. 8 See Fig. 7 CXB1455R Table 4. AC Characteristics (Under the recommended operating conditions. See Table 2.) Symbol Min. TTL input rise time Tir TTL input fall time Tif Minimum SFTCLK frequency Maximum SFTCLK frequency Fsftclk SFTCLK duty factor Dsftclk 40 Pixel/Sync/Cntl setup time to SFTCLK Tsetup 2.5 ns Pixel/Sync/Cntl hold time to SFTCLK Thold 2.5 ns SDATA rise time Tor 200 ps SDATA fall time Tof 200 ps Clock mode assert time TAclk 50 ns Clock mode deassert time TDclk 10 ns Idle mode assert time TAidle 150 ns Idle mode deassert time TDidle 100 ns PLL lock-in time Tlockin 0.1 ms Item Typ. Max. Unit 0.7 5.0 ns 0.8 to 2.0V 0.7 5.0 ns 2.0 to 0.8V 25.0 MHz MHz 60 % 65.0 VCC/A TTL clock 51 Conditions Vth = 1.4V 20 to 80%, CL = 2pF See Fig. 2. 51 41 VCC CXB1455R RGB, CE VS, HS, DE, CNTL, CKPOL FET probe 30 100 31 Sampling oscilloscope GND/A/T Fig. 2. SDATA waveform measurement –5– CXB1455R Timing Chart 1/Fsftclk Dsftclk/Fsftclk VIH_T 2.0V SFTCLK Vth 0.8V VIL_T Tir Tif Setup/hold times are referred from falling edge in CKPOL = GND rising edge in CKPOL = Vcc Tsetup Thold Tir REDxx GRNxx BLUxx H/Vsync CNTLx VIH_T 2.0V 0.8V VIL_T Tif Min. 2 (SFTCLK cycle) VSYNC Min. 2 Min. 2 Min. 2 HSYNC Min. 2 Min. 2 DE RGB CNTL There must be 2 SFTCLK cycles or more left between the CNTL edge and the HSYNC, VSYNC and DE edges. Fig. 3. TTL input timing Tor 80% SDATAP SDATAN 100% 20% 0% Tof Fig. 4. Serial output timing –6– CXB1455R Reference clock NRZ data SDATAP SDATAN REFRQ signal from CXB1454R or CXB1456R REFREQ TDclk TAclk Fig. 5. Refclk request timing CE SDATAP SDATAN NRZ data TDidle TAidle Fig. 6. Idle mode timing SFTCLK f RGB <7, 5, 3, 1> f/2 RGB <6, 4, 2, 0> f/2 Fig. 7. Worst case test pattern f SFTCLK RGB <7> f/16 RGB <6> f/8 RGB <5> f/4 RGB <4> f/2 RGB <3> Fix Low RGB <2> Fix Low RGB <1> Fix Low RGB <0> Fix Low Fig. 8. 16 grayscale test pattern –7– CXB1455R CE Pin Control The CE pin should be controlled as follows. When the power is turned ON or SFTCLK stops, or when the SFTCLK input signal falls into the disorder while the SFTCLK frequency is varied, the CE pin should be set to Low level and the CE pin should be set to High level after the SFTCLK frequency stabilizes. (Figs. 9 and 10) When the power supply and SFTCLK stabilize VCC SFTCLK 200µs or more CE Fig. 9. CE timing when power supply is turned ON When SFTCLK does not stabilize When SFTCLK stabilizes SFTCLK ∗ 200µs or more CE ∗ When SFTCLK stops or the frequencies of 15MHz or less and 75MHz or more are input. Fig. 10. CE timing when SFTCLK input signal is not stabilized –8– CXB1455R CKPOL Pin Control The CKPOL pin selects the SFTCLK data sampling trigger edge. (See Table 5) Table 5. SFTCLK polarity CKPOL SFTCLK data sampling trigger L Falling edge H Rising edge Applications The CXB1455R GVIF transmitter is applied to the digital RGB signal transmission for P/C with LCD monitor Video-on-demand system Monitoring system Graphical controller Projector Digital TV monitor Automobile Navigation System with GVIF receivers, CXB1454R/CXB1456R. CXB1455R GVIF Transmitter 4 Parallel to Serial Converter SHIFTCLOCK Cable Driver PLL STP or Twin axial Serial to Parallel Converter Cable Equalizer Decoder SYNC/DE/CNTL 8 8 8 Encoder RED (7 to 0) GRN (7 to 0) BLU (7 to 0) PLL CXB1454R/CXB1456R GVIF Receiver –9– 8 8 8 4 RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/DE/CNTL SHIFTCLOCK CXB1455R Application Circuit (1) Chip resistor (1%) (2) Chip capacitor (3) Formed by the printed circuit pattern (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm) (4) LPF chip capacitor (Temperature compensation type) Differential cable VCC 330 SW2 High: Rising edge trigger Low: Falling edge trigger Connector VCC 0.1 to 0.4n (3) 1k (1) VCC 33µ 16V 0.1 to 0.4n (3) 0.1µ (2) 51 (1) 680p (4) 4.7k (1) 0.01µ (4) 330 36 35 34 33 32 31 30 29 28 27 26 25 GNDA VCCA REXT GNDT SDATAN SDATAP CKPOL LPFB LPFA CE GND 37 GND SW1 1k (1) VCC VCC 0.1µ (2) 51 (1) High: Transmission data Low: Standby 0.1µ (2) VCC 24 38 REFREQ R0 23 39 CNTL R1 22 40 DE R2 21 41 SFTCLK R3 20 42 HSYNC VCC R4 19 CXB1455R R5 18 44 B7 R6 17 45 B6 R7 16 46 B5 G0 15 47 B4 G1 14 B2 B1 B0 G7 G6 G5 G4 G3 G2 VCC GND 13 B3 48 VCC GND VCC 43 VSYNC 1 2 3 4 5 6 7 8 9 10 11 12 0.1µ (2) 0.1µ (2) CNTL SFTCLK HSYNC VSYNC DE VCC 7 6 5 4 3 2 1 0 MSB LSB BLUE DATA 7 6 5 4 3 2 1 0 MSB LSB GREEN DATA 7 6 5 4 3 2 1 0 MSB LSB RED DATA Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXB1455R , ,, , Recommended Printed Board Structure L1: I1: L2: I2: L3: I3: L4: Cu plate (18µm) + solder coat Fiber-glass epoxy core (0.3mm) Cu plate (36µm) Fiber-glass epoxy core (0.8mm) Cu plate (36µm) Fiber-glass epoxy core (0.3mm) Cu plate (18µm) + solder coat Recommended Printed Circuit Board Pattern Example of power supply and special signal routing 0.5mm L2 doesn't have the plane in this area. E E ,,,, ,,, ,, , ,, ,,,, A : Through hole to the GNDA plane (L2) : Through hole to the GND plane (L2) E : Through hole to the VccA plane (L3) T : Through hole to the Vcc plane (L3) R : Through hole to the REXT resistor (L4) P : Through hole to the CKPOL signal (L4) C : Through hole to the CE signal (L4) ,, E A G Chip capacitor Chip resistor 37 GND CE LPFA LPFB CKPOL SDATAP SDATAN GNDT VCCA REXT G 37 GNDA VCC G GND R G P RED <0> C CNTL RED <1> DE RED <2> SFTCLK RED <3> HSYNC RED <4> VSYNC RED <5> BLU <7> RED <6> RED <7> BLU <6> T T T BLU <5> GRN <0> BLU <4> GRN <1> VCC VCC GRN <2> GRN <3> GRN <4> GRN <5> GRN <6> BLU <0> GRN <7> BLU <1> BLU <2> GND GND 48 BLU <3> 48 24 VCC REFREQ 13 Locate the bypass capacitor (0.1µF chip capacitor) as close to the pins as possible. G G 1 12 Microstrip Line The microstrip line with the characteristic impedance of 50Ω should be used to connect the LSI transmission signal pin SDATAP/N to the connector foot printer as GVIF transmits the high-speed digital signal with the maximum speed of 2Gb/s. The optimal line can be made by forming 0.5mm pattern on L1. (See the board structure shown below.) The line lengths should be the same and the through hole should be not used. Normally, L2 should be the mat GND. Termination Elements Locate the 51Ω termination resistors as close to the LSI as possible. Filter Device and Reference Resistor The capacitor and resistor connected to LPFA/B and REXT are the filter and the reference resistor. Locate them as close to the LSI as possible. Decrease the parasitic capacitance by removing the L2 GND plane under these elements and wiring. – 11 – CXB1455R By-pass Capacitor Locate a 0.1 µF chip capacitor as close to the pin as possible as shown in the Recommended Circuit Diagram. Notes on Transmission System Configuration The GVIF uses termination on both the transmitting and receiving ends, built-in equalizers, small amplitude differential signals, etc. in order to more easily resolve problems such as signal reflectance, signal attenuation and EMI which interfere with high-speed data transmission. However, a number of cautions must be observed over the entire transmission system shown in the figure below in order to completely resolve these problems. Tx termination 50Ω Tx termination 100Ω Tx LSI Rx LSI Microstrip line (50Ω) Foot print Connector Cable (diff. 100Ω) Connector Foot print Microstrip line (50Ω) The transmission system has the following four requirements. • Impedance matching shall be excellent. (Reflectance shall be low.) A differential impedance that falls within the template shown on the following page is recommended. • Attenuation shall be low and regular. For the CXB1454R (built-in equalizer) Attenuation of 15 dB (conforming to root f attenuation) @ 1 GHz or less is recommended. See the following page. For the CXB1456R (no equalizer) Attenuation of 6 dB @ 1 GHz or less is recommended. • Differential signal POS/NEG skew shall be small. 12% or less during the time for one bit is recommended. 160 ps @ VGA, 100 ps @ SVGA, 60 ps @ XGA • EMI characteristics shall be excellent. The following measures are effective for satisfying these requirements. • Use a low attenuation, low skew differential cable with excellent impedance accuracy. A cable with a two-core coaxial (shielded twisted pair) structure is recommended. • Use low reflectance connectors. • Take care for the connector pin assignment. Select pins so that there is no interference with other signals and so that the positive and negative signal wiring are the same length on the board. • Use a cable with a double shielded structure. – 12 – CXB1455R Recommended Transmission Path : Differential impedance template Zo (Ω) 150 110 106 94 90 75 < 500ps Microstrip line Foot print Connector < 500ps Cable Connector Foot print Microstrip line Recommended Transmission Path : Attennation Characteristics Loss < 15dB 2dB Measured curve Fitting curve Frequency 1GHz – 13 – CXB1455R 1.95Gbps SDATAP output waveform 100mV/div 100ps/div SFCLK jitter tolerance: Example of power spectrum which can be used for transmission ATTEN 10dB RL 0dBm 10dB/ REF LVL 0dBm D CENTER 65.00MHz RBW 100kHz VBW 100kHz – 14 – SPAN 10.00MHz SWP 50ms CXB1455R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 S 25 13 0.5 ± 0.2 B A 48 (8.0) 24 37 (0.22) 12 1 + 0.05 0.127 – 0.02 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 0.13 M 0.1 S 0.5 ± 0.2 (0.18) 0° to 10° DETAIL B:SOLDER DETAIL A 0.18 ± 0.03 0.127 ± 0.04 + 0.08 0.18 – 0.03 (0.127) +0.05 0.127 – 0.02 0.1 ± 0.1 DETAIL B:PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-48P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 15 – Sony Corporation