CXB1451Q VGA/SVGA/XGA digital data serial transmitter VEET RED0 (4) RED0 (5) RED0 (3) RED0 (2) RED0 (1) VCCT RED0 (0) IDLE 80 pin QFP (Plastic) REFREQ VEEE SDATAP VCCE SDATAN VCCA VEEA VEES LPFB LPFA Block Digagram & Pin out TESTSB Features • 1 chip transmitter for serial transmission of 18bit color VGA/SVGA/XGA picture • On chip differential cable driver • TTL/CMOS compatible interface • Support 1 pixel/shiftclock mode & 2 pixel/shiftclock mode • +3.3V single power supply • Low power consumption • 80pin Plastic QFP Package (Body size: 14mm × 14mm) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TESTDT 61 40 VCCT PANEL1 62 39 GRN0 (0) PANEL0 63 38 GRN0 (1) Cable Driver CKMODE 64 37 GRN0 (2) CNTL3 65 36 GRN0 (3) CNTL2 66 35 GRN0 (4) CNTL1 67 34 GRN0 (5) PLL VEEG 68 33 VEEG Parallel to Serial Converter VCCG 69 VCCT 70 VEET 71 32 VCCG 31 VEET 30 VCCT SFTCLK 72 29 BLU0 (0) HSYNC 73 28 BLU0 (1) VSYNC 74 27 VEEG 75 BLU0 (2) 26 VEEG Encoder VCCG 76 25 VCCG CNTL0 77 24 BLU0 (3) BLU1 (5) 78 23 BLU0 (4) BLU1 (4) 79 22 BLU0 (5) VCCT 80 BLU1 (1) BLU1 (0) GRN1 (5) GRN1 (4) GRN1 (3) GRN1 (2) VCCT BLU1 (2) RED1 (0) VEET RED1 (2) 9 10 11 12 13 14 15 16 17 18 19 20 RED1 (1) 8 RED1 (3) 7 RED1 (4) 6 RED1 (5) 5 GRN1 (0) 4 GRN1 (1) 3 VEET 2 VCCT 1 BLU1 (3) 21 VEET Fig. 1. Block Diagram & Pin out Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97913-PS CXB1451Q Pin List Power/Ground Pin Name Pin Number Descriptions VCCT 10, 20, 30, 40, 48, 70, 80 TTL power surpply , should be connected to 3.3V ± 5% VEET 1, 11, 21, 31, 41, 71 TTL ground, connected to 0V VCCG 25, 32, 69, 76 Logical core power surpply, connected to 3.3V ± 5% VEEG 26, 33, 68, 75 Logical core ground, connected to 0V VCCE 54 Serial driver power surpply, connected to 3.3V ± 5% VEEE 51 Serial driver ground, connected to 0V VCCA 56 Analog power surpply, connected to 3.3V ± 5% VEEA 57 Analog ground, connected to 0V VEES 58 Analog substrate, connected to 0V Digital Signals Pin Name Pin Number Type Descriptions SFTCLK 72 TTL in Shift clock, for the data fetch at rising or falling edge RED1 (5 to 0) GRN1 (5 to 0) BLU1 (5 to 0) 14, 15, 16, 17, 18, 19 6, 7, 8, 9, 12, 13 78, 79, 2, 3, 4, 5 TTL in Pixel data input in 1 pixcel/sftclk mode 2nd pixel data input in 2 pixel/sftclk mode RED0 (5 to 0) GRN0 (5 to 0) BLU0 (5 to 0) 42, 43, 44, 45, 46, 47 34, 35, 36, 37, 38, 39 22, 23, 24, 27, 28, 29 TTL in Ignored in 1 pixcel/sftclk mode 1st pixel data input in 2 pixel/sftclk mode HSYNC 73 TTL in Hsync data VSYNC 74 TTL in Vsync data CNTL (3 to 0) 65, 66, 67, 77 TTL in Control data PANEL (1, 0) 62, 63 TTL in Panel mode select switch CKMODE 64 TTL in Clock mode select switch IDLE 49 TTL in Idle mode select switch SDATAP/N 52, 53 Tx Serial Output & Refclk request input REFREQ 50 TTL out Refclk request detect flag Special Pin Name Pin Number Descriptions TESTSB/DT 55, 61 SFTCLK polarity / TEST function control LPFA/B External loop filter 59, 60 –2– CXB1451Q Equivalent I/O circuit VCCT VCCT VCCG 6k 6k 3k TTL-OUT TTL-IN 300 VEET VEET VEEG (a) TTL input equivalent circuit (b) TTL output equivalent circuit VCCA VCCE LPFA LPFB SDATAP SDATAN VEEA VEEE (c) LPFA/B equivalent circuit VCCA (d) SDATAP/N equivalent circuit VCCG VCCG VCCT TESTSB TESTDT VEEA VEEG (e) TESTDT equivalent circuit VEEG VEET (f) TESTSB equivalent circuit –3– CXB1451Q Electrical characteristics Tab. 1. Absolute Maximum Rating Description Symbol Min. Typ. Max. Unit Power supply voltage VCC –0.3 4 V TTL DC input voltage VI_T –0.5 5.5 V TTL output current (High) IOH_T –20 0 TTL output current (Low) IOL_T 0 20 mA ' mA Serial output pin voltage Vsdout –0.5 VCC + 0.5 V Ambient temperature Ta –55 70 °C Storage temperature Tstg –65 150 °C Comments Under bias Tab. 2. Recommended Operating Conditions Description Symbol Min. Typ. Max. Unit 3.3 3.465 V 70 °C Power supply voltage (Include VCCT5) VCC 3.135 Ambient temperature Ta 0 Comments Tab. 3. DC Characteristics (Under the recommended conditons. See Tab. 2) Description Symbol Min. Typ. Max. Unit Conditions Input HIGH voltage (TTL) VIH_T 2 5.5 V Input LOW voltage (TTL) VIL_T –0.5 0.8 V Input HIGH current (TTL) IIH_T 20 µA VIN = VCC Input LOW current (TTL) IIL_T –400 µA VIN = 0 Output HIGH voltage (TTL) VOH_T 2.3 V IOH = –0.2mA Output LOW voltage (TTL) VOL_T 0.4 V IOL = 4mA Output HIGH current (SDATA) IOH_SD –0.1 0 +0.1 mA Output LOW current (SDATA) IOL_SD 14.7 16 17.3 mA Input HIGH voltage (SDATA) VIH_SD VCC – 0.6 Input LOW voltage (SDATA) VIL_SD Supply current ICC 165 175 V 215 225 –4– VCC – 0.7 V 265 275 mA mA See Fig. 2 Common mode voltage XGA, Outputs open SVGA/VGA, Outputs open CXB1451Q VCCA/G/E/T A 61 A 52 CXB1451Q VCC 55 53 VEEA/G/E/T Fig. 2. IOH_SD and IOL_SD DC measurement Tab. 4. AC Characteristics (Under the recommended conditons. See Tab. 5) Symbol Description Min. Typ. Max. Unit Conditions Input TTL rise time Tir 0.7 4.8 ns 0.8V to 2.0V Input TTL fall time Tir 0.7 4.8 ns 2.0V to 0.8V SFTCLK frequency Fsftclk 20.0 10.0 38.0 19.0 60.0 30.0 28.0 14.0 48.0 24.0 68.0 34.0 MHz MHz MHz MHz MHz MHz SFTCLK duty factor Dsftclk 40 60 % Vth = 1.4V Pixel/Sync/Cntl setup to SFTCLK Tsetup 4.0 ns Pixel/Sync/Cntl hold to SFTCLK Thold 1.0 ns XGA 1 pixel/sftclk mode @65MHz See Fig. 4 SDATA rise time Tor 400 ps SDATA fall time Tof 400 ps CLOCK mode assert time TAclk 130 ns CLOCK mode deassert time TDclk 10 ns IDLE mode assert time TAidle 150 ns IDLE mode deassert time TDidle 350 ns PLL lockin time Tlockin 0.1 ms 25.0 12.5 40.0 20.0 65.0 32.5 VCCA/G/E/T 72 20 to 80%, CL = 2pF See Fig. 3 51 FET probe 52 TTL clock VCC 51 VGA, 1 pixel/sftclk mode VGA, 2 pixel/sftclk mode SVGA, 1 pixel/sftclk mode SVGA, 2 pixel/sftclk mode XGA, 1 pixel/sftclk mode XGA, 2 pixel/sftclk mode 100 CXB1451Q 53 Sampling oscilloscope VEEA/G/E/T Fig. 3. SDATA waveform measurement –5– CXB1451Q Timing Chart 1/Fsftclk Dsftclk/Fsftclk VIH_T 2.0V Vth SFTCLK 0.8V VIL_T Tir Tif Setup/hold time is refered from fall edge in TESTSB/DT = GND or OPEN rise edge in TESTSB/DT=V CC Tsetup Thold Tir VIH_T REDxx GRNxx BLUxx H/Vsync CNTLx 2.0V 0.8V VIL_T Tif Fig. 4. TTL input timing Tor 100% 80% SDATAP SDATAN 20% 0% Tof Fig. 5. Serial output timing Reference clock NRZ data SDATAP SDATAN REFRQ signal from CXB1452Q REFREQ TDclk TAclk Fig. 6. Refclk request timing IDLE NRZ data SDATAP SDATAN TDidle Fig. 7. Idle mode timing –6– TAidle CXB1451Q Operation mode CXB1451Q supports 3 panel mode and 2 clock mode switched by the PANEL (1, 0) and CKMODE pin according to the Tab. 5 & 6. The supporting clock rate are summarized in Tab. 7. These pins are open High TTL inputs. Tab. 5. Panel Mode select PANEL1 PANEL0 Supporting panel size & color L L VGA (640 × 480) 18bit color L H SVGA (800 × 600) 18bit color H L XGA (1024 × 768) 18bit color H H not supported Tab. 6. Clock Mode select CKMODE Supporting clock mode L 2 pixel/ShiftClock (2ppc) H 1 pixel/ShiftClock (1ppc) Tab. 7. Operation Mode Panel Mode VGA SVGA XGA Clock Mode Color Shift Clock Dot Clock Serial rate 1 pixel/SftClk 18bit 25MHz 25MHz 600Mbps 2 pixel/SftClk 18bit 12.5MHz 25MHz 600Mbps 1 pixel/SftClk 18bit 40MHz 40MHz 960Mbps 2 pixel/SftClk 18bit 20MHz 40MHz 960Mbps 1 pixel/SftClk 18bit 65MHz 65MHz 1560Mbps 2 pixel/SftClk 18bit 32.5MHz 65MHz 1560Mbps TESTSB/TESTDT pins select the trigger edge of SFTCLK and test mode according to Tab. 8. Tab. 8. SFTCLK polarity & TEST mode TESTSB TESTDT GND GND OPEN VCC OPEN Transmitter operation trigger = falling edge VCC Fabricator reserved TEST mode SDATAP = H SDATAP = L Trigger = rising edge SDATAN = L SDATAN = H IDLE pin disable differential signal transmission from SDATAP/N pins. It's open High TTL input. Transmission is disabled when IDLE = High. –7– CXB1451Q Applications CXB1451Q GVIF transmitter is applied to the digital RGB signal transmittion for P/C with LCD monitor Video on demand system Monitoring system Graphical controller Projector Digital TV monitor with GVIF receiver, CXB1452Q. CXB1451Q GVIF Transmitter 6 6 6 6 6 6 6 Parallel to Serial Converter Encoder RED1 (5 to 0) GRN1 (5 to 0) BLU1 (5 to 0) RED0 (5 to 0) GRN0 (5 to 0) BLU0 (5 to 0) SYNC/CNTL SHIFTCLOCK Cable Driver PLL Serial to Parallel Converter Cable Equalizer RED0/GRN0/BLU0 are active in 2pixel/shiftclock mode only PLL CXB1452Q GVIF Receiver –8– Decoder STP or Twin axial 6 6 6 6 6 6 6 RED1 (5 to 0) GRN1 (5 to 0) BLU1 (5 to 0) RED0 (5 to 0) GRN0 (5 to 0) BLU0 (5 to 0) SYNC/CNTL SHIFTCLOCK CXB1451Q Application Cicuit (A) Clock mode: 1 pixel/sftclk (1ppc) Picture sync: H/V sync & DE Color depth: 18bit Differential cable VCC 0.1 to 0.4n (3) Connector 0.1 to 0.4n (3) (1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm) T E E 0.1 to 0.4n (3) SW0 Select SFTCLK polarity according to Tab. 8 1k 33µ 16V 0.1 to 0.4n (3) 0.1µ 0.1µ (2) (2) 1.5k (1) E 51 (1) 51 (1) ON : transmit data OFF : Idle 330 SW1 E T 680p 0.01µ 1.5k (1) (2) (2) 0.1µ (2) 62 PANEL1 SW3 T 330 VEET RED0 (5) RED0 (4) RED0 (3) RED0 (1) RED0 (2) RED0 (0) IDLE VCCT VEEE REFREQ SDATAP VCCE SDATAN VCCA 61 TESTDT 330 TESTSB VEES VEEA Select panel resolution according to Tab. 5 SW2 LPFA LPFB 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VCCT 40 63 PANEL0 GRN0 (1) 38 64 CKMODE GRN0 (2) 37 65 CNTL3 GRN0 (3) 36 66 CNTL2 GRN0 (4) 35 67 CNTL1 GRN0 (5) 34 68 VEEG VEEG 33 E 69 VCCG VCCG 32 T 70 VCCT VEET 31 71 VEET VCCT 30 72 SFTCLK 73 HSYNC BLU0 (1) 28 74 VSYNC BLU0 (2) 27 75 VEEG VEEG 26 76 VCCG VCCG 25 9 10 11 12 13 14 15 16 17 18 19 20 T E VEET 21 VCCT RED1 (0) 8 RED1 (1) 7 RED1 (2) 6 RED1 (3) 5 RED1 (4) 4 GRN1 (0) 3 RED1 (5) 2 GRN1 (1) GRN1 (2) 0.1µ (2) VEET GRN1 (3) 1 80 VCCT T VCCT GRN1 (4) BLU0 (5) 22 GRN1 (5) 79 BLU1 (4) BLU1 (0) BLU0 (4) 23 BLU1 (1) BLU0 (3) 24 78 BLU1 (5) BLU1 (2) 77 CNTL0 BLU1 (3) E E BLU0 (0) 29 VEET 0.1µ (2) T GRN0 (0) 39 0.1µ (2) T DE VSYNC HSYNC SFTCLK T 5 MSB 4 3 2 1 BLUE DATA 0 LSB 5 MSB 4 3 2 1 GREEN DATA 0 LSB 5 MSB 4 3 2 1 0 LSB RED DATA Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– 0.1µ (2) CXB1451Q Application Cicuit (B) Clock mode: 2 pixel/sftclk Picture sync: ENABLE only Color depth: 12bit Differential cable VCC 0.1 to 0.4n (3) Connector 0.1 to 0.4n (3) E (1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm) T E 0.1 to 0.4n (3) SW0 Select SFTCLK polarity according to Tab. 8 1k 33µ 16V 0.1 to 0.4n (3) 51 (1) 330 SW1 0.1µ (2) 1.5k (1) 0.01µ 1.5k (1) (2) E 51 (1) 0.1µ (2) ON : transmit data OFF : Idle E T 680p (2) 0.1µ (2) SW3 330 VEET RED0 (4) RED0 (5) RED0 (3) RED0 (2) RED0 (1) RED0 (0) IDLE VCCT VEEE REFREQ SDATAP VCCE SDATAN VEEA VCCA 61 TESTDT TESTSB 330 VEES Select panel resolution according to Tab. 5 SW2 LPFA LPFB 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VCCT 40 62 PANEL1 GRN0 (0) 39 63 PANEL0 GRN0 (1) 38 64 CKMODE GRN0 (2) 37 65 CNTL3 GRN0 (3) 36 66 CNTL2 GRN0 (4) 35 67 CNTL1 GRN0 (5) 34 68 VEEG VEEG 33 E 69 VCCG VCCG 32 T 70 VCCT VEET 31 71 VEET VCCT 30 VEEG 26 76 VCCG VCCG 25 E T E 3 2 1 0 MSB LSB ODD GREEN DATA 0.1µ (2) VEET 21 VCCT RED1 (0) 9 10 11 12 13 14 15 16 17 18 19 20 RED1 (1) 8 RED1 (2) 7 RED1 (3) 6 RED1 (4) 5 RED1 (5) 4 GRN1 (0) 3 GRN1 (1) 2 VEET GRN1 (2) 1 80 VCCT VCCT GRN1 (3) BLU0 (5) 22 GRN1 (4) BLU0 (4) 23 79 BLU1 (4) GRN1 (5) BLU0 (3) 24 BLU1 (0) 77 CNTL0 78 BLU1 (5) BLU1 (1) 0.1µ (2) BLU0 (2) 27 75 VEEG BLU1 (2) T BLU0 (1) 28 74 VSYNC BLU1 (3) E BLU0 (0) 29 73 HSYNC VEET 0.1µ (2) 72 SFTCLK T 3 2 1 0 MSB LSB ODD RED DATA 0.1µ (2) T T 3 2 1 0 MSB LSB ODD BLUE DATA SFTCLK ENABLE ODD PIXEL 3 2 1 0 MSB LSB EVEN BLUE DATA 3 2 1 0 MSB LSB EVEN GREEN DATA 3 2 1 0 MSB LSB EVEN RED DATA EVEN PIXEL Transmission order of the PIXEL Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXB1451Q AAAAAAA AAAAAAA AAAAAAA AAAAAAA Recommended Printed Circuit Board Structure L1: Cu plate (18µm) + solder coat I1: Adhesive Sheet (0.3mm ± 0.09mm) L2: Cu plate (36µm) I2: Fiber-glass epoxy core (0.8mm) L3: Cu plate (36µm) I3: Adhesive Sheet (0.3mm) L4: Cu plate (18µm) + solder coat Recommended Printed Circuit Board Pattern SDATAP/SDATAN pins to the connector path other path W = 0.50mm (Z0 = 50Ω) W = 0.25mm POWER and special signal routing example 0.5mm G Through hole to the GND plane (L2) E Through hole to the VCCE/VCCG plane (L3) T Through hole to the VCCT plane (L3) Chip capacitor Chip resistor 41 G VEET RED0 (3) AA RED0 (4) RED0 (1) VCCT RED0 (0) REFREQ IDLE VCCE SDATAN VCCA TESTSB VEES VEEA LPFA LPFB 61 SDATAP AA 60 VEEE L2 doesn't have plane in this area E RED0 (2) AAA E RED0 (5) G TESTDT G GRN0 (0) PANEL0 GRN0 (1) CKMODE GRN0 (2) CNTL3 GRN0 (3) CNTL2 GRN0 (4) CNTL1 GRN0 (5) VEEG VEEG VCCG G E VCCG E VCCT VCCT SFTCLK BLU0 (0) HSYNC BLU0 (1) VSYNC BLU0 (2) VEEG G G VEEG VCCG VCCG E CNTL0 T T T T BLU0 (3) BLU1 (5) T T T T BLU0 (4) BLU1 (4) BLU0 (5) VCCT 21 1 VCCT RED1 (0) RED1 (2) RED1 (1) RED1 (4) RED1 (3) RED1 (5) GRN1 (0) VEET GRN1 (1) VCCT GRN1 (2) GRN1 (3) GRN1 (4) BLU1 (0) GRN1 (5) BLU1 (1) G BLU1 (2) VEET VEET BLU1 (3) 80 G VEET VEET E 40 VCCT E PANEL1 20 G – 11 – G CXB1451Q 1.56Gb/s SDATAP Output waveform 40.1820ns 40.6820ns Ch. 1 = 100.0mVolts/div Timebase = 100ps/div 41.1820ns Offset = –92.00mVolts Delay = 40.6820ns SFTCLK Jitter tolerance: example power spectrum available for transmission XGA 2ppc mode 32.5MHz REF LVL 0dBm D CENTER 32.50MHz RBW 100kHz VBW 100kHz – 12 – SPAN 10.00MHz SWP 50.0ms ATTEN 10dB RL 0dBm 10dB/ CXB1451Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 0.1 41 40 80 21 (15.0) 61 + 0.15 0.3 – 0.1 20 0.24 M 0° to 10° 0.5 ± 0.2 1 0.65 + 0.15 0.1 – 0.1 PACKAGE STRUCTURE SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL EPOXY RESIN QFP-80P-L03 LEAD TREATMENT SOLDER PLATING QFP080-P-1414 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.6g – 13 –