CXD2434ATQ Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2434ATQ is an IC developed to generate the timing pulses required by the Progressive Scan 48 pin TQFP (Plastic) CCD image sensors as well as signal processing circuits. The CXD2434ATQ adds EFS operation when using the high-speed electronic shutter and other changes to the CXD2434TQ specifications. Features • External trigger function • Electronic shutter function • Supports non-interlaced operation • 30 frames/s • Built-in driver for the horizontal (H) clock • Base oscillation 1560 fH (24.5454 MHz) Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX084AK, ICX084AL Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD VSS –0.5 to +7.0 • Input voltage VI VSS –0.5 to VDD +0.5 • Output voltage VO VSS –0.5 to VDD +0.5 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 V • Operating temperature Topr °C –20 to +75 V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E97841-TE CXD2434ATQ BUSY WEN ID PBLK XCPOB XCPDM VD HD STDBY WM SMDE FSE Block Diagram 36 35 34 33 32 31 47 46 42 29 26 25 3 PS RG 10 4 STRB 5 DCLK XSHP 21 7 DATA XSHD 22 8 SMD1 9 SMD2 H1 13 TG H2 14 REGISTER PULSE GENERATOR XRS 23 DECODE XV1 18 XV2 17 COUNTER XV3 16 GATE XSG 19 11 XSUB CLD 39 28 TEST1 CL 38 1/2 CKO 40 48 TEST2 EFS PBLK XCPOB SCPDM VDD WM TEST1 VSS SMDE FSE 36 35 34 33 32 31 30 29 28 27 26 25 30 37 VSS ESG ID 27 WEN 24 VDD TRIG 20 VSS OSCI 15 BUSY Pin Configuration (Top View) 12 6 VSS 45 VDD 44 VSS 43 VDD 2 VSS 1 OSCO 41 RESET VSS 37 24 VSS CL 38 23 XRS CLD 39 22 XSHD CKO 40 21 XSHP RESET 41 20 VDD STDBY 42 19 XSG CXD2434ATQ TRIG 43 18 XV1 ESG 44 17 XV2 EFS 45 16 XV3 HD 46 15 VSS VD 47 14 H2 9 10 11 12 VDD DCLK 8 XSUB STRB 7 RG PS 6 SMD2 5 SMD1 4 DATA 3 VSS 2 OSCI 13 H1 1 OSCO TEST2 48 —2— CXD2434ATQ Pin Description Pin No. Symbol I/O 1 2 OSCO OSCI O I 3 PS I 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 STRB DCLK VSS DATA SMD1 SMD2 RG XSUB VDD H1 H2 VSS XV3 XV2 XV1 XSG VDD XSHP XSHD XRS VSS I I — I I I O O — O O — O O O O — O O O — 25 FSE I 26 SMDE I 27 28 VSS TEST1 — I 29 WM I 30 31 32 33 34 35 36 37 38 39 VDD XCPDM XCPOB PBLK ID WEN BUSY VSS CL CLD — O O O O O O — O O Description Inverter output for oscillation. Inverter input for oscillation. Switching for electronic shutter speed input method. (With pull-up resistor) Low: Serial input, High: Parallel input Shutter speed setting. (With pull-up resistor) Shutter speed setting. (With pull-up resistor) GND Shutter speed setting. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) Reset gate pulse output. CCD discharge pulse output. Power supply. Clock output for horizontal CCD drive. Clock output for horizontal CCD drive. GND Clock output for vertical CCD drive. Clock output for vertical CCD drive. Clock output for vertical CCD drive. Sensor charge readout pulse output. Power supply. Sample-and-hold pulse output. Sample-and-hold pulse output. Sample-and-hold pulse output. GND Switching for external trigger discharge operation. (With pull-up resistor) Low: No high-speed discharge, High: High-speed discharge Switching for readout timing. (With pull-up resistor) Low: ESG input valid, High: ESG input invalid GND Test. (With pull-down resistor) WEN mode setting. (With pull-down resistor) Low: Effective line, High: XSG synchronization Power supply. Clamp pulse output. Clamp pulse output. Blanking cleaning pulse output. Line identification output. Write enable output. Trigger mode flag output. GND 780 fH clock output. AD conversion pulse output. —3— CXD2434ATQ Pin No. Symbol I/O 40 41 CKO RESET O I 42 STDBY I 43 44 45 46 47 48 TRIG ESG EFS HD VD TEST2 I I I I I I Description 1560 fH clock output. RESET. (With pull-up resistor) Low : Reset, High : Normal Standby. (With pull-up resistor) Low: Internal clock supply stopped, High: Normal External trigger input. (With pull-up resistor) External readout input. (With pull-up resistor) Vertical CCD discharge input. (With pull-up resistor) Horizontal sync signal input. Vertical sync signal input. Test. (With pull-up resistor) Electrical Characteristics 1. DC Characteristics Item VDD=4.75 V to 5.25 V Topr= –20 to +75 °C Symbol Supply voltage VDD Input voltage 1 VIH1 (Input pins other than those listed below) VIL1 Input voltage 2 VIH2 (Pin 2) VIL2 Output voltage 1 VOH1 (Output pins other than those listed below) VOL1 Output voltage 2 VOH2 (Pins 21, 22, 23, 38, 39 and 40) VOL2 Output voltage 3 VOH3 (Pin 10) VOL3 Output voltage 4 VOH4 (Pins 13 and 14) VOL4 Output voltage 5 VOH5 (Pin 1) VOL5 Feedback resistor RFB Pull-up resistor RPU Pull-down resistor RPD Current consumption IDD Conditions Min. 4.75 0.7 VDD Typ. 5.0 Max. 5.25 0.3 VDD 0.7 VDD 0.3 VDD IOH=–2.5 mA IOL=4.5 mA IOH=–5.0 mA IOL=9.0 mA IOH=–7.5 mA IOL=13.5 mA IOH=–14.0 mA IOL=24.0 mA VDD–0.4 0.4 VDD–0.4 0.4 VDD–0.4 0.4 VDD–0.4 0.4 VDD/2 VDD/2 VIN=VSS or VDD VIL=0 V VIH=VDD VDD=5 V —4— 1M 50 k 50 k 40 100 k 100 k Unit V V V V V V V V V V V V V V V Ω Ω Ω mA CXD2434ATQ 2. AC Characteristics 1) Waveform characteristics of H1, H2 and RG 0.9VDD H1 0.1VDD tRH1 tWH1 tFH1 tWH2 tRH2 0.9VDD H2 0.1VDD tFH2 0.9VDD RG 0.1VDD tRRG tWRG tFRG VDD=5.0 V, Topr=25 °C, load capacitance of H1 and H2=100 pF, load capacitance of RG=10 pF Symbol tRH1 tFH1 tWH1 tRH2 tFH2 tWH2 tRRG tFRG tWRG Definition Min. H1 rise time H1 fall time H1 high level time H2 rise time H2 fall time H2 low level time RG rise time RG fall time RG high level time 25 25 10 —5— Typ. 6 5 35 6 5 35 2 2 15 Max. 15 15 15 15 5 5 20 Unit ns ns ns ns ns ns ns ns ns CXD2434ATQ 2) Phase characteristics of H1, H2, RG, XSHP, XSHD, XRS, CL, CLD and CKO tH1 H1 0.5VDD 0.5VDD 0.5VDD H2 tPD3 RG 0.5VDD 0.5VDD tPD1 0.5VDD tPD2 0.5VDD tPD4 tPD5 tW1 0.5VDD XSHP 0.5VDD tW2 0.5VDD XSHD tPD6 0.5VDD tPD7 0.5VDD XRS 0.5VDD tPD8 0.5VDD CLD tPD10 tPD9 0.5VDD tW3 tW4 CL 0.5VDD 0.5VDD tW5 CLO 0.5VDD 0.5VDD 0.5VDD tPD11 tW5 0.5VDD tPD11 VDD=5.0 V, Topr=25 °C, load capacitance of CL and CKO=30 pF, load capacitance of CLD, XSHP, XSHD, XRS and RG=10 pF Symbol tH1 tPD1 tPD2 tPD3 tPD4 tPD5 tPD6 tPD7 tPD8 tPD9 tPD10 tPD11 tW1 tW2 tW3 tW4 tW5 Definition H1 cycle H2 rising delay, activated by the falling edge of H1 H2 falling delay, activated by the rising edge of H1 H1 rising delay, activated by the rising edge of RG XSHP falling delay, activated by the falling edge of RG H1 falling delay, activated by the rising edge of XSHP H1 rising delay, activated by the rising edge of XSHD CLD falling delay, activated by the falling edge of XSHD CLD falling delay, activated by the rising edge of XRS XRS falling delay, activated by the falling edge of CLD CL falling delay, activated by the rising edge of H1 H1 rising (falling) delay, activated by the rising edge of CKO XSHP pulse width XSHD pulse width CLD pulse width CL pulse width CKO pulse width —6— Min. –5 –5 –5 –2 –7 –5 –5 17 0 –5 –5 13 15 17 38 17 Typ. 82 0 0 0 4 2 2 2 22 8 0 2 18 20 22 41 20 Max. 5 5 5 10 7 7 7 27 15 5 7 23 25 27 45 24 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CXD2434ATQ 3) Phase conditions of HD, VD, TRIG, EFS and ESG 0.5VDD CL tSETUP tHOLD HD, VD, TRIG EFS, ESG 0.5VDD 0.5VDD VDD=5.0 V, Topr=25 °C, load capacitance of CL=30 pF Symbol tSETUP tHOLD Definition HD, VD, TRIG, EFS and ESG setup time, activated by CL HD, VD, TRIG, EFS and ESG hold time, activated by CL Min. 20 5 Typ. Max. Unit ns ns 4) Phase characteristics of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID CL 0.5VDD 0.5VDD tPDCL1 0.5VDD XV1, XV2, XV3 tPDCL2 0.5VDD BUSY, WEN, ID tPDCL3 XSG, PBLK, XCPDM, XCPOB 0.5VDD VDD=5.0 V, Topr=25 °C, load capacitance of CL=30 pF, load capacitance of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID=10 pF Symbol Definition tPDCL1 XV1, XV2 and XV3 delay, activated by the falling edge of CL tPDCL2 BUSY, WEN and ID delay, activated by the rising edge of CL XSG, PBLK, XCPDM and XCPOB delay, activated by the tPDCL3 rising edge of CL —7— Min. 30 40 40 Typ. Max. 65 60 Unit ns ns 55 ns CXD2434ATQ Description of Functions 1. Progressive Scan CCD drive pulse generation • Combining this IC with a crystal oscillator generates a fundamental frequency of 24.5454 MHz. • CCD drive pulse generation is synchronized with the HD and VD inputs. Set fCL to 780 fHD and fHD to 525 fVD. • The various operations are performed by the TRIG, EFS and ESG inputs. (See the following items.) <Detection timing for VD, TRIG, EFS and ESG> CL 1 35 HD H1 T1 Detection timing for VD, TRIG, EFS and ESG After HD input is detected, the status of VD, TRIG, ESG and EFS is detected during T1. Do not change the status of VD, TRIG, ESG and EFS during T1. When input is from a non-synchronized system, the low level period for each pulse should be set to 63.5 µs or longer to prevent misoperation. 2. Reset The internal register values are undetermined immediately after power-on, so perform one of the following reset operations. 1. Reset by the RESET pin Reset is performed by setting the RESET pin low for a period of 80 ns or more. Reset can also be performed by setting the RESET pin low during power-on and then switching the RESET pin from low to high when VDD rises to 4.75 V or higher. Note that when reset is performed by the RESET pin, the electronic shutter settings made by serial input are also reset. 2. Reset by turning off the electronic shutter Reset is performed by setting the shutter mode to electronic shutter off and inputting VD. Note that in this case the TRIG, ESG and EFS pins should all be set high. —8— CXD2434ATQ 3. Electronic shutter <Shutter modes> The electronic shutter has the following four shutter modes. • Electronic shutter off : Exposure time is 1/30 s. • High-speed electronic shutter : Exposure time is shorter than 1/30 s. • Low-speed electronic shutter: Exposure time is longer than 1/30 s. • Flickerless : Exposure time is 1/50 s. This is a special feature of the high-speed electronic shutter, and reduces flicker from fluorescent lights, etc. in areas with 50 Hz power supply <Shutter mode and speed setting methods> PS=Low : Serial input; set by the STRB, DCLK and DATA pins. The SMD1 and SMD2 pins are not used. PS=High : Parallel input; set by the STRB, DCLK, DATA, SMD1 and SMD2 pins. 3-1. [Serial input] Serial input is set by the STRB, DCLK and DATA pins. The electronic shutter mode and the meanings of the numbers indicated by D0 to 9 vary according to the SMD1 and SMD2 setting of the internal register. STRB DCLK DATA SMD1 H L H SMD2 SMD1 SMD2 H H L D9 D8 D7 D6 D5 D4 D3 Mode Electronic shutter off (1/30 s accumulation) High-speed electronic shutter Low-speed electronic shutter D2 D1 D0 D0 to 9 — Number of exposed lines (Note 1) Number of exposed frames (Note 2) Note 1) Relationship between the number of exposed lines and the exposure time The relationship between the number of exposed lines and the exposure time is as follows. (Exposure time)=(Number of exposed lines) × (One horizontal scan period) + (Accumulation time for the readout lines) In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for the readout lines is the time from the rising edge of XSUB to the rising edge of XSG (456 bits). Also, (Number of exposed lines) should be set to greater than 1 but less than 524. Note 2) The number of exposed frames should be set to greater than 1 but less than 1023. However, when the number of exposed frames is 1 and SMDE is set to high, external trigger mode does not function. Timing Chart (Serial input) STRB tWD tSDS tSDD tHDD DCLK DATA —9— tWS CXD2434ATQ AC characteristics for serial input Symbol tSDD tHDD tSDS tWS tWD Definition DATA setup time, activated by the rising edge of DCLK DATA hold time, activated by the rising edge of DCLK DCLK setup time, activated by the falling edge of STRB STRB pulse width DCLK pulse width Min. 10 ns 10 ns 10 ns 82 ns 82 ns Max. — — — — — 3-2. [Parallel input] Mode Electronic shutter off Flickerless High-speed shutter Low-speed shutter PS H H H H H H H H H H H H H H H H H H SMD1 H L L L L L L L L L H H H H H H H H SMD2 H L H H H H H H H H L L L L L L L L —10— STRB X X H L H L H L H L H L H L H L H L DCLK X X H H L L H H L L H H L L H H L L DATA X X H H H H L L L L H H H H L L L L Exposure time 1/30 s 1/50 s 1/60 s 1/125 s 1/250 s 1/500 s 1/1000 s 1/2000 s 1/4000 s 1/10000 s 2 FRM 3 FRM 4 FRM 5 FRM 6 FRM 7 FRM 8 FRM 9 FRM CXD2434ATQ 4. External trigger mode External trigger mode starts exposure in sync with the external trigger input. No special pins are required to set this mode. The IC prepares to shift to external trigger mode with the falling edge of the TRIG pin (Note). The timing to shift to external trigger mode varies according to the mode setting. (See the table.) The BUSY pin maintains high status during external trigger mode. Whether or not to discharge the vertical CCD charge is set by FSE. Note) See the detection timing for VD, TRIG, EFS and ESG. Mode settings during external trigger (Note 1) PS L H H X X SMD1 SMD2 Description of operation L X The IC is shifted to external trigger mode by HD, exposure is finished after the set L H time, and XSG is output. (Note 2) (Note 3) The IC is shifted to external trigger mode by HD, exposure is finished 1/50 s later, L L and XSG is output. H L Do not set for external trigger. H H Trigger input is not accepted. Note 1) The SMD1 and SMD2 setting method varies according to the PS status. See “3. Electronic shutter”. PS=Low : Set by serial input. PS=High : Set by the SMD1 and SMD2 pins. Note 2) The exposure time setting method is the same as the exposure time setting for the electronic shutter. Note 3) When FSE=high, set the number of exposed lines from 1 to 522. <FSE and discharge operation> During external trigger mode, the previously exposed signal charge sometimes remains in the vertical CCD when exposure finishes. In this case, the image shot with external trigger mode is output overlapped with the previously shot image. Setting FSE to high performs discharge operation for signal charges remaining in the vertical CCD after trigger input. Discharge operation is not performed when FSE is low. This setting is only valid when SMD1 is low. <Finishing the exposure period with ESG> During external trigger mode, exposure can be finished in sync with the falling edge of ESG (Note). If SMDE is set to low, the XSG pulse is output regardless of the electronic shutter setting, when the falling edge of ESG is detected. ESG should be fixed to high status at all times other than during external trigger mode. Do not change SMDE while BUSY is high. Note) See the detection timing for VD, TRIG, EFS and ESG. <Signal after external trigger mode> After high-speed external trigger mode is finished, the exposure time differs from that performed by the electronic shutter setting. This is because the start and finish of external trigger mode are not synchronized to VD input. —11— CXD2434ATQ 5. Discharge of the vertical CCD During EFS is low, discharge of the vertical CCD is performed. During FSE is high in the external trigger mode, the vertical control line by line is possible. That is different from discharge operation. The falling in the effective interval of EFS is detected, discharge is not performed even if the low status is held until the next effective period. For frames using EFS, set electronic shutter off or high-speed electronic shutter. When EFS is used, WEN (WM=low) may not indicate the proper status. <Discharge start> Vertical CCD discharge is started in sync with HD input after the falling edge of EFS (Note). Approximately 3420 ns (81.4 ns × 42 clock pulses) are required to transfer one line vertically. Note) See the detection timing for VD, TRIG, EFS and ESG. <Discharge finish> Since the operation uses 42 clock pulses as one unit, when the rising edge of EFS is detected in interval [n], discharge operation stops from interval [n+1]. The period from the rising edge of EFS to the falling edge of VD must be longer than 2HD. Timing Chart 1 n–1 n n+1 EFS XV1 XV3 Timing Chart 2 n n+1 CL XV3 <Maximum number of dischargeable lines> The number of lines transferred by discharge transfer and normal transfer during the following period should not exceed 4096 lines. Period : The period from when the XSG pin becomes low until XSG becomes low again or the TRIG pin becomes low. 6. Internal logic stop (standby mode) When the STDBY pin is set to low, clock supply is stopped to a part of the internal logic. However, output from the oscillation cell (OSCI and OSCO pins) as well as the CL and CKO pins does not stop. The status of each output pin when STDBY is low is shown below. High : Low : XSUB, XSG RG, H1, H2, XV1, XV2, XV3, XSHP, XSHD, XRS, XCPOB, XCPDM, PBLK, ID, WEN, BUSY, CLD Not stopped : OSCO, CL, CKO —12— CXD2434ATQ 7. Mode settings 7-1. VD input-related BUSY H L SMD1 L SMD2 H H L X X SMDE X X H X EFS X H L VD input Invalid Readout operation or the number of accumulated frames is counted. Readout operation is performed. Invalid Note 1) When PS is high, SMD1 and SMD2 indicate the status of the SMD1 and SMD2 pins, respectively. When PS is low, these are the corresponding internal register values. See “3. Electronic shutter”. Note 2) Operation when PS=high, SMD1=low and SMD2=low conforms to that when SMD1=low and SMD2=high. 7-2. TRIG, ESG and EFS input-related BUSY H SMDE Discharge period (Note 1) X Exposure period H L TRIG L After TRIG input (Note 2) (Note 3) X EFS Prohibited Invalid Prohibited Readout operation (Note 4) Prohibited Signal output period Before TRIG input ESG IC shifted to external trigger mode (Note 3) Prohibited Discharge operation (Note 6) (Note 7) Prohibited (Note 5) Prohibited Note 1) Only when FSE is high. Note 2) Valid only during low-speed shutter. Note 3) See “4. External trigger mode”. Note 4) ESG input is valid only one time after TRIG input. Do not input ESG two times or more. Note 5) Fix ESG to high status when BUSY is low. Note 6) When EFS is low, readout is not activated by VD input. See “7-1. VD input-related”. Note 7) Use in electronic shutter off state. Note 8) In case any two pins or more among TRIG, ESG, and EFS are falled at the same time, the operation is not guaranteed. 7-3. WEN mode switching by WM WM L H Description of WEN operation Lines for which the signal from the CCD is valid output high; all other lines output low. Output is synchronized with XSG. —13— —14— 7 8 9 10 11 12 13 6 48 5 14 47 4 15 46 3 16 45 2 17 18 44 43 1 25 19 CXD2434ATQ 26 42 27 20 28 41 29 21 30 40 31 22 32 39 33 23 34 38 35 24 36 37 CXD1267AN +5V 1000p ICX084AK/AL 100k +15V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Reset Circuit Application Circuit CXA2006Q CXD2311AR CXD2434ATQ —15— BUSY WEN (WM=Low) WEN (WM=High) ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 OUT HD VD Normal Operation (vertical synchronization) 14 1 2 3 4 5 6 7 8 1 2 3 4 494 CXD2434ATQ 510 508 1 —16— 1 12 31 35 35 35 780 47 XSUB may be kept high depending on the electronic shutter setting. BUSY WEN ID XCPDM XCPOB PBLK XRS XSHD XSHP RG H2 H1 XSUB XSG (=High) XV3 XV2 XV1 CL HD 1 Normal Operation (horizontal synchronization) 59 71 72 78 83 93 95 95 109 119 120 CXD2434ATQ 107 —17— BUSY =High(trig) Low(others) WEN (=Low) ID XCPDM PBLK (=Low) XCPOB XRS XSHD XSHP RG H2 H1 XSUB (=High) XSG XV3 XV2 XV1 CL HD 1 12 31 35 35 780 1 47 Normal Operation: readout timing (horizontal synchronization) 59 71 78 83 93 109 119 520 551 576 CXD2434ATQ 107 —18— 27 1 ∗ See “3. Electronic Shutter” for the time from TRIG input to XSG. ∗ The fall of VD is invalid during the period while BUSY=high. BUSY WEN (WM=Low) WEN (WM=High) ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD TRIG 1 2 3 4 5 6 7 8 1 2 3 4 14 1 External Trigger Mode: high-speed electronic shutter, discharge (FSE=high, SMDE=high, SMD1=low, SMD2=high) CXD2434ATQ 508 —19— BUSY WEN ID XCPDM XCPOB PBLK XRS XSHD XSHP RG H2 H1 XSUB XSG (=High) XV3 XV2 XV1 CL HD TRIG 12 31 35 35 35 780 1 42 49 56 1 63 72 70 77 93 95 2 External Trigger Mode: high-speed electronic shutter, when discharge starts (FSE=high, SMD1=low, SMD2=high) 3 CXD2434ATQ —20— WEN (=Low) BUSY (=High) PBLK =(Low) XCPOB (=High) XCPDM (=High) ID XRS XSHD XSHP RG H2 H1 XSUB XSG (=High) XV3 XV2 XV1 CL HD 499 500 External Trigger Mode: high-speed electronic shutter, when discharge finishes (FSE=high, SMD1=low, SMD2=high) CXD2434ATQ —21— ∗ See “3. Electronic Shutter” for the time from TRIG input to XSG. ∗ The fall of VD is invalid during the period while BUSY=high. BUSY WEN (WM=Low) WEN (WM=High) ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD TRIG 14 1 2 3 4 5 6 7 812 3 4 508 1 External Trigger Mode: high-speed electronic shutter, no discharge (FSE=low, SMDE=high, SMD1=low, SMD2=X) CXD2434ATQ —22— 1 The fall of VD is invalid during the period while BUSY=high. BUSY WEN (WM=Low) WEN (WM=High) ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD ESG TRIG 27 Example during ESG Input (FSE=high, SMDE=low, SMD1=low, SMD2=X) 14 1 2 3 45 6 7 8 1 2 3 4 CXD2434ATQ 508 1 —23— 27 1 The fall of VD is invalid during the period while BUSY=high. BUSY WEN (WM=Low) WEN (WM=High) ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD 42 bits ×104 times 6 EFS 13 TRIG 1 Example during EFS Input (trigger mode: FSE=high, SMDE=high, SMD1=low, SMD2=X) 98 99 339 340 CXD2434ATQ 264 256 —24— BUSY WEN ID XCPDM XCPOB PBLK XRS XSHD XSHP RG H2 H1 XSUB (=High) XSG (=High) XV3 XV2 XV1 CL HD EFS 780 1 12 During EFS Input, when discharge starts 31 35 35 35 42 49 56 63 70 77 93 CXD2434ATQ 107 —25— WEN (=Low) BUSY (=Low) PBLK =(Low) XCPOB (=High) XCPDM (=High) ID XRS XSHD XSHP RG H2 H1 XSUB XSG (=High) XV3 XV2 XV1 CL HD EFS During EFS Input, when discharge finishes CXD2434ATQ CXD2434ATQ Unit : mm 48PIN TQFP (PLASTIC) 1.27 MAX 9.0 ± 0.4 7.0 ± 0.2 36 1.0 ± 0.1 25 0.1 37 24 A 13 48 1 12 0.5 0.2 ± 0.1 0.08 0.125 ± 0.05 M + 7° 3° – 3° 1.0 ± 0.2 0.1 ± 0.1 0.5 ± 0.2 Package Outline DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE TQFP-48P-L071 LEAD TREATMENT SOLDER PLATING EIAJ CODE TQFP048-P-0707-AN LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE —26—