SONY CXD2460R

CXD2460R
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2460R is an IC developed to generate the
timing pulses required by Progressive Scan CCD
image sensors as well as signal processing circuits.
Features
• Electronic shutter function
• Supports non-interlaced operation
• Base oscillation frequency 28.636MHz
• Horizontal drive frequency switchable between
14.3/7.2MHz
• Switchable between FINE (Progressive Scan) mode
or DRAFT (high-speed draft) mode
• Built-in vertical driver
Applications
Progressive Scan CCD cameras
48 pin LQFP (Plastic)
Absolute Maximum Ratings
• Supply voltage VDDa, VDDb, VDDc, VDDd
Vss – 0.5 to Vss + 7.0
• Supply voltage VSS
VL – 0.5 to VL + 26.0
• Supply voltage VH
VL – 0.5 to VL + 26.0
• Supply voltage VM
VL – 0.5 to VL + 26.0
• Input voltage VI Vss – 0.5 to VDDa,b,c,d + 0.5
V
V
V
V
V
• Output voltage VO Vss – 0.5 to VDDa,b,c,d + 0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensor
ICX205AK
Recommended Operating Conditions
• Supply voltage 1 VDDa, VDDb, VDDd
3.0 to 3.6
• Supply voltage 2 VDDc
3.0 to 5.25
• Supply voltage 3 VH
14.25 to 15.75
• Supply voltage 4 VL
–9.0 to –5.0
• Supply voltage 5 VM
0
• Operating temperature
Topr
–20 to +75
V
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98414-PS
CXD2460R
H2
RG
XSHD
XSHP
XRS
VM
V1
V3
V2A
VH
V2B
SUB
VL
9
18
17
19
39
40
41
42
43
44
45
46
5
V-Driver
XSUB
XSGA
3
XSGB
4
XV2
CKI
13
XV3
OSCO
12
XV1
OSCI
H1
Block Diagram
15 XCPDM
CKO 1
1/2
21 PBLK
2MCK 27
22 XCPOB
Pulse Generator
32 ID
33 EXP
1/2
28 TEST2
MCK 25
ADCLK 23
VDD0 6
AVD0 8
AVD2 16
47 DSGAT
SSG
AVD1 14
48 PS
1/1790
VDD1 26
VSS0 2
1/1068 1/267
29 SEN
VSS1 10
Register
VSS2 11
31 SSI
VSS3 20
7
24
RST
38
FRI
HRI
FRO
HRO
37
TEST1
VSS4 36
35 34
30 SSK
XSGA and XSGB are readout pulses that use V2A and V2B, respectively, as the VH value.
–2–
CXD2460R
VSS4
FRO
HRO
EXP
ID
SSI
SSK
SEN
TEST2
2MCK
VDD1
MCK
Pin Configuration (Top View)
36
35
34
33
32
31
30
29
28
27
26
25
V3
41
20 VSS3
V2A
42
19 XRS
VH
43
18 XSHD
V2B
44
17 XSHP
SUB
45
16 AVD2
VL
46
15 XCPDM
DSGAT
47
14 AVD1
PS
48
13 H2
1
2
3
4
5
6
7
8
9
10
11
12
H1
21 PBLK
VSS2
40
VSS1
V1
RG
22 XCPOB
AVD0
39
TEST1
VM
VDD0
23 ADCLK
OSCI
38
OSCO
FRI
CKI
24 RST
VSS0
37
CKO
HRI
The enclosed pins use separate power supplies.
–3–
CXD2460R
Pin Description
Pin
No.
Symbol
I/O
Description
1
CKO
O
Oscillator output. (28.6MHz)
2
Vss0
—
GND
3
CKI
I
Oscillator input. (28.6MHz)
4
OSCO
O
Inverter output for oscillation. (28.6MHz)
5
OSCI
I
Inverter input for oscillation. (28.6MHz)
6
VDD0
—
7
TEST1
I
8
AVD0
—
Power supply.
9
RG
O
Reset gate pulse output.
10
Vss1
—
GND
11
Vss2
—
GND
12
H1
O
Clock output for horizontal CCD drive.
13
H2
O
Clock output for horizontal CCD drive.
14
AVD1
—
Power supply.
15
XCPDM
O
Clamp pulse.
16
AVD2
—
Power supply.
17
XSHP
O
Sample-and-hold pulse.
18
XSHD
O
Sample-and-hold pulse.
19
XRS
O
Sample-and-hold pulse.
20
VSS3
—
GND
21
PBLK
O
Blanking cleaning pulse.
22
XCPOB
O
Clamp pulse.
23
ADCLK
O
Clock output for AD conversion.
24
RST
I
Reset (Low: Reset, High: Normal operation).
Always input one reset pulse during power-on.
25
MCK
O
Clock output for digital circuit.
26
VDD1
—
Power supply.
27
2MCK
O
Clock output for digital circuit.
28
TEST2
I
Test. Fix to high.
29
SEN
I
PS = High: Drive frequency setting input.
PS = Low: Serial setting strobe input.
30
SSK
I
PS = High: Readout method setting input.
PS = Low: Serial setting clock input.
31
SSI
I
PS = High: Shutter speed setting input.
PS = Low: Serial setting data input.
32
ID
O
Line identification signal output write enable pulse output or XSUB output.
33
EXP
O
Pulse output indicating exposure is underway or checksum result output.
Power supply.
Test. With pull-down resistor. Fix to low.
–4–
CXD2460R
Pin
No.
Symbol
I/O
Description
34
HRO
O
Horizontal sync signal (HR) output or XSGA output.
35
FRO
O
Vertical sync signal (FR) output or XSGB output.
36
VSS4
—
GND
37
HRI
I
Horizontal sync signal (HR) input.
38
FRI
I
Vertical sync signal (FR) input.
39
VM
—
GND (vertical clock driver GND).
40
V1
O
Clock output for vertical CCD drive.
41
V3
O
Clock output for vertical CCD drive.
42
V2A
O
Clock output for vertical CCD drive.
43
VH
—
15V power supply (vertical clock driver power supply).
44
V2B
O
Clock output for vertical CCD drive.
45
SUB
O
CCD electric charge sweep pulse output.
46
VL
—
–8.0V power supply (vertical clock driver power supply).
47
DSGAT
I
Output stop (Same operation control as SLP when low).
48
PS
I
Parallel/serial switching for mode setting input method.
(High: Parallel, Low: Serial) With pull-down resistor.
–5–
CXD2460R
Electrical Characteristics
DC Characteristics
Item
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1 VDD0, VDD1,
VDDa
3.0
3.3
3.6
V
Supply voltage 2 AVD0
VDDb
3.0
3.3
3.6
V
Supply voltage 3 AVD1
VDDc
3.0
5.0
5.25
V
Supply voltage 4 AVD2
VDDd
3.0
3.3
3.6
V
Supply voltage 5 VH
VH
14.5
15.0
15.5
V
Supply voltage 6 VM
VM
—
0.0
—
V
Supply voltage 7 VL
VL
–9.0
–5.0
V
VIH1
0.7VDDa
Input voltage 1
CKI
VIL1
0.3VDDa
VIH2
Input voltage 2
Input voltage 3
Output voltage 1
TEST1, PS
VIL2
VOH1
Feed current where IOH = –10.0mA VDDa – 0.8
VOL1
Pull-in current where IOL = 7.2mA
VOH2
Feed current where IOH = –3.3mA VDDb – 0.8
VOL2
Pull-in current where IOL = 2.4mA
VOH3
Feed current where IOH = –36.0mA VDDc – 0.8
VOL3
Pull-in current where IOL = 24.0mA
VOH4
Feed current where IOH = –3.3mA VDDd – 0.8
VOL4
Pull-in current where IOL = 2.4mA
Output voltage 3 H1, H2
XCPDM, XSHP,
Output voltage 4 XSHD, XRS,
PBLK, XCPOB
Feed current where IOH = –2.4mA VDDa – 0.8
VOH6
Feed current where IOH = –4.0mA VH – 0.25
VOL6
Pull-in current where IOL = 5.4mA
VOM7
Feed current where IOH = –5.0mA VM – 0.25
VOL7
Pull-in current where IOL = 10.0mA
Output voltage 6 SUB
Output voltage 7 V1, V3
Pull-in current where IOL = 4.8mA
VOM102 Pull-in current where IOL = 5.0mA
VOL8
Feed current where IOH = –5.0mA VM – 0.25
VOL8
Pull-in current where IOL = 10.0mA
–6–
V
V
0.4
V
V
0.4
V
V
0.4
V
V
0.4
V
V
0.4
V
V
VL + 0.25
V
V
VL + 0.25
VOM101 Feed current where IOH = –7.2mA VH – 0.25
Output voltage 8 V2A, V2B
V
V
0.2VDDa
ID, EXP, HRO, VOH5
FRO
VOL5
V
V
0.3VDDa
0.8VDDa
Output voltage 2 RG
Output voltage 5
0.7VDDa
RST, TEST2,
Vt + 1
SEN, SSK, SSI,
HRI, FRI, DSGAT Vt – 1
CKO, MCK,
2MCK
V
V
V
VM + 0.25 V
V
VL + 0.25
V
CXD2460R
(Within the recommended operating conditions)
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input voltage
OSCI
Output voltage
OSCO
Symbol
Conditions
Min.
LVth
VIH
0.3VDDa
Pull-in current where IOL = 6.0mA
Feedback resistor OSCI, OSCO
RFB
VIN = VDDa or Vss
Oscillator frequency OSCI, OSCO
f
Input voltage
Symbol
500k
Conditions
Min.
Typ.
5M
Ω
50
MHz
Max.
V
0.3VDDa
fmax 50MHz sine wave
Unit
V
0.7VDDa
VIL
VIN
V
VDDa/2
VIH
Input amplitude
2M
VDDa/2
(Within the recommended operating conditions)
LVth
CKI
V
V
20
Base Oscillation Clock Input Characteristics
Logical Vth
V
VIL
VOL
Unit
V
0.7VDDa
Feed current where IOH = –6.0mA VDDa/2
Pins
Max.
VDDa/2
VOH
Item
Typ.
V
Vp-p
0.3
∗1 Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is
the input amplitude characteristics for input through capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise
voltage
(VH = 15.0V, VM = GND, VL = –8.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
350
550
ns
TTMH
VM to VH
450
700
ns
TTLH
VL to VH
50
80
ns
TTML
VM to VL
250
400
ns
TTHM
VH to VM
300
450
ns
TTHL
VH to VL
50
80
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
∗1 The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
∗2 For noise and latch-up countermeasures, be sure to connect a bypass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
–7–
CXD2460R
Switching Waveforms
TTMH
TTHM
VH
90%
90%
TTLM
TTML
10%
V2A (V2B)
10%
VM
90%
90%
10%
10%
TTLM
VL
TTML
VM
90%
90%
V1 (V3)
10%
10%
VL
TTHL
TTLH
VH
90%
90%
VSUB
10%
10%
VL
Waveform Noise
VCMH
VCML
VH
VCLH
VCLL
VL
Measurement Circuit
C1
R1
R1
C2
C2
V1
V3
C1
C1
C2
V2A
C2
V2B
R1
R1
C1
R2
–8–
R1: 27Ω
R2: 5Ω
C1: 1500pF
C2: 3300pF
CXD2460R
AC Characteristics
1) AC characteristics between the serial interface clocks
SSI
0.8VDDa
0.2VDDa
0.8VDDa
SSK
0.2VDDa
ts1
SEN
th1
0.2VDDa
ts3
0.8VDDa
SEN
ts2
th2
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
th1
ts2
th2
ts3
SSI setup time, activated by the rising edge of SSK
20
ns
SSI hold time, activated by the rising edge of SSK
20
ns
SSK setup time, activated by the rising edge of SEN
20
ns
SSK hold time, activated by the rising edge of SEN
20
ns
SEN setup time, activated by the rising edge of SSK
20
ns
fk
SSK frequency
7.15
2) Serial interface clock internal loading characteristics
V2A
HRI
0.5VDDa
0.5VDDa
300ns
300ns
Do not start up SEN during this period.
(From 300ns from the falling edge of HRI immediately before
generation of XSGA pulse to 300ns from the falling edge of
HRI immediately after generation of XSGA pulse)
–9–
MHZ
CXD2460R
3) Output timing characteristics using DSGAT and RST
twRST
0.5VDDa
0.5VDDa
DSGAT, RST
EXP, XCPDM, XCPOB,
PBLK, XSHP, XSHD, XRS,
RG, H1, H2
0.5VDDa, b, c, d
tpRST
H1 and H2 load = 270pF
EXP, XCPDM, PBLK, XSHP, XSHD, XRS and RG load = 10pF (Within the recommended operating conditions)
Symbol
Definition
Min.
tpRST
Time until the above outputs reach the specified value after
the fall of DSGAT and RST
twRST
RST and DSGAT pulse width
Typ.
Max.
Unit
125
ns
ns
10
4) FRI and HRI loading characteristics
FRI, HRI
0.5VDDa
0.5VDDa
tsSYNC
0.5VDDa
MCK
MCK load = 35pF
Symbol
tsSYNC
thSYNC
thSYNC
(Within the recommended operating conditions)
Definition
Min.
FRI and HRI setup time, activated by the rising edge of MCK
5
ns
FRI and HRI hold time, activated by the rising edge of MCK
5
ns
– 10 –
Typ.
Max.
Unit
CXD2460R
5) Output variation characteristics of ID, WEN, EXP, FRO and HRO
MCK
0.5VDDa
EXP, ID, WEN
0.5VDDa
tpdEXP
0.5VDDa
FRO, HRO
tpdSYNCO
EXP, ID and WEN load = 10pF
Symbol
(Within the recommended operating conditions)
Definition
Min.
tpdEXP
Time until the WEN, ID and EXP outputs change after the
fall of MCK
tpdSYNCO
Time until the FRO and HRO outputs change after the fall
of MCK
– 11 –
Typ.
Max.
Unit
0.5
8.5
ns
0.5
3.5
ns
CXD2460R
Description of Operation
1. Progressive Scan CCD drive pulse generation
• Combining this IC with a crystal oscillator generates a fundamental frequency of 28.636MHz.
• CCD drive pulse generation is synchronized with HRI and FRI.
• The CCD drive method can be changed to various modes by inputting serial data or parallel data to the
CXD2460R.
• The various drive methods possessed by the CXD2460R are shown in the Timing Charts A-1 to 3 (V rate)
and B-1 to 6 (H rate).
2. Serial data input method
• All CXD2460R operations can be controlled via the serial data. The serial data format is as follows.
SSI
00
01
02
03
04
05
06
41
42
43
44
45
46
47
SSK
SEN
Serial data format
Serial data
When reset
Function
Symbol
Data
D00
to
D07
CHIP
Chip switching
See D00 to D07
CHIP.
All 0
D08
to
D11
CTGRY
Category switching
See D08 to D11
CTGRY.
All 0
D12
to
D39
DATA
Control data for each category
The meaning of this CTGRY control data
differs according to the category set by D08 to
D11.
See D12 to D39
DATA.
All 0
D40
to
D47
Checksum bits
Checksum bits
See D40 to D47
CHKSUM.
All 0
– 12 –
CXD2460R
3. Serial data and description of functions
Detailed description
D00
The serial interface data is loaded to the CXD2460R when D00 and D07 are "1". However, this
assumes that D40 to D47 CHKSUM is satisfied.
to
D07
CHIP
D07
D06
1
0
D05 D04
0
D03
0
0
D02 D01
0
D00
0
1
Function
Loading to the CXD2460R
This CTGRY data indicates the functions that the serial interface data controls.
D08
to
D11
CTGRY
D11
D10
D09 D08
0
0
0
0
Mode control data
0
0
1
0
Electronic shutter control data
0
0
1
1
High-speed phase adjustment data (Set all of D12 to D39 to "0".)
0
1
0
0
System setting data
Function
Input of values other than those listed above is prohibited.
CTGRY: Mode control data
Detailed description
0: Power saving drive mode
1: High-speed drive mode
When FHIGH = 0, the clock input to CKI is immediately frequency divided by 1/2 and loaded
internally.
Mode switching timing
(5 clocks after the fall of HRI just before XSGA is generated)
D12
FHIGH
MCK
Unstable
Unstable
CKI
FHIGH = 1
FHIGH = 0
FHIGH = 1
The high-speed phases of H1, H2, RG, XSHP, XSHD, XRS, ADCLK and other pulses are always
logically the same phase with respect to MCK.
0: DRAFT mode
1: FINE mode
D13
FINE
In FINE mode, image data is taken by the normal Progressive Scan method.
In DRAFT mode, image data is taken by pulse elimination readout. This enables a frame rate
four times that during FINE mode. The mode is switched at the fall of HRI just before XSGA.
Note that the FRO output is also switched accordingly. (DRAFT mode: 267H, FINE mode: 1068H)
0: Normal operation
1: Readout prohibited mode
D14
NSG
In readout prohibited mode, a readout pulse is not added even at the timing when a readout pulse
is added to V2A and V2B (VH value). (V1, V2 and V3 are not modulated.)
The mode is normally switched at the fall of HRI just before the position where the readout pulse
is added.
– 13 –
CXD2460R
Detailed description
0: Normal operation
1: FS mode
D15
In order to increase the frame rate, a certain portion of the captured image of CCD can be cut out
by performing high-speed sweep.
In FS mode, high-speed sweep is performed for the V registers of the entire image (period Z)
after FRI input. Next, high-speed sweep is performed again for only the desired period (period X)
after generating the XSGA/XSGB pulses. Then, after performing normal V transfer and outputting
the effective signal (period Y), high-speed sweep is performed for the entire image again by
inputting FRI at the desired timing. This makes it possible to take only the desired portion in the V
direction, thus effectively increasing the frame rate.
Operation is fixed during period Z, with 20 lines swept every 1H and repeating over a 69H period.
During period X, first XSGA/XSGB are generated. These pulses are dependent on serial data
FINE. In other words, if FINE = 1, then both XSGA and XSGB are generated, while if FINE = 0,
only XSGA is generated. Next, sweep operation starts. This period is set in serial data FVFS
(system setting data: D21 to D26) in HRI units. If FINE = 1, sweeping is performed at 8 lines per
1H, and if FINE = 0, sweeping is performed at 20 lines per 1H.
The operations of V1, V2 and V3 after readout during period Y differ depending on the FINE
data.
FS
• When the frame rate is increased as the
vertical effective signal Y line (example)
X
, ,,
,
, ,
,
,
Sweep variable period (period X)
Effective signal period (period Y)
Y
Sweep fixed period (period Z)
Z
Reset by FRI after
normal transfer
Timing chart
FRI
Z
X
Y
V2A
69H
(Fix)
Set by FVFS
D16
to
Set to "0".
D17
– 14 –
1068
CXD2460R
Detailed description
Operation control settings
The operating mode control bits are loaded to the CXD2460R at the rise timing of the SEN input,
and control is applied immediately.
D19
D18
Symbol
Control mode
0
0
CAM
Normal operation mode
0
1
SLP
Sleep mode (mode for the status where CCD drive is not required)
1
X
STN
Standby mode
Pin status during operation control
Symbol
CAM
SLP
STN
RST∗
Pin
No.
Symbol
CAM
SLP
STN
RST∗
1
CKO
ACT
ACT
ACT
ACT
25
MCK
ACT
ACT
ACT
ACT
2
VSS0
—
—
—
—
26
VDD1
—
—
—
—
3
CKI
ACT
ACT
ACT
ACT
27
2MCK
ACT
ACT
ACT
ACT
4
OSCO
ACT
ACT
ACT
ACT
28
TEST2
—
—
—
—
5
OSCI
ACT
ACT
ACT
ACT
29
SEN
ACT
ACT
—
—
6
VDD0
—
—
—
—
30
SSK
ACT
ACT
—
—
7
TEST1
—
—
—
—
31
SSI
ACT
ACT
—
—
8
AVD0
—
—
—
—
32
ID
ACT
L
L
L
9
RG
ACT
L
L
L
33
EXP
ACT
L
L
L
10
VSS1
—
—
—
—
34
HRO
ACT
ACT
L
L
11
VSS2
—
—
—
—
35
FRO
ACT
ACT
L
L
12
H1
ACT
L
L
L
36
VSS4
—
—
—
—
13
H2
ACT
L
L
L
37
HRI
ACT
ACT
—
—
14
AVD1
—
—
—
—
38
FRI
ACT
ACT
—
—
15
XCPDM
ACT
L
L
L
39
VM
—
—
—
—
16
AVD2
—
—
—
—
40
V1
ACT
VM
VM
VM
17
XSHP
ACT
L
L
L
41
V3
ACT
VM
VM
VM
18
XSHD
ACT
L
L
L
42
V2A
ACT
VH
VH
VH
19
XRS
ACT
L
L
L
43
VH
—
—
—
—
20
VSS3
—
—
—
—
44
V2B
ACT
VH
VH
VH
21
PBLK
ACT
L
L
L
45
SUB
ACT
VH
VH
VH
22
XCPOB
ACT
L
L
L
46
VL
—
—
—
—
23
ADCLK
ACT
L
L
L
47
DSGAT
ACT
ACT
L
L
24
RST
ACT
ACT
ACT
ACT
48
PS
ACT
ACT
ACT
ACT
Pin
No.
D17
to
D18
STB
∗ See "6. RST pulse" for a detailed description of RST.
Note) ACT indicates circuit operation, and L indicates "low" output level in the controlled status.
For sleep mode or standby mode, stop supplying VH and VL power supplies with CCD
image sensor.
– 15 –
CXD2460R
Detailed description
D20
EXPXEN
0: The EXP pulse indicating the exposure period is generated (when PS = low).
1: The EXP pulse indicating the exposure period is not generated (when PS = low), and is
constantly fixed to low.
This bit is invalid when STATUS = 1.
Note that the STB setting has priority.
D21
to
Invalid data
D24
D25
to
D29
VSHUT
Low-speed electronic shutter setting.
The value set here is the number of FR during which readout operation is not performed even if
there is input. The setting range is from "0" to "31". When set to "0", readout operation is
performed at the first FR.
When FS = 1, this bit is invalid.
MSB
D29
D28
D27
D26
LSB
Function
D25
Number of FR during which readout operation is not performed
D30
to
Invalid data
D39
CXD2460R clock system
When using a 28.636MHz crystal
FHIGH
FINE
Mode1
1
1
14.3MHz
28.6MHz
7.5Frame/s
Basic
Mode2
1
0
14.3MHz
28.6MHz
30Frame/s
DRAFT
Mode3
0
0
7.2MHz
14.3MHz
15Frame/s
Power-save
MCK frequency 2MCK pin output
Frame rate
Note) Combinations of FHIGH and FINE other than those listed above are prohibited.
– 16 –
CXD2460R
CTGRY: Electronic shutter control data
Detailed description
D12
to
D22
HSHUT
High-speed electronic shutter setting.
The value set here is the number of SUB pulses from FR to the next FR.
MSB
LSB
D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
Function
Number of SUB pulses setting
D23
to
Input "0".
D39
High-speed and low-speed electronic shutter can be used together. Therefore, the exposure time is as follows:
FR cycle × VSHUT + (fv – HSHUT) × HR cycle + 634/MCK frequency [Hz] = Exposure time [s]
(fv: Number of HR in 1FR)
– 17 –
CXD2460R
CTGRY: System setting data
Detailed description
D12
SGXEN
D13
EXSG
0: Internal SSG (Sync Signal Generator) functions operate to generate FRO and HRO.
1: Internal SSG functions are stopped, and the FRO and HRO pulses are fixed to low.
Note that the STB setting has priority. Set SGXEN to "1" in the case of input of a CXD2460R
sync signal from the outside.
0: Normal operation
1: XSGA and XSGB are output from the HRO and FRO pins.
Note that the output pulse amplitude is VSS to VDDa.
These bits select the pulse output from the ID pin.
D15
D14
to
D15
D14
IDSEL
0
1
0
ID pulse output
WEN pulse output
1
XSUB pulse output
ID pulse output
XSUB: Inverted SUB pulse output at the amplitude of VSS to VDDa
D16
VTXEN
0: VT (readout clock) is added to V2A, V2B and V3 as normal.
1: VT is not added to V2A, V2B and V3.
During readout, only the modulation necessary for readout is performed.
Note that this setting has priority over mode control data NSG (D14).
0: Checksum is not performed and the checksum data is invalid. (However, dummy data must be
set in the CHKSUM register.)
CHKSUM 1: Checksum is performed. This data is reflected even if the checksum results are NG.
D17
D18
STATUS
0: The EXP pulse is output from the EXP pin.
1: High is indicated if the checksum results from the EXP pin are OK, and low if the results are NG.
This pulse is output at the rise of SEN, and reset high again at the fall of SEN. This pulse has
priority over mode control data EXP.
D19
to
Input "0".
D22
These bits set the high-speed sweep period (unit: H) in FS mode.
D23
to
D29
FVFS
MSB
D29
LSB
D28
D27
D26
D25
D24
D23
The high-speed sweep is perfomed for 8 lines for every 1H when FINE = 1, and 20 lines for every
1H when FINE = 0.
– 18 –
CXD2460R
Detailed description
D30
XVCK
0: Normal operation
1: V1, V2 and V3 are inverted and output as XV1, XV2 and XV3. The amplitude is from VL to VM.
D31
to
Invalid data
D39
CHKSUM
Detailed description
These are the checksum bits.
D40
to
D47
+)
MSB
D07
D15
D23
D31
D39
D47
D06
D14
D22
D30
D38
D46
D05
D13
D21
D29
D37
D45
D04
D12
D20
D28
D36
D44
D03 D02
D11 D10
D19 D18
D27 D26
D35 D34
D43 D42
LSB
D01 D00
D09 D08
D17 D16
D25 D24
D33 D32
D41 D40 → CHKSUM
If the total = 0, the checksum results are OK.
Serial data is loaded to the internal registers only when checksum is OK.
Data is not reflected to the registers if checksum is NG.
Also, when CHKSUM = 0, the checksum results are always OK and the data is reflected to the
registers.
– 19 –
CXD2460R
4. Shutter speed setting specifications when PS = H
When PS = H, the CXD2460R can be controlled without inputting serial data by using the SEN, SSK and SSI
pins.
Pin
When L
FHIGH
SEN (horizontal drive
frequency)
SSK
When H
Serial register FHIGH = 1.
Serial register FHIGH = 0.
Serial register FINE = 0 and the
FINE
(readout method) CXD2460R operates in DRAFT mode.
Serial register FINE = 1 and the
CXD2460R operates in FINE mode.
Number of SUB pulses when PS = H
SSK
SSI
HSHUT,
VSHUT
(exposure time)
L
H
L
251
201
1052
1002
H
235
134
1034
935
SEN
Upper number: When SSI = H (1/250)
Lower number: When SSI = L (1/60)
Other registers hold the value input when PS = L, and assume the status indicated by STB when the RST
pulse is input.
– 20 –
CXD2460R
5. Reflection position of each data
Each serial data is reflected at the timing shown in the table below. The reflection position is the same when
PS = H. When using the low-speed electronic shutter, the data is not reflected at FR where XSG is not
generated (a readout pulse is not added to V2A).
Table 5-1. Serial data reflection timing
Data
Reflection position
Mode control data (STB)
SEN rise
Mode control data (EXPXEN)
XSGA pulse rise
HRI∗1 fall just before XSGA pulse generation
Mode control data (other than STB and EXPXEN)
HRI∗2 fall just after XSGA pulse generation
HRI∗1 fall just before XSGA pulse generation
Electronic shutter control data
High-speed phase adjustment data
System setting data (SGXEN)
SEN rise
HRI∗2 fall just before XSGA pulse generation
System setting data (other than SGXEN)
∗1 For FS mode, 7HRI later from FRI fall.
∗2 For FS mode, 8HRI later from FRI fall.
6. RST pulse
Setting Pin 30 to low resets the system. The serial data values after reset are as shown in the "Serial data"
table.
Also, some internal circuits stop operating when RST = L. For a description of the pin status when RST = L,
see the "Pin status during operation control" table given in the detailed description of STB under "3. Serial data
and description of functions".
7. DSGAT
DSGAT is ON when low and the CXD2460R is set to sleep mode as with SLP of STB.
Note that control is applied when either or both of DSGAT and SLP are ON. Also, when STN is ON, the
CXD2460R is set to standby mode regardless of the DSGAT status.
8. EXP pulse
The EXP pulse indicates the exposure period.
The details are shown on the following pages.
– 21 –
CXD2460R
(1) HSHUT ≥ MAX
HSHUT value
1 to MAX
0
MAX
6 (76)
0
6 (76)
0
6 (76)
0
HRI
FRI
V2A
SUB
EXP
(2) HSHUT ≥ MAX (with low-speed electronic shutter)
HSHUT value
1 to MAX
0
6 (76)
0
MAX
6 (76)
0
0
6 (76)
HRI
FRI
Location where XSG is normally generated.
(However, this pulse is not actually generated.)
V2A
SUB
EXP
(3) 1 ≤ HSHUT < MAX
HSHUT value
1 to MAX
0
MAX
6 (76)
0
1 to MAX
6 (76)
0
0
6 (76)
HRI
FRI
V2A
SUB
EXP
Numbers in parentheses are for FS mode.
– 22 –
CXD2460R
(4) 1 ≤ HSHUT < MAX (with low-speed electronic shutter)
HSHUT value
1 to MAX (with low-speed electronic shutter)
1 to MAX
0
6 (76)
1 to MAX
0
MAX
6 (76)
0
0
6 (76)
HRI
FRI
V2A
SUB
EXP
(5) HSHUT = 0
HSHUT value
0
0
6 (76)
0
6 (76)
0
HRI
FRI
V2A
SUB
EXP
(6) HSHUT = 0 (with low-speed electronic shutter)
HSHUT value
1 to MAX
0
0 (with low-speed electronic shutter)
6 (76)
0
6 (76)
HRI
FRI
V2A
SUB
EXP
Numbers in parentheses are for FS mode.
– 23 –
– 24 –
Mode
OUT
ID
WEN
XCPDM
XCPOB
PBLK
XSUB
XV3
V2B
V2A
V1
HRI
FRI
Reset
(Chart B-3)
17
FINE mode
1 2 3 4 5 6 7 8 1 2 3 4 5 6
(Chart B-1)
1057
1040
0/1068
1
Chart A-1. FINE Mode (Vertical synchronization)
1 2 3 4 5 6 7
CXD2460R
0/1068
1
Mode
OUT
ID
WEN
XCPDM
XCPOB
PBLK
SUB
V3
V2B
V2A
V1
HRI
FRI
1017
1020
1025
1028
1033
1036
0/267
1
DRAFT mode
(Chart B-4)
5
(Chart B-2)
1
4
1
4
9
12
17
20
25
28
33
Chart A-2. DRAFT Mode (Vertical synchronization)
255
256
257
258
259
260
261
1
2
3
4
5
6
7
8
9
255
256
257
258
259
260
261
– 25 –
1017
1020
1025
1028
1033
1036
0/267
1
5
1
2
3
4
5
6
7
8
9
1
4
1
4
9
12
17
20
25
28
33
CXD2460R
– 26 –
Mode
OUT
ID
WEN
XCPDM
XCPOB
PBLK
SUB
V3
V2B
V2A
V1
HRI
FRI
5
0
FS mode
The number of SUB pulses is
specified by the serial data.
XSGB is not generated when FINE = 0
High when FINE = 1
Low when FINE = 0
0
Chart B-2 when FINE = 0 in this period
The number of sweeps is specified by the serial data
(20 × FVFS when FINE = 0, 8 × FVFS when FINE = 1).
Set by FVFS
The mode is switched at the point where XSG is normally generated.
FINE mode
The number of sweeps is fixed (20 × 69H).
(Charts B-3/4)
74
75
Chart A-3. FS Mode (Vertical synchronization)
CXD2460R
5
HRI
– 27 –
120
152
152
184
216
216
379
50
88
EXP
25
56
96
379
16
56
56
ID/WEN
XCPDM
XCPOB
SUB
H2
H1
V3
V2A/B
V1
MCK
PBLK
0/1790
Chart B-1. FINE Mode (Horizontal synchronization)
394
392
409
412
414
CXD2460R
HRI
– 28 –
84
84
98
98
112
112
126
126
140
140
152
154
154
168
168
182
182
196
196
216
210
210
224
224
238
238
252
252
266
266
280
280
294
294
308
308
322
322
336
336
350
350
364
364
378
378
379
50
70
70
EXP
25
56
56
56
ID/WEN
16
379
XCPDM
XCPOB
SUB
H2
H1
V3
V2A/B
V1
MCK
PBLK
0/1790
Chart B-2. DRAFT Mode (Horizontal synchronization)
394
392
409
412
414
CXD2460R
– 29 –
EXP
V3
V2A/V2B
V1
XSGB
XSGA
XV3
XV2A/XV2B
XV1
HRI
56
56
88
88
120
120
96
152
152
184
184
216
248
800 bits
216
248
800 bits
2 bits
802
800
802
50 bits
2 bits
51 bits
850
0/1790
Chart B-3. Readout Timing (FINE mode)
56
56
88
88
120
120
152
152
CXD2460R
0/1270
EXP
V2B
V3
V2A
V1
XSGB
XSGA
XV3
XV2A/B
XV1
HRI
0/1790
56
84
112
112
126
154
154
168
196
196
210
56
70
84
98
126
140
98
96
112
154
168
182
196
210
224
238
140
182
224
238
238
252
252
266
280
266
280
280
294
294
308
322
308
322
322
336
336
350
364
350
364
364
378
378
392
392
Chart B-4. Readout Timing (DRAFT mode)
70
70
– 30 –
2 bits
800
800
802
802
850
850
936
922
50 bits
950
964
992
978
0/1790
71
57
71
85
70
84
99
113
113
56
98
112
127
126
141
155
155
154
169
197
168
183
197
196
211
210
225
140
182
224
CXD2460R
– 31 –
ID/WEN
XCPDM
XCPOB
SUB
H2
H1
V3
V2A/B
V1
MCK
PBLK
HRI
56
56
1
216
184
248
152 216
120
152
96
88
56
56
25 50
0/1790
312
280
344
2
379
536
504
472
394 409
392
392
408
376
440
412
3
600
568
632
4
728
696
664
Chart B-5. FS Mode: V clock continuous drive (FINE = 1)
792
760
824
888
856
920
5
984
952
1080
1176
7
1272
1368
8
1464
1560
1528
1496
1432
1400
1336
1304
1240
1208
1144
1112
1048
1016
6
0/1790
25 50
56
56
88
56
56
120
152
184
CXD2460R
– 32 –
ID/WEN
XCPDM
XCPOB
SUB
H2
H1
V3
V2A/B
V1
MCK
PBLK
HRI
56
56
70
56
96
98
2
182
224
3
266
308
4
350
364
378
1
84
392
140
154
168
196
210
392
392
406
412
434
5
420
476
6
518
560
7
602
644
Chart B-6. FS Mode: V clock continuous drive (FINE = 0)
0/1790
25
50
56
112
120
152
216
238
252
280
294
322
336
379
394
409
448
462
490
504
532
546
574
588
616
630
658
8
672
686
700
714
728
742
9
756
770
784
798
812
826
10
840
854
868
882
896
910
11
924
938
952
966
980
994
12
1008
1022
1036
1050
1064
1078
13
1092
1106
1120
1134
1148
1162
14
1176
1190
1204
1218
1232
1246
15
1260
1274
1288
1302
1316
1330
16
1344
1358
1372
1386
1400
1414
17
1428
1442
1456
1470
1484
1498
18
1512
1526
1540
1554
1568
1582
19
1596
1610
1624
1638
1652
1666
1680
20
1694
1708
1722
0/1790
25
50
56
56
56
70
84
56
98
112
126
140
154
CXD2460R
CXD2460R
Logical Phase
2MCK
MCK
H1
H2
RG
XSHP
XSHD
XRS
ADCLK
– 33 –
CXD2460R
Application Circuit
DRVOUT
VRT
VRB
A/D
CXD2311AR
XSHP
XSHD
XRS
XCPOB
XCPDM
PBLK
2MCK
MCK
ID
CCDOUT
HRO
FRO
HRI
FRI
Timing Generator
CXD2460R
RG
H1
H2
V1
V2A
V2B
V3
SUB
Controller
PS
+3.3V TEST2
OSCI
CKI
SEN
SSK
SSI
RST
EXP
OSCO
CCD Image
Sensor
ICX205AK
Signal Processor
Block
ADCLK
TEST1
CDS/AGC
CXA2006Q
D0 to D9
For making FR and HR outside the CXD2460R, configure a circuit that counts MCK. (Using 2MCK, CKO, etc.
is not recommended.) Also, set system setting data, SGXEN (D12) to "1" and stop a built-in SSG.
Use crystal oscillator (fundamental wave) as base oscillation. Be sure to input duty 50% pulse when crystal
oscillator is used.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 34 –
CXD2460R
Notes on Turning Power ON
To avoid setting VSUB pin of the CCD image sensor negative potential, the former two power supplies should
be raised by the following order among three power supplies, VL and VH.
VH
t1
20%
0V
20%
VL
t2
t2 ≥ t1
– 35 –
CXD2460R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
A
13
48
0.5 ± 0.2
(8.0)
24
37
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
0° to 10°
S
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER/PALLADIUM
PLATING
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 36 –