CXD2437TQ Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2437TQ is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features • External trigger function • Electronic shutter function • Supports non-interlaced operation • 12 frames/s. Double-speed readout (24 frames/s) is also possible by mixing two vertical pixels. • Base oscillation 40.490496MHz Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX085AK, ICX085AL 64 pin TQFP (Plastic) Absolute Maximum Ratings Vss – 0.5 to +7.0 • Supply voltage VDD • Input voltage VI Vss – 0.5 to VDD + 0.5 • Output voltage VO Vss – 0.5 to VDD + 0.5 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 V V V °C °C Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 • Operating temperature Topr –20 to +75 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96319A95-PS HD XGRST VD STDBY ESG XCPOB PBLK XCPDM ID WEN BUSY Block Diagram TRIG CXD2437TQ 48 47 46 36 35 34 59 58 57 56 62 61 RG 27 XH1 25 XH2 26 6 STRB 7 DCLK 8 DATA 5 TEST1 REGISTER XSHP1 30 XSHD1 31 XRS1 32 TG PULSE GENERATOR XSHP2 38 DECODE 12 TEST2 XSHD2 39 15 TEST3 XRS2 40 COUNTER 16 TEST4 XV1 23 XV2 22 19 GATE XSUB XV3 21 10 XSG 18 20 1/2 CLD1 52 CLD2 49 28 CL 51 33 42 CKO 53 INT 54 4 63 9 24 29 37 41 50 55 60 VSS FSE 3 SMDE RM OSCO CKI 11 13 14 2 OSCI 1 64 VDD XCPOB XCPDM PBLK VSS XSHP2 XSHD2 XRS2 VSS VDD NC NC NC ID WEN BUSY Pin Configuration (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 XRS1 CLD2 49 VSS 50 31 XSHD1 CL 51 30 XSHP1 CLD1 52 29 VSS CKO 53 28 VDD VDD 54 27 RG VSS 55 26 XH2 XGRST 56 25 XH1 STDBY 57 24 VSS TRIG 58 23 XV1 ESG 59 22 XV2 VSS 60 21 XV3 HD 61 20 VDD VD 62 19 XSUB –2– STRB DCLK TEST4 TEST1 9 10 11 12 13 14 15 16 TEST3 INT 8 SMDE 7 FSE 6 TEST2 5 RM 4 VDD 3 VSS 2 DATA 1 VSS 17 CH OSCI 18 XSG CKI 64 OSCO VDD 63 VDD CXD2437TQ Pin Description Pin No. Symbol I/O Description 1 OSCO O Inverter output for oscillation. 2 OSCI I Inverter input for oscillation. 3 VSS — 4 INT I Switching for base oscillation input (with pull-up resistor). High: Oscillation provided by the internal oscillation cell, Low: CKI input valid 5 TEST1 I Test (with pull-up resistor). Fix to high. 6 STRB I Shutter speed setting (with pull-up resistor). 7 DCLK I Shutter speed setting (with pull-up resistor). 8 DATA I Shutter speed setting (with pull-up resistor). 9 VSS — GND 10 VDD — Power supply. 11 RM I Switching for frame rate (with pull-up resistor). High: Normal readout mode, Low: Double-speed readout mode 12 TEST2 I Test (with pull-up resistor). Fix to high. 13 FSE I Switching for external trigger discharge operation (with pull-up resistor). High: High-speed discharge, Low: No high-speed discharge 14 SMDE I Switching for readout timing (with pull-up resistor). High: ESG setting invalid, Low: ESG input valid 15 TEST3 I Test (with pull-up resistor). Fix to high. 16 TEST4 I Test (with pull-up resistor). Fix to high. 17 CH — Switching for color separated pulse output (with pull-up resistor). High: Normal pulse output mode, Low: Color separated pulse output mode 18 XSG O Sensor charge readout pulse output. 19 XSUB O CCD discharge pulse output. 20 VDD — Power supply. 21 XV3 O Clock output for vertical CCD drive. 22 XV2 O Clock output for vertical CCD drive. 23 XV1 O Clock output for vertical CCD drive. 24 VSS — GND 25 XH1 O Clock output for horizontal CCD drive. 26 XH2 O Clock output for horizontal CCD drive. 27 RG O Reset gate pulse output. 28 VDD — Power supply. 29 VSS — GND 30 XSHP1 O Sample-and-hold pulse output. 31 XSHD1 O Sample-and-hold pulse output. 32 XRS1 O Sample-and-hold pulse output. 33 VDD — Power supply. 34 XCPOB O Clamp pulse output. GND –3– CXD2437TQ Pin No. Symbol I/O Description 35 XCPDM O Clamp pulse output. 36 PBLK O Blanking cleaning pulse output. 37 VSS — GND 38 XSHP2 O Sample-and-hold pulse output. 39 XSHD2 O Sample-and-hold pulse output. 40 XRS2 O Sample-and-hold pulse output. 41 VSS — GND 42 VDD — Power supply. 43 NC 44 NC 45 NC 46 ID O Line identification output. 47 WEN O Write enable output. 48 BUSY O Trigger mode flag. 49 CLD2 O AD conversion pulse output. 50 VSS — GND 51 CL O Clock output (1616fH). 52 CLD1 O AD conversion pulse output. 53 CKO O Clock output (3232fH). 54 VDD — Power supply. 55 VSS — GND 56 XGRST I Resets all internal FF. Low: Reset (with pull-up resistor). Always input one reset pulse after power–on. 57 STDBY I Standby (with pull-up resistor). High: Normal, Low: Internal clock supply stopped 58 TRIG I External trigger input (with pull-up resistor). 59 ESG I External readout input (with pull-up resistor). 60 VSS — 61 HD I Horizontal sync signal input. 62 VD I Vertical sync signal input. 63 VDD — 64 CKI I GND Power supply. Clock input (valid when INT = low). –4– CXD2437TQ Electrical Characteristics 1. DC Characteristics (VDD = 4.75 to 5.25V, Topr = –20 to +75°C) Item Symbol Conditions Min. Typ. Max. Unit 5.0 5.25 V Supply voltage VDD 4.75 Input voltage 1 (Input pins other than those listed below) VIH1 0.7VDD Input voltage 2 (Pin 2) VIH2 Output voltage 1 (Output pins other than those listed below) VOH1 IOH = –2.5mA VOL1 IOL = 4.5mA Output voltage 2 (Pins 30, 31, 32, 38, 39, 40, 49, 51, 52 and 53) VOH2 IOH = –5.0mA VOL2 IOL = 9.0mA Output voltage 3 (Pins 25, 26 and 27) VOH3 IOH = –7.5mA VOL3 IOL = 13.5mA Output voltage 4 (Pin 1) VOH4 Feedback resistor RFB VIN = VSS or VDD 1M Pull-up resistor RPU VIL = 0V 50k 100k Ω Pull-down resistor RPD VIH = VDD 50k 100k Ω Current consumption IDD VDD = 5V 60 V VIL1 0.3VDD 0.7VDD V VIL2 0.3VDD VDD – 0.4 V V 0.4 VDD – 0.4 V V 0.4 VDD – 0.4 V V 0.4 VDD/2 V V VOL4 –5– V VDD/2 V Ω mA CXD2437TQ 2. AC Characteristics 1) Waveform characteristics of XH1, XH2 and RG 0.9VDD XH1 0.1VDD tFH1 tWH1 tRH1 tWH2 tFH2 0.9VDD XH2 0.1VDD tRH2 0.9VDD RG 0.1VDD tRRG tWRG tFRG (VDD = 5.0V, Topr = 25°C, load capacitance of XH1 and XH2 = 30pF, load capacitance of RG = 10pF) Symbol tRH1 tFH1 tWH1 tRH2 tFH2 tWH2 tRRG tFRG tWRG Definition Min. Typ. Max. Unit XH1 rise time 3 ns XH1 fall time 3 ns XH1 low level time 25 ns XH2 rise time 3 ns XH2 fall time 3 ns XH2 high level time 25 ns RG rise time 2 ns RG fall time 2 ns RG high level time 12 ns –6– CXD2437TQ 2) Phase characteristics of XH1, XH2, RG, XSHP, XSHD, XRS, CL, CLD and CKO tH1 XH1 0.5VDD 0.5VDD XH2 0.5VDD 0.5VDD tPD2 0.5VDD tPD4 XSHP 0.5VDD tPD1 tPD3 RG 0.5VDD tW1 tPD5 0.5VDD 0.5VDD tW2 XSHD 0.5VDD tPD6 0.5VDD tPD7 XRS 0.5VDD 0.5VDD tPD8 CLD 0.5VDD tPD9 0.5VDD tW3 tPD10 CL 0.5VDD 0.5VDD tW4 tW5 CKO 0.5VDD 0.5VDD tPD11 (VDD = 5.0V, Topr = 25°C, load capacitance of CL and CKO = 30pF, load capacitance of CLD, XSHP, XSHD, XRS and RG = 10pF) Symbol tH1 tPD1 tPD2 tPD3 tPD4 tPD5 tPD6 tPD7 tPD8 tPD9 tPD10 Definition Min. XH1 cycle Typ. Max. Unit 49.4 ns XH2 falling delay, activated by the rising edge of XH1 0 ns XH2 rising delay, activated by the falling edge of XH1 0 ns XH1 falling delay, activated by the rising edge of RG 4 ns XSHP falling delay, activated by the falling edge of RG 4.5 ns XSHP rising delay, activated by the rising edge of XH1 9 ns XH1 falling delay, activated by the rising edge of XSHD 3 ns CLD falling delay, activated by the falling edge of XSHD 23 ns CLD falling delay, activated by the rising edge of XRS 21.5 ns XRS falling delay, activated by the falling edge of CLD 9 ns 2.5 ns CL rising delay, activated by the falling edge of CLD –7– CXD2437TQ Symbol tPD11 tW1 tW2 tW3 tW4 tW5 Definition Min. Typ. Max. Unit CKO rising delay, activated by the falling (rising) edge of XH1 2.5 ns XSHP pulse width 21 ns XSHD pulse width 20 ns CLD pulse width 21 ns CL pulse width 25 ns 11.5 ns CKO pulse width 3) Phase conditions of HD, VD, TRIG and ESG CL 0.5VDD tSETUP HD, VD, TRIG, ESG tHOLD 0.5VDD 0.5VDD (VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF) Symbol tSETUP tHOLD Definition Min. Typ. Max. Unit HD, VD, TRIG and ESG setup time, activated by CL 6 ns HD, VD, TRIG and ESG hold time, activated by CL 6 ns 3) Phase conditions of HD, VD, TRIG and ESG tWRST XGRST 0.3VDD 0.3VDD (Within the recommended operating condition) Symbol tWRST Definition Min. XGRST pulse width 50 –8– Typ. Max. Unit ns CXD2437TQ 5) Phase characteristics of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID CL 0.5VDD 0.5VDD tPDCL1 XV1, XV2, XV3 0.5VDD tPDCL2 0.5VDD BUSY, WEN, ID tPDCL3 XSG, XSUB, PBLK, XCPDM, XCPOB 0.5VDD (VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF, load capacitance of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID = 10pF) Symbol Definition Min. Typ. Max. Unit tPDCL1 tPDCL2 XV1, XV2 and XV3 delay, activated by the falling edge of CL 20 30 ns BUSY, WEN and ID delay, activated by the rising edge of CL 20 35 ns tPDCL3 XSG, XSUB, PBLK, XCPDM and XCPOB delay, activated by the rising edge of CL 15 30 ns –9– CXD2437TQ Description of Functions 1. Progressive Scan CCD drive pulse generation • Combining this IC with a crystal oscillator generates a fundamental frequency of 40.49MHz. • CCD drive pulse generation is synchronized with the HD and VD inputs. • Setting the RM pin to low sets the frame rate to double-speed readout mode (24 frames/s). However, the CCD vertical resolution is halved. • fCL = 1616fHD, fHD = 1044fVD (normal readout mode: RM = high) • fCL = 1616fHD, fHD = 522fVD (double-speed readout mode: RM = low) • The various operations are performed by the TRIG and ESG inputs. (See the following items.) <Detection timing for VD, RM, TRIG and ESG> CL 1 65 68 HD XH1 Detection timing for VD, RM, TRIG and ESG After HD input is detected, VD, RM, TRIG and ESG are detected at the rising edge of the 65th CL pulse. However, the low level period for each pulse should be set to 1H or longer to prevent misoperation. 2. Electronic shutter <Shutter modes> The electronic shutter has the following four shutter modes. • Electronic shutter off: Exposure time is 1/12s (RM = high) or 1/24s (RM = low) • High-speed electronic shutter: Exposure time is shorter than 1/12s (RM = high) or 1/24s (RM = low) • Low-speed electronic shutter: Exposure time is longer than 1/12s (RM = high) or 1/24s (RM = low) <Shutter mode and speed setting methods> The shutter speed is set serially using the STRB, DCLK and DATA pins. The electronic shutter mode and the meanings of the numbers indicated by D0 to 10 vary according to the SMD1 and SMD2 settings of the internal register. STRB DCLK DATA D0 D1 D2 D3 D4 D5 D6 – 10 – D7 D8 D9 D10 SMD1 SMD2 CXD2437TQ SMD1 SMD2 Mode D0 to 10 H H Electronic shutter off (1/12s accumulation∗1) L H High-speed electronic shutter Number of exposed lines∗2 H L Low-speed electronic shutter Number of exposed frames∗3 L L Electronic shutter off (1/12s accumulation∗1) — — ∗1 When RM = high. 1/24s accumulation when RM = low. ∗2 Relationship between the number of exposed lines and the exposure time The relationship between the number of exposed lines and the exposure time is as follows. (Exposure time) = (Number of exposed lines) × (One horizontal scan period) + (Accumulation time for the readout lines) In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for the readout lines is the time from the rising edge of XSUB to the falling edge of XSG (510 bits). Also, the number of exposed lines should be set to greater than 1 but less than 1043. ∗3 The number of exposed frames should be set to greater than 1 but less than 120. During external trigger mode, the number of exposed frames should be set to greater than 2. Timing Chart STRB tWD tSDS tWS DCLK tSDD tHDD DATA AC characteristics for serial input Definition Symbol tSDD tHDD tSDS tWS tWD Min. Max. Unit DATA setup time, activated by the rising edge of DCLK 10 — ns DATA hold time, activated by the rising edge of DCLK 10 — ns DCLK setup time, activated by the falling edge of STRB 30 — ns STRB pulse width 82 — ns DCLK pulse width 82 — ns – 11 – CXD2437TQ 3. External trigger mode External trigger mode starts exposure in sync with the external trigger input. No special pins are required to set this mode. Note that during external trigger mode, normal readout mode results regardless of the RM status. The IC prepares to shift to external trigger mode with the rising edge of the TRIG pin.∗1 The timing to shift to external trigger mode varies according to the mode setting. (See the table.) The BUSY pin maintains high status during external trigger mode. Whether or not to discharge the vertical CCD charge is set by FSE just after shifting to external trigger mode. ∗1 See the detection timing for VD, TRIG and ESG. Mode settings during external trigger SMD1 SMD2 Description of operation L L Trigger input is not accepted. Fix SMDE to high. L H The IC is shifted to external trigger mode by HD, exposure is finished after the set time, and XSG is output.∗2 H L The IC is shifted to external trigger mode by VD and exposure is finished in sync with VD after the set time.∗2 H H Trigger input is not accepted. Fix SMDE to high ∗2 The exposure time setting method is the same as the exposure time setting for the electronic shutter. <FSE and discharge operation> During external trigger mode, the previously exposed signal charge sometimes remains in the vertical CCD when exposure finishes. In this case, the image shot with external trigger mode is output overlapped with the previously shot image. Setting FSE to high performs discharge operation for signal charges remaining in the vertical CCD after trigger input. Discharge operation is not performed when FSE is low. This setting is only valid when using the highspeed shutter. <Finishing the exposure period with ESG> During external trigger mode, exposure can be finished in sync with the falling edge of ESG.∗3 If SMDE is set to low, the XSG pulse is output regardless of the electronic shutter setting, when the falling edge of ESG is detected. ESG should be fixed to high status at all times other than during external trigger mode. ∗3 See the detection timing for VD, TRIG and ESG. <Signal after external trigger mode> After high-speed external trigger mode is finished, the exposure time differs from that performed by the electronic shutter setting. This is because the start and finish of external trigger mode are not synchronized to VD input. 4. Internal logic stop (standby mode) When the STDBY pin is set to low, clock supply is stopped to a part of the internal logic. However, output from the oscillation cell (OSCI and OSCO pins) as well as the CL and CKO pins does not stop. The status of each output pin when STDBY is low is shown below. High: XSUB, XSG Low: RG, XH1, XH2, XV1, XV2, XV3, XSHP, XSHD, XRS, XCPOB, XCPDM, PBLK, ID, WEN, BUSY, CLD Not stopped: OSCO, CL, CKO – 12 – CXD2437TQ 5. Color separated pulse output mode • CDS/AGC can be supported to the system which performs with 2-channel by setting CH pin to low. When using CH pin at high, leave XSHP2, XSHD2, XRS2 and CLD2 pins open, respectivery. • XSHP, XSHD, XRS and CLD pins operate as shown in the figure below. Note) XSHP = XSHP1 and XSHP2, XSHD = XSHD1 and XSHD2 XRS = XRS1 and XRS2, CLD = CLD1 and CLD2 High-speed pulse when CH = low XH1 and 2 stop. XH1 and 2 operations start. R and Gr lines when ID = high XH1 XH2 RG ID = H XSHP1 XSHD1 XRS1 CLD1 XSHP2 XSHD2 XRS2 CLD2 ID = L Gb and B lines when ID = low XSHP1 XSHD1 XRS1 CLD1 XSHP2 XSHD2 XRS2 CLD2 – 13 – CXD2437TQ 6. Mode settings 6-1. VD input-related BUSY SMD1 SMD2 SMDE L H X Invalid L Exposure is started from the first VD input. H Readout operation or the number of accumulated frames is counted. H L H L L H H H L L VD input X Readout operation is performed. Notes) 1. SMD1 and SMD2 indicate the corresponding internal register values. 2. See "2. Electronic shutter". 6-2. TRIG and ESG input-related BUSY SMDE Discharge period∗1 H X ESG Prohibited∗5 H Exposure period Signal output period L L After TRIG input∗2,∗3 Prohibited X H Before TRIG input ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 TRIG∗4 L IC shifted to external trigger mode∗3 H L Readout operation∗5 Prohibited∗5 Prohibited∗6 Prohibited Only when FSE is high. Valid only during low-speed shutter. See "3. External trigger mode". Do not re-input the TRIG pulse until BUSY goes low. ESG input is valid only one time after TRIG input. Do not input ESG two times or more. Lock ESG to high status when BUSY is low. – 14 – CXD2437TQ 6-3. List of Timing Charts SMD1 SMD2 RM H L X X X Timing chart Vertical/ Horizontal L Chart-1 Vertical X Chart-2 L Chart-3 FSE SMDE BUSY X X X Horizontal Normal readout Vertical Horizontal Double-speed readout Chart-5 Horizontal Readout operation Vertical Shifting from normal readout to double-speed readout H→L Chart-7 Vertical Shifting from double-speed readout to normal readout H Chart-8 Vertical During external trigger input, discharge Chart-9 Vertical During external trigger input, discharge, double-speed L H X H L H H L H H L L H Double-speed readout Chart-4 L H Normal readout Chart-6 L→H L Operation L H Chart-10 Horizontal During external trigger input, (discharge operation) Chart-11 Vertical During external trigger input, no discharge Chart-12 Vertical During external trigger input, no discharge, double-speed Chart-13 Vertical During external trigger input, low-speed shutter Chart-14 Vertical During external trigger input, low-speed shutter, double-speed Chart-15 Vertical During external trigger input, ESG X H L – 15 – Chart-1 – 16 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 OUT HD VD 3 1 2 3 1 2 3 4 5 6 7 8 6 1 Normal Operation: Vertical synchronization 1036 1037 See "2. Electronic shutter" for the number of XSUB pulses. 1030 CXD2437TQ 1 XV3 – 17 – 1 1 XCPOB XCPDM BUSY WEN ID 1 PBLK XRS XSHD XSHP RG XH2 XH1 1 1 1 XV2 XSG (= High) XSUB 1 1616 1 XV1 CL HD 0 22 59 67 68 87 106 125 Normal Operation: Horizontal synchronization 68 Chart-2 144 163 234 286 276 306 321 322 CXD2437TQ 300 Chart-3 – 18 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 OUT HD VD 4 1 2 1 3 2 4 6 8 2 1 3 5 7 See "2. Electronic shutter" for the number of XSUB pulses. 1030 1029 519 520 Normal Operation, Double-speed Mode (RM = low): Vertical synchronization CXD2437TQ 1 1 1 1 XV2 XV3 XSG (= High) XSUB – 19 – 1 1 XCPOB XCPDM BUSY WEN ID 1 PBLK XRS XSHD XSHP RG XH2 XH1 1 1616 1 XV1 CL HD 0 22 59 67 68 87 106 125 144 163 182 201 220 234 239 Normal Operation, Double-speed Mode (RM = low): Horizontal synchronization 68 Chart-4 258 286 276 277 306 321 322 CXD2437TQ 300 – 20 – PBLK XV3 XV2 XV1 XSG Double-speed readout PBLK XV3 XV2 XV1 XSG Normal readout CL HD 1 1 1 1 1 1 1 1 1 1 1 67 106 163 220 258 239 201 182 144 125 87 68 67 144 106 87 68 125 Readout Operation: Horizontal synchronization 68 Chart-5 684 684 786 786 868 868 1 1 1 1 1 1 1 1 1 1 68 106 163 220 277 258 239 201 182 144 125 87 68 163 144 125 106 87 68 322 322 CXD2437TQ – 21 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 OUT HD VD RM RM is reflected from the next VD. 2 1 3 5 7 1 3 2 4 6 8 1 2 Switching from Normal Mode (RM = high) to Double-speed Mode (RM = low) 4 Chart-6 See "2. Electronic shutter" for the number of XSUB pulses. CXD2437TQ – 22 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 OUT HD VD RM RM is reflected from the next VD. 1 2 3 1 2 3 4 5 6 7 8 3 1 Switching from Double-speed Mode (RM = low) to Normal Mode (RM = high) 6 Chart-7 See "2. Electronic shutter" for the number of XSUB pulses. CXD2437TQ – 23 – XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD BUSY WEN ID 76 1 5 The number of XSUB pulses here conforms to normal operation. See "2. Electronic shutter" for the XSG output position. 1 2 31 2 3 4 5 6 7 8 This VD is ignored. 1 TRIG 1037 9 1 1 2 31 2 3 4 5 6 7 External Trigger Mode: High-speed electronic shutter, discharge, normal readout (FSE = high, SMDE = high, RM = high) XCPDM Chart-8 CXD2437TQ – 24 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD The number of XSUB pulses here conforms to normal operation. See "2. Electronic shutter" for the XSG output position. 1 2 31 2 3 4 5 6 7 8 This VD is ignored. 1 TRIG 76 1 6 9 1 1 3 2 4 6 8 2 1 3 5 7 External Trigger Mode: High-speed electronic shutter, discharge, double-speed mode (FSE = high, SMDE = high, RM = low) 1037 Chart-9 CXD2437TQ 1 1 1 1 XV2 XV3 XSG (= High) XSUB – 25 – 1 1 XCPOB XCPDM BUSY WEN ID 1 PBLK XRS XSHD XSHP RG XH2 XH1 1 1616 1 XV1 CL HD 0 22 59 67 68 68 87 106 1 125 144 163 182 201 220 239 234 2 258 3 286 276 277 (This XV1 to XV3 operation is repeated up to 1045 times.) External Trigger Mode: High-speed electronic shutter, when discharge starts (FSE = high) 298 Chart-10 CXD2437TQ – 26 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD The number of XSUB pulses here conforms to normal operation. See "2. Electronic shutter" for the XSG output position. 1 2 3 1 2 3 4 5 6 7 8 This VD is ignored. 1 TRIG 6 1 2 3 12 34 5 6 7 External Trigger Mode: High-speed electronic shutter, no discharge (FSE = low, SMDE = high) 1037 Chart-11 CXD2437TQ – 27 – XSG XV3 XV2 XV1 RG OUT HD VD BUSY WEN ID XCPDM XCPOB PBLK 6 The number of XSUB pulses here conforms to normal operation. See "2. Electronic shutter" for the XSG output position. 1 2 3 12 3 4 5 6 7 8 This VD is ignored. 1 TRIG 1037 1 3 2 4 6 8 2 1 3 5 7 External Trigger Mode: High-speed electronic shutter, no discharge, double-speed mode (FSE = low, SMDE = high, RM = low) XSUB Chart-12 CXD2437TQ – 28 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD TRIG External Trigger Mode: Low-speed electronic shutter (SMDE = high, RM = high) 6 1 1 See "2. Electronic shutter" for the time from the XSG output after TRIG input until the next XSG output. 1 2 3 12 34 5 6 7 8 1037 Chart-13 6 1 2 31 2 3 4 5 6 7 8 CXD2437TQ 1037 – 29 – BUSY WEN ID XCPDM XCPOB PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD TRIG External Trigger Mode: Low-speed electronic shutter, double-speed mode (SMDE = high, RM = low) 6 1 2 3 1 2 3 4 5 6 6 1 1 See "2. Electronic shutter" for the time from the XSG output after TRIG input until the next XSG output. 1 2 3 1 2 3 4 5 6 1037 Chart-14 2 1 3 5 7 4 1 3 2 4 6 8 CXD2437TQ 1 – 30 – PBLK XSUB XSG XV3 XV2 XV1 RG OUT HD VD ESG BUSY WEN ID XCPDM This VD is ignored. 1 TRIG 76 1 1037 The number of XSUB pulses here conforms to normal operation. 1 2 31 2 3 4 5 6 7 8 6 9 1 Example during ESG Input: Discharge, normal readout (FSE = high, RMDE = low, RM = high) XCPOB Chart-15 1 2 31 2 3 4 5 6 7 CXD2437TQ Application Circuit 1 4 5 6 – 31 – 20 19 18 17 61 62 63 64 CXD1268M × 2 CXD1267AN 1/6 74AC04 × 3 1000p +15V ICX085AL CDS/AGC A/D Converter Digital Out Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 21 60 9 10 11 12 13 14 15 16 22 8 23 58 59 7 25 56 24 26 55 57 28 27 53 54 3 29 52 2 30 51 1 31 50 CXD2437TQ 32 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +5V CXD2437TQ Application Circuit 2 4 5 6 – 32 – 8 9 10 11 12 13 14 15 16 18 17 62 63 64 +15V CXD1268M × 2 CXD1267AN 74AC04 × 3 1000p A/D Converter CDS/AGC ICX085AK/AL A/D Converter CDS/AGC Digital Out Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 20 19 60 61 22 21 59 23 58 7 25 56 24 26 55 57 28 27 53 54 3 29 52 2 30 51 1 31 50 CXD2437TQ 32 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +5V CXD2437TQ CXD2437TQ Package Outline Unit: mm 64PIN TQFP (PLASTIC) 12.0 ± 0.4 1.27 MAX 10.0 ± 0.2 1.0 ± 0.1 48 33 0.1 49 32 64 17 A 16 1 0.5 0.2 ± 0.1 0.08 0.125 ± 0.05 M 1.0 ± 0.2 0.5 ± 0.2 0.1 ± 0.1 + 7° 3° – 3° PACKAGE STRUCTURE DETAIL A PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE TQFP-64P-L071 LEAD TREATMENT EIAJ CODE TQFP064-P-1010-AN LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.3g JEDEC CODE – 33 –