CXD2457R Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2457R is an IC developed to generate the timing pulses required by Progressive Scan CCD image sensors as well as signal processing circuits. Features • Electronic shutter function • Supports non-interlaced operation • Base oscillation frequency 30.0MHz • Horizontal drive frequency switchable between 15/10/5MHz • Switchable between FINE (Progressive Scan) mode or DRAFT (high-frame rate readout) mode • Vertical driver Applications Progressive Scan CCD cameras 48 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDDa, VDDb, VDDc, VDDd Vss – 0.5 to Vss + 7.0 • Supply voltage VSS VL – 0.5 to VL + 10.0 • Supply voltage VH VL – 0.5 to VL + 26.0 • Supply voltage VM VL – 0.5 to VL + 26.0 • Input voltage VI Vss – 0.5 to VDD + 0.5 V V V V V V • Output voltage VO Vss – 0.5 to VDD + 0.5 • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Structure Silicon gate CMOS IC Applicable CCD Image Sensor ICX204AK Recommended Operating Conditions • Supply voltage 1 VDDa, VDDb, VDDc 3.0 to 3.6 • Supply voltage 2 VDDd 3.0 to 3.6 • Supply voltage 3 VH 14.25 to 15.75 • Supply voltage 4 VL –9.0 to –5.0 • Supply voltage 5 VM 0 • Operating temperature Topr –20 to +75 V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98113A86-PS CXD2457R H2 RG XSHD XSHP XRS VM V1 V3 V2A VH V2B SUB VL 9 18 17 19 39 40 41 42 43 44 45 46 5 V-Driver XSUB XSGA 3 XSGB 4 XV2 CKI 13 XV3 OSCO 12 XV1 OSCI H1 Block Diagram 15 XCPDM CKO 1 1/3 , 21 PBLK 2MCK 27 1/2 22 XCPOB Pulse Generator 32 ID 1/3 33 EXP 28 TEST2 MCK 25 ADCLK 23 VDD0 6 AVD0 8 AVD2 16 47 DSGAT SSG AVD1 14 48 PS 1/1270 VDD1 26 VSS0 2 1/792 1/264 29 SEN VSS1 10 Register VSS2 11 31 SSI VSS3 20 7 24 RST 38 FRI HRI FRO HRO 37 TEST1 VSS4 36 35 34 30 SSK XSGA and XSGB are readout pulses that use V2A and V2B, respectively, as the VH value. –2– CXD2457R VSS4 FRO HRO EXP ID SSI SSK SEN TEST2 2MCK VDD1 MCK Pin Configuration (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 V3 41 20 VSS3 V2A 42 19 XRS VH 43 18 XSHD V2B 44 17 XSHP SUB 45 16 AVD2 VL 46 15 XCPDM DSGAT 47 14 AVD1 PS 48 13 H2 1 2 3 4 5 6 7 8 9 10 11 12 H1 21 PBLK VSS2 40 VSS1 V1 RG 22 XCPOB AVD0 39 TEST1 VM VDD0 23 ADCLK OSCI 38 OSCO FRI CKI 24 RST VSS0 37 CKO HRI The enclosed pins use separate power supplies. –3– CXD2457R Pin Description Pin No. Symbol I/O Description 1 CKO O Oscillator output. (30.0MHz) 2 Vss0 — GND 3 CKI I Oscillator input. (30.0MHz) 4 OSCO O Inverter output for oscillation. (30.0MHz) 5 OSCI I Inverter input for oscillation. (30.0MHz) 6 VDD0 — 7 TEST1 I 8 AVD0 — Power supply. 9 RG O Reset gate pulse output. 10 Vss1 — GND 11 Vss2 — GND 12 H1 O Clock output for horizontal CCD drive. 13 H2 O Clock output for horizontal CCD drive. 14 AVD1 — Power supply. 15 XCPDM O Clamp pulse. 16 AVD2 — Power supply. 17 XSHP O Sample-and-hold pulse. 18 XSHD O Sample-and-hold pulse. 19 XRS O Sample-and-hold pulse. 20 VSS3 — GND 21 PBLK O Blanking cleaning pulse. 22 XCPOB O Clamp pulse. 23 ADCLK O Clock output for AD conversion. 24 RST I Reset (Low: Reset, High: Normal operation). Always input one reset pulse during power-on. 25 MCK O Clock output for digital circuit. 26 VDD1 — Power supply. 27 2MCK O Clock output for digital circuit. 28 TEST2 I Test. Fix to high. 29 SEN I PS = High: Drive frequency setting input. PS = Low: Serial setting strobe input. 30 SSK I PS = High: Readout method setting input. PS = Low: Serial setting clock input. 31 SSI I PS = High: Shutter speed setting input. PS = Low: Serial setting data input. 32 ID O Line identification signal output write enable pulse output or XSUB output. 33 EXP O Pulse output indicating exposure is underway or checksum result output. Power supply. Test. With pull-down resistor. Fix to low. –4– CXD2457R Pin No. Symbol I/O Description 34 HRO O Horizontal sync signal (HR) output or XSGB output. 35 FRO O Vertical sync signal (FR) output or XSGA output. 36 VSS4 — GND 37 HRI I Horizontal sync signal (HR) input. 38 FRI I Vertical sync signal (FR) input. 39 VM — GND (vertical clock driver GND). 40 V1 O Clock output for vertical CCD drive. 41 V3 O Clock output for vertical CCD drive. 42 V2A O Clock output for vertical CCD drive. 43 VH — 15V power supply (vertical clock driver power supply). 44 V2B O Clock output for vertical CCD drive. 45 SUB O CCD electric charge sweep pulse output. 46 VL — –7.5V power supply (vertical clock driver power supply). 47 DSGAT I Output stop (Same operation control as SLP when low). 48 PS I Parallel/serial switching for mode setting input method. (High: Parallel, Low: Serial) With pull-down resistor. –5– CXD2457R Electrical Characteristics DC Characteristics Item (Within the recommended operating conditions) Pins Symbol Conditions Min. Typ. Max. Unit Supply voltage 1 VDD0, VDD1, VDDa 3.0 3.3 3.6 V Supply voltage 2 AVD0 VDDb 3.0 3.3 3.6 V Supply voltage 3 AVD1 VDDc 3.0 3.3 3.6 V Supply voltage 4 AVD2 VDDd 3.0 3.3 3.6 V Supply voltage 5 VH VH 14.5 15.5 15.5 V Supply voltage 6 VM VM — 0.0 — V Supply voltage 7 VL VL –9.0 –5.0 V VIH1 0.7VDDa Input voltage 1 Input voltage 2 Input voltage 3 Output voltage 1 CKI 0.3VDDa VIH2 TEST1, PS 0.7VDDb VIL2 0.8VDDa VOH1 Feed current where IOH = –10.0mA VDDa – 0.8 VOL1 Pull-in current where IOL = 7.2mA VOH2 Feed current where IOH = –3.3mA VDDb – 0.8 VOL2 Pull-in current where IOL = 2.4mA VOH3 Feed current where IOH = –22.0mA VDDc – 0.8 VOL3 Pull-in current where IOL = 14.4mA VOH4 Feed current where IOH = –3.3mA VDDd – 0.8 VOL4 Pull-in current where IOL = 2.4mA CKO, MCK, 2MCK Output voltage 3 H1, H2 XCPDM, XSHP, Output voltage 4 XSHD, XRS, PBLK, XCPOB Feed current where IOH = –2.4mA VDDa – 0.8 VOH6 Feed current where IOH = –4.0mA VH – 0.25 VOL6 Pull-in current where IOL = 5.4mA VOM7 Feed current where IOH = –5.0mA VM – 0.25 VOL7 Pull-in current where IOL = 10.0mA Output voltage 6 SUB Output voltage 7 V1, V3 Pull-in current where IOL = 4.8mA VOM102 Pull-in current where IOL = 5.0mA VOL8 Feed current where IOH = –5.0mA VM – 0.25 VOL8 Pull-in current where IOL = 10.0mA –6– V V 0.4 V V 0.4 V V 0.4 V V 0.4 V V 0.4 V V VL + 0.25 V V VL + 0.25 VOM101 Feed current where IOH = –7.2mA VH – 0.25 Output voltage 8 V2A, V2B V V 0.2VDDa ID, EXP, HRO, VOH5 FRO VOL5 V V 0.3VDDa RST, TEST2, Vt + 1 SEN, SSK, SSI, HRI, FRI, DSGAT Vt – 1 Output voltage 2 RG Output voltage 5 VIL1 V V V VM + 0.25 V V VL + 0.25 V CXD2457R (Within the recommended operating conditions) Inverter I/O Characteristics for Oscillation Item Pins Logical Vth OSCI Input voltage OSCI Output voltage OSCO Symbol Conditions Min. LVth VIH 0.3VDDa Pull-in current where IOL = 6.0mA Feedback resistor OSCI, OSCO RFB VIN = VDDd or Vss Oscillator frequency OSCI, OSCO f Input voltage Symbol 500k Conditions Min. Typ. 5M Ω 50 MHz Max. V 0.3VDDa fmax 50MHz sine wave Unit V 0.7VDDa VIL VIN V VDDa/2 VIH Input amplification 2M VDDa/2 (Within the recommended operating conditions) LVth CKI V V 20 Base Oscillation Clock Input Characteristics Logical Vth V VIL VOL Unit V 0.7VDDd Feed current where IOH = –6.0mA VDDa/2 Pins Max. VDDa/2 VOH Item Typ. V Vp-p 0.3 ∗1 Input voltage is the input voltage characteristics for direct input from an external source. Input amplification is the input amplification characteristics for input through capacitor. Switching Characteristics Item Rise time Fall time Output noise voltage (VH = 15.0V, VM = GND, VL = –8.5V) Symbol Conditions Min. Typ. Max. Unit TTLM VL to VM 350 550 ns TTMH VM to VH 450 700 ns TTLH VL to VH 50 80 ns TTML VM to VL 250 400 ns TTHM VH to VM 300 450 ns TTHL VH to VL 50 80 ns VCLH 1.0 V VCLL 1.0 V VCMH 1.0 V VCML 1.0 V ∗1 The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. ∗2 For noise and latch-up countermeasures, be sure to connect a bypass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. –7– CXD2457R Switching Waveforms TTMH TTHM VH 90% 90% TTLM TTML 10% V2A (V2B) 10% VM 90% 90% 10% 10% TTLM VL TTML VM 90% 90% V1 (V3) 10% 10% VL TTHL TTLH VH 90% 90% VSUB 10% 10% VL Waveform Noise VCMH VCML VH VCLH VCLL VL Measurement Circuit C1 R1 R1 C2 C2 V1 V3 C1 C1 C2 V2A C2 V2B R1 R1 C1 R2 –8– R1: R2: C1: C2: 27Ω 5Ω 1500pF 3300pF CXD2457R AC Characteristics 1) AC characteristics between the serial interface clocks SSI 0.8VDDa 0.2VDDa 0.8VDDa SSK 0.2VDDa ts1 SEN th1 0.2VDDa ts3 0.8VDDa SEN ts2 th2 (Within the recommended operating conditions) Symbol Definition Min. Typ. Max. Unit ts1 th1 ts2 th2 ts3 SSI setup time, activated by the rising edge of SSK 20 ns SSI hold time, activated by the rising edge of SSK 20 ns SSK setup time, activated by the rising edge of SEN 20 ns SSK hold time, activated by the rising edge of SEN 20 ns SEN setup time, activated by the rising edge of SSK 20 ns fk SSK frequency 7.5 2) Serial interface clock internal loading characteristics V2A HRI 0.5VDDa 0.5VDDa 300ns 300ns Do not rise the SEN level in this time (300ns after the fall of HRI just before XSGA pulse generation to 300ns after the fall of HRI just after XSGA pulse generation) –9– MHZ CXD2457R 3) Output timing characteristics using DSGAT and RST twRST 0.5VDDa 0.5VDDa DSGAT, RST EXP, XCPDM, XCPOB PBLK, XSHP, XSHD, XRS, RG, H1, H2 0.5VDDa, b, c, d tpRST H1 and H2 load capacitance = 180pF EXP, XCPDM, PBLK, XSHP, XSHD, XRS and RG load capacitance = 10pF (Within the recommended operating conditions) Min. Definition Symbol tpRST Time until the above outputs reach the specified value after the fall of DSGAT and RST twRST RST and DSGAT pulse width Typ. Max. Unit 75 ns ns 10 4) FRI and HRI loading characteristics FRI, HRI 0.5VDDa 0.5VDDa tsSYNC 0.5VDDa MCK MCK load capacitance = 10pF Symbol tsSYNC thSYNC thSYNC (Within the recommended operating conditions) Definition Min. FRI and HRI setup time, activated by the rising edge of MCK 5 ns FRI and HRI hold time, activated by the rising edge of MCK 5 ns – 10 – Typ. Max. Unit CXD2457R 5) Output variation characteristics of ID, WEN, EXP, FRO and HRO MCK 0.5VDDa EXP, ID, WEN 0.5VDDa tpdEXP FRO, HRO 0.5VDDa tpdSYNCO EXP, ID and WEN load capacitance = 10pF Symbol (Within the recommended operating conditions) Definition Min. tpdEXP Time until the WEN, ID and EXP outputs change after the fall of MCK tpdSYNCO Time until the FRO and HRO outputs change after the fall of MCK – 11 – Typ. Max. Unit 0.5 8.5 ns 1.0 11.5 ns CXD2457R Description of Operation 1. Progressive Scan CCD drive pulse generation • Combining this IC with a crystal oscillator generates a fundamental frequency of 30.0MHz. • CCD drive pulse generation is synchronized with HRI and FRI. • The CCD drive method can be changed to various modes by inputting serial data or parallel data to the CXD2457R. • The various drive methods possessed by the CXD2457R are shown in the Timing Charts A-1 to 4 (V rate) and B-1 to 6 (H rate). 2. Serial data input method • All CXD2457R operations can be controlled via the serial interface. The serial data format is as follows. SSI 00 01 02 03 04 05 06 33 34 35 36 37 38 39 SSK SEN Serial data format Serial data Symbol Data Function When reset D00 to D07 CHIP Chip switching See D00 to D07 CHIP. All 0 D08 to D10 CTGRY Category switching See D08 to D10 CTGRY. All 0 D11 to D31 DATA Control data for each category The meaning of this CTGRY control data differs according to the category set by D08 to D10. See D11 to D31 DATA. All 0 D32 to D39 Checksum bits Checksum bits See D32 to D39 CHKSUM. All 0 – 12 – CXD2457R 3. Serial data and description of functions Detailed description D00 The serial interface data is loaded to the CXD2457R when D00 and D07 are 1. However, this assumes that D32 to D39 CHKSUM is satisfied. to D07 CHIP D07 D06 1 0 D05 D04 0 D03 0 0 D02 D01 0 D00 0 1 Function Loading to the CXD2457R This CTGRY data indicates the functions that the serial interface data controls. D08 to D10 CTGRY D10 D09 D08 0 0 0 Mode control data 0 1 0 Electronic shutter control data 0 1 1 High-speed phase adjustment data (Set all of D11 to D31 to 0.) 1 0 0 System setting data Function Input of values other than those listed above is prohibited. CTGRY: Mode control data Detailed description 0: Power saving drive mode 1: High-speed drive mode When FHIGH = 0, the clock input to CKI is immediately frequency divided by 1/3 and loaded internally. Mode switching timing (5 clocks after the fall of HRI just before XSG is generated) D11 FHIGH MCK Unstable Unstable CKI FHIGH = 1 FHIGH = 0 FHIGH = 1 The high-speed phases of H1, H2, RG, XSHP, XSHD, XRS, ADCLK and other pulses are always logically the same phase with respect to MCK. 0: DRAFT mode 1: FINE mode D12 FINE In FINE mode, image data is taken by the normal Progressive Scan method. In DRAFT mode, image data is taken by pulse elimination readout. This enables a frame rate three times that during FINE mode. The mode is switched at the fall of HRI just before XSGA. Note that the FRO output is also switched accordingly. (DRAFT mode: 264H, FINE mode: 792H) 0: Normal operation 1: Readout prohibited mode D13 NSG In readout prohibited mode, a readout pulse is not added to V2A and V2B (V2A or V2B takes a VH value). (V1, V2 and V3 are not modulated.) The mode is normally switched at the fall of HRI just before the position where the readout pulse is added. – 13 – CXD2457R Detailed description 0: Normal operation 1: FS mode In order to increase the frame rate, a certain portion of the captured image of CCD can be cut out by performing high-speed sweep. In FS mode, high-speed sweep is performed for the V registers of the entire image (period Z) after FRI input. Next, high-speed sweep is performed again for only the desired period (period X) after generating the XSGA pulse. Then, after performing normal V transfer and outputting the effective signal (period Y), high-speed sweep is performed for the entire image again by inputting FRI at the desired timing. This makes it possible to take only the desired portion in the V direction, thus effectively increasing the frame rate. Operation is fixed during period Z, with 22 lines swept every 1H and repeating over a 36H period. During period X, first XSGA is generated, then sweep operation starts. This period is set in serial data FVFS (system setting data: D21 to D26) in HRI units. Be sure to set FINE = 0 in this mode. D14 • When the frame rate is increased as the vertical effective signal Y line (example) FS X , , ,, , , , , , Sweep variable period (period X) Effective signal period (period Y) Y Sweep fixed period (period Z) Z Reset by FRI after normal transfer Timing chart FRI Z X Y V2A 36H (Fix) Set by FVFS D15 to Set to 0. D16 – 14 – 1068 CXD2457R Detailed description Operation control settings The operating mode control bits are loaded to the CXD2457R at the rise timing of the SEN input, and control is applied immediately. D18 D17 Symbol Control mode 0 0 CAM Normal operation mode 0 1 SLP Sleep mode (mode for the status where CCD drive is not required) 1 X STN Standby mode Pin status during operation control Symbol CAM SLP STN RST∗ Pin No. Symbol CAM SLP STN RST∗ 1 CKO ACT ACT ACT ACT 25 MCK ACT ACT ACT ACT 2 VSS0 — — — — 26 VDD1 — — — — 3 CKI ACT ACT ACT ACT 27 2MCK ACT ACT ACT ACT 4 OSCO ACT ACT ACT ACT 28 TEST2 — — — — 5 OSCI ACT ACT ACT ACT 29 SEN ACT ACT — — 6 VDD0 — — — — 30 SSK ACT ACT — — 7 TEST1 — — — — 31 SSI ACT ACT — — 8 AVD0 — — — — 32 ID ACT L L L 9 RG ACT L L L 33 EXP ACT L L L 10 VSS1 — — — — 34 HRO ACT ACT L L 11 VSS2 — — — — 35 FRO ACT ACT L L 12 H1 ACT L L L 36 VSS4 — — — — 13 H2 ACT L L L 37 HRI ACT ACT — — 14 AVD1 — — — — 38 FRI ACT ACT — — 15 XCPDM ACT L L L 39 VM — — — — 16 AVD2 — — — — 40 V1 ACT VM VM VM 17 XSHP ACT L L L 41 V3 ACT VM VM VM 18 XSHD ACT L L L 42 V2A ACT VH VH VH 19 XRS ACT L L L 43 VH — — — — 20 VSS3 — — — — 44 V2B ACT VH VH VH 21 PBLK ACT L L L 45 SUB ACT VH VH VH 22 XCPOB ACT L L L 46 VL — — — — 23 ADCLK ACT L L L 47 DSGAT ACT ACT L L 24 RST ACT ACT ACT ACT 48 PS ACT ACT ACT ACT Pin No. D17 to D18 STB ∗ See "6. RST pulse" for a detailed description of RST. Note) ACT indicates circuit operation, and L indicates "low" output level in the controlled status. For sleep mode or standby mode, stop supplying VH and VL power supplies with CCD image sensor. – 15 – CXD2457R Detailed description 0: The EXP pulse indicating the exposure period is generated. 1: The EXP pulse indicating the exposure period is not generated, and is constantly fixed to low. D19 EXPXEN D20 3MCK This bit is invalid when STATUS = 1. Note that the STB setting has priority. The data is reflected at the rise of XSGA. 0: 2MCK clock system 1: 3MCK clock system This bit switches how MCK is comprised from the clock selected by FHIGH. Note that the waveform is unstable for 5 clocks before and after switching. D21 to Invalid data D23 D24 to D28 VSHUT Low-speed electronic shutter setting. The value set here is the number of FR during which readout operation is not performed even if there is input. The setting range is from 0 to 31. When set to 0, readout operation is performed at the first VR. When FS = 1, this bit is invalid. MSB D28 D27 D26 D25 LSB Function D24 Number of FR during which readout operation is not performed D29 to Invalid data D31 CXD2457R clock system When using a 30MHz crystal Frame rate FHIGH 3MCK FINE Mode1 1 0 1 15MHz 30MHz 15Frame/s Mode2 1 1 0 10MHz 15MHz 30Frame/s Mode3 0 0 0 5MHz 10MHz 15Frame/s Mode4 1 0 0 15MHz 30MHz 45Frame/s Mode5 1 1 1 10MHz 15MHz 10Frame/s MCK frequency 2MCK pin output Note) Combinations of FHIGH, 3MCK and FINE other than those listed above are prohibited. – 16 – CXD2457R CTGRY: Electronic shutter control data Detailed description D11 to High-speed electronic shutter setting. The value set here is the number of SUB pulses from FR to the next FR. D20 MSB HSHUT D20 D19 D18 D17 D16 D15 D14 D13 D12 LSB Function D11 Number of SUB pulses setting D21 to Input 0. D31 High-speed and low-speed electronic shutter can be used together. Therefore, the exposure time is as follows: FR cycle × VSHUT + (fv – HSHUT) × HR cycle + 745/MCK frequency [Hz] = Exposure time [s] (fv: Number of HR in 1FR) – 17 – CXD2457R CTGRY: System setting data Detailed description D11 SGXEN 0: Internal SSG (Sync Signal Generator) functions operate to generate FRO and HRO. 1: Internal SSG functions are stopped, and the FRO and HRO pulses are fixed to low. Note that the STB setting has priority. When the sync signal is input from external CXD2457R, use it at SGXEN = 1. D12 0: Normal operation 1: XSGA and XSGB are output from the FRO and HRO pins. EXSG Note that the amplitude of the output pulses are VSS to VDDa. These bits select the pulse output from the ID pin. D14 D13 to D14 D13 IDSEL 0 1 0 ID pulse output WEN pulse output 1 XSUB pulse output ID pulse output XSUB: Inverted SUB pulse output at the amplitude of VSS to VDDa D15 VTXEN 0: VT (readout clock) is added to V2A, V2B and V3 as normal. 1: VT is not added to V2A, V2B and V3. During readout, only the modulation necessary for readout is performed. Note that this setting has priority over mode control data NSG (D13). 0: Checksum is not performed and the checksum data is invalid. (However, dummy data must be set in the CHKSUM register.) CHKSUM 1: Checksum is performed. This data is reflected even if the checksum results are NG. D16 D17 STATUS 0: The EXP pulse is output from the EXP pin. 1: High is indicated if the checksum results are OK, and low if the results are NG. This pulse is output at the rise of SEN, and reset high at the fall of SEN. This pulse has priority over mode control data EXP. D18 to Input 0. D20 D21 These bits set the high-speed sweep period (unit: H) in FS mode. to MSB D26 D26 FVFS LSB D25 D24 D23 D22 D21 The high-speed sweep is performed 22 times every 1H. – 18 – CXD2457R Detailed description D27 XVCK 0: Normal operation 1: V1, V2 and V3 are inverted and output as XV1, XV2 and XV3. The amplitude is from VL to VM. D28 to Invalid data D31 CHKSUM Detailed description These are the checksum bits. D32 to +) MSB D07 D15 D23 D31 D39 D06 D14 D22 D30 D38 D05 D13 D21 D29 D37 D04 D12 D20 D28 D36 D03 D02 D11 D10 D19 D18 D27 D26 D35 D34 D39 LSB D01 D00 D09 D08 D17 D16 D25 D24 D33 D32 → CHKSUM If the total = 0, the checksum results are OK. Serial data is loaded to the internal registers only when checksum is OK. Data is not reflected to the registers if checksum is NG. Also, when CHKSUM = 0, the checksum results are always OK and the data is reflected to the registers. – 19 – CXD2457R 4. Shutter speed setting specifications when PS = H When PS = H, the CXD2457R can be controlled without inputting serial data by using the SEN, SSK and SSI pins. Pin When L FHIGH SEN (horizontal CCD drive frequency) SSK When H Serial registers FHIGH and 3MCK = 0. Serial register FINE = 0 and the FINE (readout method) CXD2457R operates in DRAFT mode. Serial registers FHIGH = 1 and 3MCK = 0. Serial register FINE = 1 and the CXD2457R operates in FINE mode. Number of SUB pulses when PS = H SSK SSI HSHUT, VSHUT (exposure time) L H L 249 199 777 727 H 217 68 745 596 SEN Upper number: When SSI = H (1/250) Lower number: When SSI = L (1/60) Other registers hold the value input when PS = L, and assume the status indicated by STB when the RST pulse is input. – 20 – CXD2457R 5. Reflective position of each data Each serial data is reflected at the timing shown in the table below. The reflection position is the same when PS = H. When using the low-speed electronic shutter, the data is not reflected at FR where XSGA is not generated (a readout pulse is not added to V2A). Table 5-1. Serial data reflection timing Data Reflection position Mode control data (STB) SEN rise Mode control data (EXPXEN) XSGA pulse rise HRI∗1 fall just before XSGA pulse generation Mode control data (other than STB and EXPXEN) HRI∗2 fall just after XSGA pulse generation HRI∗1 fall just before XSGA pulse generation Electronic shutter control data High-speed phase adjustment data System setting data (SGXEN) SEN rise HRI∗1 fall just before XSGA pulse generation System setting data (other than SGXEN) ∗1 For FS mode, 7HRI later from FRI fall ∗2 For FS mode, 8HRI later from FRI fall 6. RST pulse Setting Pin 30 to low resets the system. The serial data values after reset are as shown in the "Serial data" table. Also, some internal circuits stop operating when RST = L. For a description of the pin status when RST = L, see the "Pin status during operation control" table given in the detailed description of STB under "3. Serial data and description of functions". 7. DSGAT DSGAT is ON when low and the CXD2457R is set to sleep mode as with SLP of STB. Note that control is applied when either or both of DSGAT and SLP are ON. Also, when STN is ON, the CXD2457R is set to standby mode regardless of the DSGAT status. 8. EXP pulse The EXP pulse indicates the exposure period. The details are shown on the following pages. – 21 – CXD2457R (1) HSHUT ≥ MAX value of HSHUT 1 to MAX 0 8 (42) 0 MAX 8 (42) 0 0 8 (42) HRI FRI V2A SUB EXP (2)HSHUT ≥ MAX (with low-speed erectronic shutter) value of HSHUT 1 to MAX 0 8 (42) 0 MAX 8 (42) 0 8 (42) 0 HRI FRI Location where XSG is normally generated. (However, this pulse is not actually generated.) V2A SUB EXP (3) 1 ≤ HSHUT < MAX value of HSHUT 1 to MAX MAX 0 8 (42) 1 to MAX 0 8 (42) 0 0 8 (42) HRI FRI V2A SUB EXP Numbers in parentheses are for FS mode. – 22 – CXD2457R (4) 1 ≤ HSHUT < MAX (with low-speed erectronic shutter) value of HSHUT 1 to MAX 1 to MAX (with low-speed erectronic shutter) 0 8 (42) 0 8 (42) 0 HRI FRI V2A SUB EXP (5) HSHUT = 0 value of HSHUT 1 to MAX MAX 0 8 (42) 0 0 8 (42) 0 0 8 (42) HRI FRI V2A SUB EXP (6) HSHUT = 0 (with low-speed erecyronic shutter) value of HSHUT 1 to MAX 0 (with low-speed erectronic shutter) 0 8 (42) 0 8 (42) HRI FRI V2A SUB EXP Numbers in parentheses are for FS mode. – 23 – – 24 – Mode OUT WEN ID XCPDM XCPOB PBLK SUB V3 V2B V2A V1 HRI FRI 779 (Chart B-1) FINE mode 1 2 3 4 5 6 7 1 2 3 4 (Chart B-3) 8 9 792 1 Chart A-1. FINE Mode (Vertical synchronization) 779 1 2 3 CXD2457R 792 1 790 788 Mode OUT WEN ID XCPDM XCPOB PBLK SUB V3 V2B V2A V1 757 760 763 766 769 772 251 252 253 254 255 256 HRI 7 10 13 16 19 22 25 28 31 1 2 3 4 5 6 7 8 9 FRI 757 760 763 766 769 772 251 252 253 254 255 256 264 1 5 DRAFT mode (Chart B-4) 10 (Chart B-2) 15 Chart A-2. DRAFT Mode (Vertical synchronization) 7 10 13 16 19 22 25 28 31 1 2 3 4 5 6 7 8 9 – 25 – 20 262 264 1 5 10 15 20 CXD2457R – 26 – Mode OUT WEN ID XCPDM XCPOB PBLK SUB V3 V2B V2A V1 HRI (Charts B-5/6) 1 (Chart B-4) (Charts B-1/2) FS mode The number of XSUB pulses is specified by the serial data. The number of sweeps is specified by the serial data. (Charts B-5/6) The mode is switched at the point where XSG is normally generated. DRAFT mode The number of sweeps is fixed (792). 7 8 9 FRI 43 Chart A-3. FS Mode (Vertical synchronization) CXD2457R 1 – 27 – Mode OUT WEN ID XCPDM XCPOB PBLK SUB V3 V2B V2A V1 HRI FRI (Chart B-1) 1 2 3 4 5 6 7 1 2 FINE mode 779 (Chart B-3) 8 9 792 1 FINE mode Chart A-4. FINE Mode (Vertical synchronization) Low-speed electronic shutter FINE mode FINE mode 1 2 3 CXD2457R 1 – 28 – 105 116 154 165 185 198 41 85 145 EXP 11 45 45 198 0 45 94 ID/WEN XCPDM XCPOB SUB H2 H1 V3 V2B V2A V1 MCK PBLK 0 0/1270 HRI Chart B-1. FINE Mode (Horizontal synchronization) 211 209 234 238 241 CXD2457R 11 63 – 29 – 116 117 135 135 144 154 153 162 162 171 180 189 189 198 198 108 108 126 EXP 99 198 90 94 ID/WEN XCPDM XCPOB SUB H2 H1 41 81 54 V2B V3 81 72 54 45 45 V2A V1 MCK PBLK 0 0/1270 HRI Chart B-2. DRAFT Mode (Horizontal synchronization) 211 209 234 241 238 CXD2457R – 30 – EXP V3 V2A/V2B V1 XSGB XSGA XV3 V2A/V2B XV1 0 85 45 105 185 165 145 94 245 848 bits 2 bits 850 848 HRI 51 bits 51 bits 899 900 Chart B-3. Readout Timing (FINE mode) CXD2457R – 31 – EXP V3 V2B V2A V1 XSGB XSGA XV3 XV2A/B XV1 HRI 0 90 117 144 171 198 81 108 135 162 189 72 99 126 153 188 215 63 54 45 94 848 bits Chart B-4. Readout Timing (DRAFT mode) 848 2 bits 1001 900 9 100 bits 9 1017 1008 899 850 51 bits 9 9 9 9 1046 1037 1028 54 bits CXD2457R 11 63 – 32 – EXP WEN ID XCPDM XCPOB SUB H2 H1 41 81 54 V2B V3 81 72 54 45 45 1 V2A V1 MCK PBLK HRI 0/1270 0 90 94 99 108 108 116 117 2 126 135 135 144 154 153 Chart B-5. FS Mode: V clock continuous drive start (Horizontal synchronization) 162 162 171 180 3 189 189 198 198 211 209 4 234 241 238 5 CXD2457R – 33 – EXP WEN ID XCPDM XCPOB SUB H2 H1 V3 11 63 41 81 54 72 V2B 45 45 81 22 54 21 0/1270 V2A V1 MCK PBLK HRI 20 1233 Chart B-6. FS Mode: V clock continuous drive end (Horizontal synchronization) CXD2457R CXD2457R Logical Phase 2MCK MCK H1 H2 RG XSHP XSHD XRS ADCLK (3MCK = 0) – 34 – CXD2457R Application Circuit DRVOUT VRT VRB A/D CXD2311AR XSHP XSHD XRS XCPOB XCPDM PBLK 2MCK MCK ID CCDOUT HRO FRO HRI FRI Timing Generator CXD2457R RG H1 H2 V1 V2A V2B V3 SUB Controller PS +3.3V TEST2 OSCI CKI SEN SSK SSI RST EXP OSCO CCD Image Sensor ICX204AK Signal Processor Block ADCLK TEST1 CDS/AGC CXA2006Q D0 to D9 For making FR and HR outside the CXD2457R, configure a circuit that counts MCK. (Using 2MCK, CKO, etc. is not recommended.) Also, set system setting data, SGXEN (D11) to "1" and stop a built-in SSG. Use crystal oscillator (fundamental wave) as base oscillation. Be sure to input duty 50% pulse when crystal oscillator is used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 35 – CXD2457R Notes on Turning Power ON To avoid setting VSUB pin of the CCD image sensor negative potential, the former two power supplies should be raised by the following order among three power supplies, –7.5V, +15.0V and +3.3V. 15.0V t1 20% 0V 20% –7.5V t2 t2 ≥ t1 – 36 – CXD2457R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 S 25 A 13 48 0.5 ± 0.2 (8.0) 24 37 (0.22) 12 1 + 0.05 0.127 – 0.02 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 0.13 M 0.1 0° to 10° S 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE LQFP-48P-L01 LEAD TREATMENT EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 37 –