CXD3300R 10-bit 20MSPS Video A/D Converter Description The CXD3300R is a 10-bit CMOS A/D converter for video applications. This IC is ideally suited for the A/D conversion of video signals in TVs, VCRs, camcorders, etc. Features • Resolution: 10 bits ± 1.0LSB (D.L.E.) • Maximum sampling frequency: 20MSPS • Low power consumption: 40mW (Except self-bias ) • Low input capacitance • Built-in self-bias circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage AVDD DVDD • Reference voltage VRT, VRB • Input voltage VIN (analog) • Input voltage VIH, VIL (digital) • Output voltage VOH, VOL (digital) • Storage temperature Tstg 48 pin LQFP (Plastic) Structure Silicon gate CMOS IC AVSS – 0.5 to +4.5 DVSS – 0.5 to +4.5 AVDD + 0.5 to AVSS – 0.5 AVDD + 0.5 to AVSS – 0.5 V V V V AVDD + 0.5 to AVSS – 0.5 V DVDD + 0.5 to DVSS – 0.5 V –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 3.0 ± 0.3 DVDD, DVSS 3.0 ± 0.3 | DVSS – AVSS | 0 to 100 • Reference input voltage VRB 0.3AVDD to 0.5AVDD VRT 0.6AVDD to 0.8AVDD • Analog input VIN 0.9Vp-p or more • Clock pulse width tPW1 25 (min.) tPW0 25 (min.) • Operating ambient temperature Topr –40 to +85 V V mV V V ns ns °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97310-PS CXD3300R Block Diagram VIN 38 VRT 28 VRTC 29 VRTS 27 AAA AAAA AAA AAAA AAAA AAAAAA AAAAAAA AAAA AAA AAA AAA AAAAAA AAA AAAA AAA AAAAAAA AAA AAA AAA AAA AAAA AAA AAA AAA AAAA AAA AAAAAAAAAA AAAA AAAA AAAAAA AAAAAA AAAAAA S/H Amp + ×8 12 – Coarse Correction & Latch D9 11 D8 10 D7 9 D6 8 D5 5 D4 4 D3 3 D2 2 D1 1 D0 (LSB) DAC VRMC 30 BE 36 VRBS 33 Fine Comparate & Encode Coarse Comparate & Encode Fine Latch Calibration Unit AVSS AVDD VRTS VRT VRTC BE Pin Configuration VRBC 36 35 34 33 32 31 30 29 28 27 26 25 TSTR 37 VIN 24 CE 38 23 TS 39 OE 22 CLK AVDD 40 21 AVDD AVSS 41 20 CAL 42 MINV 19 LINV AVDD 43 18 TESTMODE 3 4 5 6 7 8 9 10 11 12 D6 –2– D9 2 D8 1 D5 13 TO DVDD 14 TIN DVSS 48 DVSS DVDD 47 D4 15 RESET D3 16 AVSS AVSS 46 D1 AVDD 45 D2 17 AVDD D0 AT 44 D7 CE 24 Auto Calibration Pulse Generator VRMC OE 23 18 TESTMODE 42 CAL 15 RESET Timing Gen. VRB CLK 22 19 LINV VRBS VRBC 31 20 MINV AVDD 32 AVSS VRB CXD3300R Pin Description Pin No. Symbol Equivalent circuit Description DVDD 1 to 5 8 to 12 D0 (LSB) to D9 (MSB) output. D0 to D9 DVSS 6, 48 DVSS Digital VSS. 7, 47 DVDD Digital VDD. 13 TO Test pin. High impedance when TS = High. 14 TIN Test signal input. Normally fixed to AVDD or AVSS. AVDD 15 RESET Calibration circuit reset and startup calibration restart. 15 AVSS 16, 25, 34, 41, 46 AVSS Analog VSS. 17, 21, 26, 35, AVDD 40, 43, 45 Analog VDD. AVDD 18 TESTMODE Test mode. High: Output state Low: Output fixed 18 AVSS AVDD 19 LINV Output inversion. High: D0 to D8 are inverted and output. Low: D0 to D8 are normal output. 19 AVSS –3– CXD3300R Pin No. Symbol Equivalent circuit Description AVDD 20 MINV Output inversion. High: D9 is inverted and output. Low: D9 is normal output. 20 AVSS AVDD 22 CLK Clock. 22 AVSS AVDD 23 OE D0 to D9 output enable. Low: Output state High: High impedance state 23 AVSS AVDD 24 CE Chip enable. Low: Active state High: Standby state 24 AVSS –4– CXD3300R Pin No. Symbol Equivalent circuit Description AVDD 27 Self-bias. (Reference top) VRTS 27 AVSS AVDD 28 Reference top. VRT 28 AVSS AVDD 29 VRTC Reference top output. 29 AVSS AVDD 30 Reference middle output. VRMC 30 AVSS AVDD 31 Reference bottom output. VRBC 31 AVSS AVDD 32 VRB Reference bottom. 32 AVSS AVDD 33 Self-bias. (Reference bottom) VRBS 33 AVDD AVSS 36 36 Bias enable. BE AVSS –5– CXD3300R Pin No. Symbol Equivalent circuit Description 37 TSTR Test signal input. Normally fixed to AVDD or AVSS. 44 AT Test signal input. High impedance when TS = High. AVDD 38 VIN Analog input. 38 AVSS AVDD 42 CAL Calibration pulse input. 42 AVSS 39 Test signal input. Normally fixed to AVDD. TS –6– CXD3300R Digital Output The following table shows the correlation between the analog input voltage and the digital output code. (TESTMODE = 1, LINV, MINV = 0) Digital output code Input signal voltage Step VRT 1023 1 1 1 1 1 1 1 1 1 1 512 511 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VRB MSB LSB The following table shows the output state for the combination of TESTMODE, LINV, and MINV states. TESTMODE LINV MINV D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 P N P N 1 0 1 0 P N P N 0 1 0 1 P N P N 1 0 1 0 P N P N 0 1 0 1 P N P N 1 0 1 0 P N P N 0 1 0 1 P N P N 1 0 1 0 P N P N 0 1 0 1 P N P N 1 0 1 0 P P N N 0 0 1 1 P: Forward-phase output N: Inverted output Timing Chart 1 tPW1 tPW0 1.5V Clock A tSD Analog input AA AA N+1 N N+2 Data output N–3 N–2 A N–1 N+4 N A 1.5V Timing Chart 2 A A N+3 tDL : Indicates point at which analog data is sampled tPZE tPEZ 1.5V 1.5V Output enable (OE) 1.5V Data output Active High Impedance –7– Active CXD3300R Electrical Characteristics (Fc = 20MSPS, AVDD = 3V, DVDD = 3V, VRB = 1V, VRT = 2V, Ta = 25°C) Item Symbol Maximum conversion rate Fc max Minimum conversion rate Fc min Supply current Standby current Analog IADD Digital IDDD Analog IAST Digital IDST Reference pin current 1 IRT1 IRB1 IRT2 Conditions FIN = 1.0kHz sine wave input FIN = 1.0kHz sine wave input BE = High VRTS, VRBS: Open Between VRT and VRB Analog input band BW –1dB Analog input capacitance CIN Reference resistance value 1 RREF1 Between VRTS and VRT, VRT and VRB, VRB and VRBS Reference resistance value 2 RREF2 EOT1 Offset voltage2 Digital input voltage Analog input current Digital input current Digital output current Digital output current EOB1 EOT2 EOB2 11 14 17 1.0 4 1.0 µA 87 97 111 –111 97 –87 1.81 2.04 2.33 –2.33 –2.04 1.81 10 pF 10.3k 11.5k Ω Between VRTC and VRBC 430 490 550 Ω BE = AVDD EOT1 = Theoretical value – Measured value EOB1 = Measured value – Theoretical value –30 +5 +40 –30 +5 +40 BE = AVSS EOT2 = Theoretical value – Measured value EOB2 = Measured value – Theoretical value –30 +5 +40 –20 +10 +40 AVDD = 2.7 to 3.3V 0.7AVDD 0.2AVDD 55 AIL VIN = 1V –55 –48 –40 IIH IOZL mA MHz 48 IOZH µA 85 40 IOL mA mA VIN = 2V IOH MSPS 3.0 AIH IIL Unit 9k VIH VIL Max. 20 CE = AVDD IRB2 Offset voltage1 Typ. 0.5 BE = AVDD Between VRTC and VRBC Reference pin current 2 Min. AVDD = 3.3V VIH = AVDD 5 VIL = AVSS 5 OE = AVSS VOH = DVDD – 0.4V DVDD = 2.7V VOL = 0.4V 1.0 mV mV V µA µA mA 1.0 1 OE = AVDD VOH = DVDD DVDD = 3.3V VOL = 0V 1 µA Tri-state output disable time tPEZ Clock not synchronized for active → high impedance 6 8 10 ns Tri-state output enable time tPZE Clock not synchronized for high impedance → active 3 5 7 ns Integral nonlinearity error EL ±1.0 ±3.0 LSB Differential nonlinearity error ED ±0.5 ±1.0 LSB –8– CXD3300R Item Symbol Differential gain error DG Differential phase error DP Output data delay tDL tSD Sampling delay SNR SFDR SNR SFDR Conditions Min. NTSC 40 IRE mod ramp, Fc = 14.3MSPS CL = 3pF, Ta = –40 to +85°C Typ. Unit 1.0 % 0.3 deg 6 9 18 ns 6 7 8 ns FIN = 100kHz 50 FIN = 500kHz 50 FIN = 1MHz 50 FIN = 3MHz 50 FIN = 7MHz 45 FIN = 10MHz 44 FIN = 100kHz 52 FIN = 500kHz 52 FIN = 1MHz 52 FIN = 3MHz 52 FIN = 7MHz 49 FIN = 10MHz 50 –9– Max. dB dB CXD3300R Application Circuit 1 When not using self-bias and the internal bias circuits, and supplying the reference voltage from an external source. 1V 2V AVDD AVDD AVSS AVDD 21 41 AVSS MINV 20 42 CAL LINV 19 TESTMODE 18 48 DVSS TO 13 1 2 3 4 D6 TIN 14 D5 47 DVDD DVDD RESET 15 D4 46 AVSS DVSS AVSS 16 D3 AVDD 17 D2 44 AT 45 AVDD D1 DVSS AVSS 40 AVDD D0 DVDD AVDD CLK 22 43 AVDD AVSS VRTS VRT VRTC VRMC VRB VRBC OE 23 39 TS 5 6 7 8 9 10 11 12 Clock input AVDD Reset pulse AVSS D9 Calibration pulse CE 24 38 VIN D7 Signal input D8 1.0V AVSS BE 37 TSTR VRBS 2.0V AVDD 36 35 34 33 32 31 30 29 28 27 26 25 AVDD : 0.1µF DVSS DVDD Digital output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXD3300R Application Circuit 2 When not using self-bias circuit, using only the internal bias circuit, and supplying the reference voltage from an external source. 2V 1V AVDD AVDD AVSS AVSS 40 AVDD AVDD 21 41 AVSS MINV 20 42 CAL LINV 19 TESTMODE 18 TIN 14 48 DVSS TO 13 D6 47 DVDD D5 RESET 15 DVDD 46 AVSS DVSS AVSS 16 D4 45 AVDD D3 AVDD 17 D2 44 AT D1 DVSS AVSS CLK 22 D0 DVDD AVDD 39 TS 43 AVDD AVSS VRTS VRT VRTC VRBC VRMC VRB OE 23 1 2 3 4 5 6 7 8 9 10 11 12 Clock input AVDD Reset pulse AVSS D9 Calibration pulse CE 24 38 VIN D8 Signal input D7 1.0V VRBS BE 37 TSTR AVSS 2.0V AVDD 36 35 34 33 32 31 30 29 28 27 26 25 AVDD : 0.1µF DVSS DVDD Digital output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – CXD3300R Application Circuit 3 When using the self-bias and internal bias circuits, and supplying the reference voltage. AVDD AVDD AVSS AVSS AVDD 21 41 AVSS MINV 20 42 CAL LINV 19 TESTMODE 18 TO 13 1 2 3 4 5 6 D6 TIN 14 48 DVSS DVDD 47 DVDD D5 RESET 15 DVSS 46 AVSS D4 AVSS 16 D3 AVDD 17 D1 44 AT 45 AVDD D2 DVSS AVSS 40 AVDD D0 DVDD AVDD VRT CLK 22 43 AVDD AVSS VRTS VRTC VRBC VRMC VRB OE 23 39 TS 7 8 9 10 11 12 Clock input AVDD Reset pulse AVSS D9 Calibration pulse CE 24 38 VIN D8 Signal input D7 1.0V VRBS BE 37 TSTR AVSS 2.0V AVDD 36 35 34 33 32 31 30 29 28 27 26 25 AVDD : 0.1µF DVSS DVDD Digital output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 12 – CXD3300R 1. Calibration function 1) Activating startup calibration To achieve superior linearity, the CXD3300R has a built-in calibration circuit. When using this IC, therefore, startup calibration must be activated when the power supply and reference voltage have risen and stabilized. Care should be taken as only the upper five bits may be output in the worst case if startup calibration is not activated. Startup calibration can be activated either at the rise of the RESET pin (Pin 15) or at the fall of the CE pin (Pin 24). The startup calibration activation method for each case is shown in Fig. 1. a) When using RESET [V] 0 CE [V] AVDD 3 RESET b) When using CE VRT VRT VRB VRB 0 [t] H RESET L H CE L Startup calibration AVDD 3 [t] H L H L Startup calibration 33,000 CLK 33,000 CLK Fig. 1. Startup Calibration Activation Methods As shown in the figure above, startup calibration must be activated after the supply voltage has risen and stabilized (full scale of 90% or more). After activation, startup calibration is performed for an interval of about 33,000 clocks. Therefore, care should be taken as the output data during this interval (about 2.3ms at 14.3MHz) cannot be used. 2) Calibration pulse supply The IC's operating status with changes due to fluctuations in the supply voltage and ambient temperature during use can be constantly monitored and then compensated appropriately by inputting a pulse at regular intervals to the CAL pin (Pin 41). Fig. 2 shows the timing chart. 10ns or more 7 clocks CLK CAL D0 to D9 1 clock or more N–3 N–2 N–1 Fig. 2. Calibration Timing Chart – 13 – N N+5 CXD3300R Calibration starts when the fall of the pulse input to the CAL pin (Pin 41) is detected at the clock rise. At this time, the comparator is used in an exclusive manner for a four clock interval. So, the output data holds the immediately previous data for a four clock interval after seven clocks from the rise of the clock where the fall of the calibration pulse was detected, and then the data during this interval is missing. Therefore, the effects of this function can be avoided by inputting a sync or other signal as the calibration pulse so that calibration is performed outside of the interval of the actually used video signal. An input example is shown below. [1] Input every H sync Input CLK CAL [2] Input every V sync Input CLK RESET CAL 2. Latch-up Ensure that the AVDD and DVDD pins share the same power supply on a board to prevent latch-up which may be caused by power-ON time lag. 3. Board To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate its characteristics adequately. – 14 – CXD3300R Example of Representative Characteristics Maximum operating frequency vs. Ambient temperature Supply current vs. Ambient temperature 20 38 Maximum operating frequency [MHz] Supply current [mA] AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave 18 16 14 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave 36 34 32 –40 0 25 50 85 –40 Ambient temperature [°C] 25 50 85 Ambient temperature [°C] Output data delay vs. Ambient temperature Sampling delay vs. Ambient temperature 8 Sampling delay [ns] 11 Output data delay [ns] 0 10 9 6 4 AVDD = 3.0V DVDD = 3.0V Fc = 2MHz CL = 30pF AVDD = 3.0V DVDD = 3.0V Fc = 2MHz 8 2 –40 0 25 50 85 –40 Ambient temperature [°C] 0 25 50 85 Ambient temperature [°C] VRTC vs. Ambient temperature VRBC vs. Ambient temperature 2.0 1.20 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave 1.15 VRBC [V] VRTC [V] 1.95 1.90 1.10 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave 1.85 –40 1.05 0 25 50 85 –40 Ambient temperature [°C] 0 25 50 Ambient temperature [°C] – 15 – 85 CXD3300R SNR vs. Analog input frequency SFDR vs. Analog input frequency 70 70 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C 60 SNR [dB] SFDR [dB] 60 50 50 40 100k 1M 40 100k 100M Analog input frequency [Hz] 1M 100M Analog input frequency [Hz] Effective bit vs. Analog input frequency Analog input band 1 8 Output level [dB] Effective bit [bit] 0 7 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C 6 100k –1 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C –2 –3 1M 5M 100M 10M 50M 75M 85M Analog input frequency [Hz] Analog input frequency [Hz] – 16 – 100M CXD3300R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 S 25 13 0.5 ± 0.2 B A 48 (8.0) 24 37 (0.22) 12 1 + 0.05 0.127 – 0.02 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 0.13 M 0.1 S 0.5 ± 0.2 (0.18) 0° to 10° DETAIL B:SOLDER DETAIL A 0.18 ± 0.03 0.127 ± 0.04 + 0.08 0.18 – 0.03 (0.127) +0.05 0.127 – 0.02 0.1 ± 0.1 DETAIL B:PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-48P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 17 –