CXD2301Q
8-bit 30MSPS Video A/D Converter with Built-in Amplifier/Clamp
For the availability of this product, please contact the sales office.
Description
The CXD2301Q is an 8-bit CMOS A/D converter
for video applications with built-in amplifier/syncclamp circuits. A maximum conversion rate of
30MSPS is attained at a low power consumption by
adopting a 2-step parallel system.
Features
• Resolution: 8 bits ±1/2LSB (DL)
• Maximum sampling frequency: 30MSPS
• Low power consumption: 120mW (at 30MSPS
typ.)
(Including reference current)
• Standby function:
0.5mW power consumption in standby
• Amplifier functions: Built-in 3x amplifier (15MHz band),
2-input
selector
function
provided
• Synchronous clamp function
• Clamp ON/OFF function
• Reference voltage self-bias circuit
• TTL compatible output
• 3V digital interface capability
• Single 5V or dual 4.75/3.3V power supplies
• Low input capacitance: 8pF
• Reference impedance: 330Ω (typ.)
Applications
Wide range of application fields where high-speed
A/D conversion is required such as in the digital
systems of TVs, VCRs, etc.
Structure
Silicon gate CMOS IC
32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
7
• Reference voltage
VRT, VRB
VDD +0.5 to VSS –0.5
• Input voltage (analog) VIN
V
V
VDD +0.5 to VSS –0.5 V
• Input voltage (digital) VIH, VIL
VDD +0.5 to VSS –0.5 V
• Output voltage (digital) VOH, VOL
VDD +0.5 to VSS –0.5 V
• Storage temperature Tstg
–55 to +150 °C
Recommended Operating Conditions
• Supply voltage
IDVSS–AVSSI 0 to 100 mV
Single power supply
AVDD, DVDD 5.0 ± 0.25 V
Dual power supply
AVDD
4.75 ± 0.25 V
DVDD
3.3 ± 0.3
V
• Reference input voltage
VRB
0 to
V
VRT
to 2.2
V
• Analog input
ADIN More than 1.2Vp-p
• Clock pulse width
TPWI
16 (min) ns
16 (min) ns
TPWO
• Operating ambient temperature
Topr
–20 to +75 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E92Y50B4X-PK
CXD2301Q
Block Diagram
VIN2 VIN1
27
25
OPO
ADV
ADV
AVDD
30
21
22
26
3R
R
R
TEST 19
(DVSS)
RTS
VBI
SEL 4
23 VRT
Reference supply
CE 5
1 VRB
D0(LSB) 16
D1 15
D2 14
Lower
data
latch
D3 13
D4 12
D5 11
D6 10
Upper
data
latch
Lower encoder
(4 bit)
Lower
sampling comparator
(4 bit)
Lower encoder
(4 bit)
Lower
sampling comparator
(4 bit)
Upper encoder
(4 bit)
29 ADIN
Upper
sampling comparator
(4 bit)
ADV
3
AVSS
28 AVSS
31 AVSS
Clock generator
DVDD 17
DVSS 8
AVSS
7 AVSS
D7(MSB) 9
CLK 18
2
A/D Converter
Block
24
VREF
–2–
6
20
32
CLE CLP CCP
CXD2301Q
Pin Description
Pin No.
Symbol
Equivalent circuit
Description
Reference voltage (bottom)
Connect to AVSS for normal use.
When another external voltage is input,
connect an external 0.1µF capacitor and
retain a 1.5V differential compared to the
top reference voltage.
AVDD
1
VRB
RTS
Rref
1
23
23
VRT
AVSS
2, 3, 7,
28, 31
AVSS
4
SEL
Analog GND.
Switches the input of the 3x amplifier.
When SEL is at Low level, VIN1 is selected.
When SEL is at High level, VIN2 is selected.
AVDD
4
5
5
CE
Reference voltage (top)
By setting VRB to AVSS, outputs
approximately 1.5V.
Connect only a 0.1µF external by-pass
capacitor for normal use.
When another external voltage is input, it
must be 2.2V or lower.
Standby function ON/OFF selector.
In standby state when High.
19
DVSS
19
AVSS
TEST
Fix to VSS for normal use.
When CLE = Low: Clamp functiion is
enabled.
When CLE = High: Clamp function is
disabled, and only the normal A/D
converter function is enabled.
AVDD
6
CLE
6
18
18
CLK
20
Clock input
CE
Inputs the clamp pulse to Pin 20 (CLP).
Clamps the High interval signal voltage.
AVSS
20
CLP
8
DVSS
Digital GND.
D7 to D0
D7 (MSB) to D0 (LSB) output
Outputs Low level in standby.
In operation, the phase of D7 to D0
output is inverted against the phase of
ADIN.
9 to 16
17
Di
DVDD
5V or 3.3V
–3–
CXD2301Q
Pin No.
Symbol
Equivalent circuit
Description
AVDD
CE
21
ADV
21
AVSS
Short Pins 21 and 22, and connect 0.1µF
external capacitor.
AVDD
22
22
ADV
AVSS
AVDD
24
VREF
Clamp reference voltage input.
Clamps so that the reference voltage
and the clamp interval ADIN input signal
are equal.
The reference voltage is more than 0.5V.
24
AVSS
AVDD
25
27
VIN1
VIN2
200
R11
R
25
27
R12
AVSS
26
AVDD
Amplifier input pin.
Biased internally
at 1.9V (when AVDD = 5V) or
at 1.8V (when AVDD = 4.75V).
When in standby as well.
When SEL is at Low level, VIN1 is
selected for input;
When SEL is at High level, VIN2 is
selected for input.
5V or 4.75V
–4–
CXD2301Q
Pin No.
Symbol
Equivalent circuit
Description
AVDD
29
ADIN
A/D converter block analog input.
29
AVSS
AVDD
30
OPO
Amplifier output.
The phase of this output is inverted
against the phase of VIN1, 2.
In standby mode, it becomes
high-impedance output condition.
30
AVSS
AVDD
32
Integrates the clamp control voltage.
The relationship between the CCP
voltage variation and the ADIN voltage
is positive phase.
32
CCP
AVSS
• The following table shows the status of the digital output pins when the TEST pin is used with the CE and
SEL pins.
TEST
CE
SEL
D1
D2
D3
L
L
H
H
H
L
H
L
H
H
X
X
X
L
H
D1
L
D2
L
D3
L
H
L
L
H
H
L
D4
D5
D4
D5
L
L
TEST mode
L
H
H
L
–5–
D6
D7
D8
D6
L
D7
L
D8
L
L
H
H
L
L
H
CXD2301Q
Digital Output
The following table shows the correlation between the ADIN input voltage and the digital output code.
Take notice that the phase of ADIN input signal voltage is inverted against the phase of the digital output.
ADIN
Input signal voltage
Step
VRT
:
:
:
:
VRB
0
:
127
128
:
255
TPW 1
Digital output code
MSB
LSB
0 0 0 0 0
:
0 1 1 1 1
1 0 0 0 0
:
1 1 1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
TPW 0
Clock 2V
ADIN input
Data output
N
N+1
N–3
N+2
N–2
N+1
N+3
N
N+4
N–1
Td
: Indicates point at which input signal is sampled
Fig. 1. Timing Chart
–6–
CXD2301Q
Electrical Characteristics
(1) When using a single power supply (Fc = 30MSPS, AVDD = DVDD = +5V, VRB = 0V, VRT = 1.5V, Ta = 25°C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply current
IAD +
IDD
Fc = 35MSPS
NTSC ramp wave input
27
35
mA
Standby supply current
ISTB
CE = DVDD
130
200
µA
Max. conversion rate
Min. conversion rate
Fc max VIN = 0 to 1.5V
Fc min fIN = 1kHz ramp
ADIN input band (at –1dB)
BW
ADIN input capacitance
CADIN
30
0.5
VIN = 0.75V + 0.07Vrms
Offset voltage
Digital input voltage
Digital input current
Digital output current
20
MHz
8
pF
230
330
440
Ω
1.38
1.52
1.66
V
EOT
–40
–20
0
EOB
+25
+45
+65
VIH
3.5
Reference resistance (VRT to VRB) RREF
Self bias
MSPS
VRT
VRB = AVSS
0.5
VIL
IIH
DVDD = max.
IIL
IOH
IOL
DVDD = min.
VIH = VDD
5
VIL = 0V
5
mV
V
µA
VOH = VDD–0.5V
–1.1
–2.5
VOL = 0.4V
3.7
6.5
7
13
25
ns
mA
Output data delay
TDL
With TTL 1gate and 10pF load
Integral nonlinearity error
EL
Fc = 30MSPS
VIN = 0 to 1.5V
+0.5
+1.3
LSB
Differential nonlinearity error
ED
Fc = 30MSPS
VIN = 0 to 1.5V
±0.3
±0.5
LSB
Differential gain error
DG
Differential phase error
DP
Aperture jitter
1
%
0.5
deg
taj
30
ps
Sampling delay
tsd
2
ns
Clamp offset voltage
Eoc
Clamp pulse delay
tcpd
Amplifier gain
NTSC 40IRE mod
ramp, Fc = 14.3MSPS
VADIN = DC,
PWS = 3µsec
VBI1, 2
VIN1 and VIN2 input resistance
RI1, 2
0
+20
+40
VREF = 1.5V
–40
–20
0
8.5
19
27
15
–7–
10.5
1.9
When open
VIN1 and VIN2 input capacitance CI1, 2
9.5
mV
ns
25
DC to 15MHz
VIN1 and VIN2 bias voltage
VREF = 0.5V
dB
V
35
kΩ
pF
CXD2301Q
(2) When using a dual power supply (Fc = 30MSPS, AVDD = 4.75V, DVDD = 3.3V, VRB = 0V, VRT = 1.5V, Ta = 25°C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Analog supply current
IAD
Fc = 30MSPS
NTSC ramp wave input
24
32
mA
Digital supply current
IDD
Fc = 30MSPS
NTSC ramp wave input
1
2
mA
Standby supply current
ISTB
CE = DVDD
130
200
µA
Max. conversion rate
Min. conversion rate
Fc max VIN = 0 to 1.5V
Fc min fIN = 1kHz ramp
ADIN input band (at –1dB)
BW
ADIN input capacitance
CADIN
30
0.5
VIN = 0.75V + 0.07Vrms
Offset voltage
Digital input voltage
Digital input current
Digital output current
20
MHz
8
pF
230
330
440
Ω
1.44
1.52
1.6
V
EOT
–40
–20
0
EOB
+25
+45
+65
VIH
2.5
Reference resistance (VRT to VRB) RREF
Self bias
MSPS
VRT
VRB = AVSS
VIL
IIH
0.5
DVDD = max.
IIL
IOH
IOL
DVDD = min.
VIH = DVDD
5
VIL = 0V
5
mV
V
µA
VOH = VDD–0.5V
–1.1
–2.5
VOL = 0.4V
3.7
6.5
7
13
25
ns
mA
Output data delay
TDL
With TTL 1gate and 10pF load
Integral nonlinearity error
EL
Fc = 30MSPS
VIN = 0 to 1.5V
+0.5
+1.3
LSB
Differential nonlinearity error
ED
Fc = 30MSPS
VIN = 0 to 1.5V
±0.3
±0.5
LSB
Differential gain error
DG
Differential phase error
DP
Aperture jitter
1
%
0.5
deg
taj
30
ps
Sampling delay
tsd
2
ns
Clamp offset voltage
Eoc
Clamp pulse delay
tcpd
3x amplifier gain
NTSC 40IRE mod
ramp, Fc = 14.3MSPS
VREF = 0.5V
VIN = DC,
PWS = 3µsec VREF = 1.5V
VBI1, 2
VIN1 and VIN2 input resistance
RI1, 2
VIN1 and VIN2 input capacitance
CI1, 2
+20
+40
–40
–20
0
25
DC to 15MHz
VIN1 and VIN2 bias voltage
0
8.5
When open
9.5
27
15
–8–
ns
10.5
1.8
19
mV
dB
V
35
kΩ
pF
CXD2301Q
Application Circuit
(1) When using the internal amplifier
a) Clamp usage example (using self bias)
ACO4
+3.3V
CLOCK IN
CK
CLAMP PULSE IN
Q
LATCH *
+4.75V
0.1µ
0.1µ
0.1µ
VREF
20k
24
0.1µ
0.1µ
VIDEO IN
23
22
21
20
19
18
17
25
16
D0
26
15
D1
27
14
D2
28
13
D3
29
12
D4
30
11
D5
31
10
D6
32
9
D7
75
0.1µ
10p
0.01µ
1
2
3
4
GND (analog)
5
6
7
8
GND (digital)
∗ Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp
operation. However, depending on the relationship between the sampling frequency and the
clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at
this time.
–9–
CXD2301Q
b) Digital clamp usage example (using self bias)
ACO4
+3.3V
CLOCK IN
0.1µ
0.1µ
0.1µ
+4.75V
VIDEO
IN1
24
0.1µ
VIDEO
IN2
0.1µ
23
22
21
20
19
18
17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
Subtracter,
Comparator,
Clamp Level
Setting data
etc.
75
0.1µ
1
2
3
4
5
6
7
8
DAC,
GND (analog)
GND (digital)
PWM,
etc.
High impedance for all
information outside the
clamp interval
∗ The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is
positive phase.
∗ ∆ADIN/∆VCCP = 3.0 (fs = 30MSPS)
– 10 –
CXD2301Q
c) When not using the clamp
+3.3V (digital)
0.1µ
0.1µ
ACO4
0.1µ
CLOCK IN
24
0.1µ
+4.75V
0.1µ
VIDEO IN
0.1µ
23
22
21
20
19
18
17
25
16
D0
26
15
D1
27
14
D2
28
13
D3
29
12
D4
30
11
D5
31
10
D6
32
9
D7
75
0.1µ
10p
1
2
3
4
5
6
7
8
GND (digital)
GND (analog)
+3.3V (digital)
– 11 –
CXD2301Q
(2) When not using the internal amplifier
a) Clamp usage example
+4.75V
20k
0.1µ
0.1µ
+3.3V (digital)
ACO4
CLOCK IN
CLAMP PULSE IN
LATCH *
0.1µ
CK
Q
24
23
22
21
20
19
18
17
+4.75V (analog)
0.1µ
25
16
D0
26
15
D1
27
14
D2
28
13
D3
29
12
D4
30
11
D5
31
10
D6
32
9
D7
VIDEO IN #
10µ 75
10p
0.01µ
1
2
3
4
GND (analog)
5
6
7
8
GND (digital)
∗ Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp
operation. However, depending on the relationship between the sampling frequency and the
clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at
this time.
# Take care that the phase of ADIN input is inverted against the phase of the digital output,
because the use of the built-in inverting amplifier is standard. (Refer to “Digital Output” on page
6.)
– 12 –
CXD2301Q
b) Digital clamp usage example
{ 3.3V (digital)
0.1µ
0.1µ
ACO4
0.1µ
CLOCK IN
24
23
22
21
20
19
18
17
+4.75V (analog)
0.1µ
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
Subtracter,
Clamp Level
Setting data
Comparator,
VIDEO IN #
etc.
10µ 75
10p
1
0.01µ
2
3
6
5
4
GND (analog)
8
7
DAC,
GND (digital)
PWM,
etc.
High impedance for all
information outside the
clamp interval
∗ The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is
positive phase.
∗ ∆VADIN/∆VCCP = 3.0 (fs = 20MSPS)
c) When not using the clamp
+3.3V (digital)
0.1µ
0.1µ
ACO4
0.1µ
CLOCK IN
24
23
22
21
20
19
18
17
+4.75V (analog)
0.1µ
VIDEO IN #
25
16
D0
26
15
D1
27
14
D2
28
13
D3
29
12
D4
30
11
D5
31
10
D6
32
9
D7
75
10p
1
2
3
4
5
6
7
8
GND (digital)
GND (analog)
+3.3V (digital)
# Take care that the phase of ADIN input is inverted against the phase of the digital output,
because the use of the built-in inverting amplifier is standard. (Refer to “Digital Output” on page
6.)
– 13 –
CXD2301Q
Example of Representative Characteristics
–10
fIN=NTSC ramp wave
VIN=150mVrms
Current consumption [mA]
VDD=4.75V
VIN=150mVrms
–20
VIN1=GND
Crosstalk [dB]
–30
–40
–50
–60
30
20
–70
–80
1
5
10
0.1
50
fIN–Input frequency [MHz]
Input frequency of VIN2 vs.
Crosstalk VIN2→VIN1
Current consumption [mA]
40
30
0.5
1
5
10
1
5
10
Sampling frequency vs. Current consumption
VDD=5V,
Input waveform is ramp wave
VIN=150mVrms
20
0.1
0.5
fs–Sampling frequency [MHz]
50
fIN–Input frequency [MHz]
Input frequency vs. Current consumption
– 14 –
CXD2301Q
8bit ADC and DAC Evaluation Board
Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD2301Q
(8-bit 30MHz A/D) and CXD1171M (8-bit 40MHz D/A).
The evaluation board is composed of a main board common to either type, to which is added sub board
D2301Q or sub board D1171M. The junction is made through a socket.
To the main board are mounted an input interface, clock buffer and latch. To each of the sub boards is
mounted CXD2301Q and CXD1171M respectively. Those IC's are mounted according to recommended print
patterns designed to provide maximum performance to the A/D and D/A converters.
Block Diagram
V OUT
8
DATA LATCH
DAC
SOCKET
ANALOG CIRCUIT
MOUNT PORTION
DAC
SOCKET
V REF
ANALOG INPUT
INTERFACE
V IN
DIGITAL CIRCUIT MOUNT
PORTION
8
4
CLOCK
BUFFER
OSC
ANALOG CIRCUIT
MOUNT PORTION
SW
GND +5V
CLOCK OE SEL SYNC
–5V
CLE
BLK
Unnecessary at
self bias use
Characteristics
• Resolution
• Maximum conversion rate
• Digital input level
• Supply voltage
8bit
30MHz
CMOS level
±5.0V (Single +5V power supply possible at self bias use)
Supply Voltage
Item
Min.
Typ.
+5V
–5V
Clock Input
CMOS compatible
Pulse width TCW1
TCW0
Max.
Unit
165
20
mA
16ns (min)
16ns (min)
– 15 –
CXD2301Q
Analog Output (CXD1171M)
Item
Analog output
(RL > 10kΩ)
Min.
Typ.
Max.
Unit
1.8
2.0
2.1
V
Output Format (CXD2301Q)
The table shows the output format of AD Converter
Analog input
voltage
Step
VRT
:
:
:
:
VRB
0
:
127
128
:
255
Digital output code
MSB
LSB
0 0 0 0 0
:
0 1 1 1 1
1 0 0 0 0
:
1 1 1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
Timing Chart
Analog input
TPW0
External clock
TPW1
Tdc
AD clock
tPD(AD)
AD output
tDD
Latch output
DA input
tS
th
DA clock
DA output
Item
Symbol
tPD(DA)
Min.
Typ.
Max.
Unit
Clock High time
TPW1
16
ns
Clock Low time
TPW0
16
ns
Clock Delay
Tdc
Data delay AD
tPD (AD)
Data delay (latch)
tDD
tS
th
tPD (DA)
Settling time
Hold time
Data delay DA
13
24
ns
25
ns
5
ns
5
ns
10
ns
10
– 16 –
ns
C1 470µ
R1
100k
C3
Q3
R6
510
VIDEO INPUT
VR1
2k
R4
510
VRB
ADJUST
Q1
VR2
2k
Q2
AVSS
CLAMP
VOLTAGE
ADJUST
R2
75
R3
C2 10µ 75
AVDD
AVSS
R5
510
AVDD
VRT
ADJUST
47µ
VR3
20k
D0 1
24 DVDD
SW3
C4
0.01
C3
0.01
SW2
D6 9
D5 8
D4 7
D3 6
D2 5
D1 4
D0 3
DVSS 2
OE 1
21 AVDD
22 VIN
23 AVSS
24 AVSS
25 VRBS
26 VRB
27 VREF
28 CLE
0.01
D7 10
19 VRTS
20 AVDD
CLK 12
DVDD 11
17 NC
SEL 13
16 NC
18 VRT
SYNC 14
15 PW
SW1
D1 2
23 NC
DVDD
DVSS
DVDD
DVDD
CLK
DVDD
3
4
5
6
7
8
1
2
DVSS
CLEAR
DVSS
14
13
12
11
10
9
8
0.01µ
1
2
3
4
5
6
7
DVSS
2
CLEAR
74S174
16 (LATCH) 1
15
14
13
12
11
10
9
16
15
0.01µ
4
3
D3 4
21 IO
14
13
D4 5
D2 3
5
12
D5 6
19 AVDD
20 AVDD
22 IO
10 74S174 7
11 (LATCH) 6
D6 7
8
18 VREF
9
D7 8
CLK
BLK 9
0.01µ
16 AVSS
CLK 10
17 IREF
15 AVSS
NC 12
DVSS 11
13 NC
14 NC
V OUT
R7
200
(R)
0.1 (16R)
R8
C5 3.3k
VR4
20k
OUTPUT
GAIN
ADJUST
DVSS
74S04 OR 74HC04
(INV BUFFER)
– 17 –
–5V
+5V
GND
AVDD
DVDD
DVDD
CMOS ADC/DAC Peripheral Circuit Board (Main Board)
OE
SEL
CLE
BLK
SYNC
OSC SWITCH
EXT/INT
8
7 DVSS
R9
75
VR5
20k
47µ
R10
75
SYNC INT
(R IN=75µ)
EXTERNAL CLOCK
INPUT
OSC OUT
1
14 DVDD
CXD2301Q
CXD2301Q
CMOS ADC/DAC Peripheral Circuit Board (Sub Board)
C3
0.01µ
CLP 15
14 NC
C2
0.1µ
NC 16
24
NC 17
23
22
21
C1
0.1µ
20
19
18
13 NC
17
12 CLK
25
16
11 DVDD
NC 19
26
15
10 D7
AVDD 20
27
14
9
D6
13
8
D5
29
12
7
D4
AVSS 23
30
11
6
D3
AVSS 24
31
10
5
D2
32
9
4
D1
3
D0
VREF 27
2
DVSS
CLE 28
1
NC
NC 18
C4
0.1µ
AVDD 21
28
C6
1µ
VIN 22
CXD2301Q
NC 25
C5
1000p
NC 26
1
2
3
4
5
6
7
8
NC 13
13
12
NC 14
14
11
12 NC
11 DVSS
C4
AVSS 15
15
10
AVSS 16
16
9
9
BLK
17
8
8
D7
7
7
D6
D5
IREF 17
C3
10 CLK
C2
VREF 18
18
AVDD 19
19
6
6
AVDD 20
20
5
5 D4
IO 21
21
4
4
D3
IO 22
22
3
3
D2
NC 23
23
2
2 D1
DVDD 24
24
1
1
CXD1171M
C1
– 18 –
D0
CXD2301Q
List of Parts
resitance
R1
100k
R2
75Ω
R3
75Ω
R4
510Ω
R5
510Ω
R6
510Ω
R7
R = 200
R8
18R ≈ 3.3k
R9
75Ω
R10
75Ω
VR1
2k
VR2
2k
VR3
20k
VR4
20k
VR5
20k
transistor
Q1
Q2
Q3
2SC2785
2SC2785
2SC2785
ic
IC1
IC2
IC3
74S174
74S174
74S04
oscillator
OSC
others
connector
SW
BNC071
AT1D2M3
capacitance
C1
470µF/6.3V (chemical)
C2
10µF/16V (chemical)
C3
0.01µF
C4
0.01µF
C5
0.1µF
C6
0.1µF
C7
0.1µF
C8
0.1µF
C9
0.1µF
C10
0.1µF
C11
47µF/10V (chemical)
C12
47µF/10V (chemical)
C13
47µF/10V (chemical)
C14
0.1µF
Adjustment
1. Vref adjustment (VR1, VR2)
Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2. When
self bias is used, there is no need for adjustment. Reference voltage is set through self bias at delivery.
2. Setting of clamp reference voltage (VR3)
Clamp reference voltage is set.
3. DAC output full scale adjustment (VR4)
Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is adjusted
to approx. 2V.
4. Sync (clamp) pulse interface (VR5)
This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is
performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V.
– 19 –
CXD2301Q
5. OE, SEL, Sync, BLK, CLE, Sync INT
The following pins are set on the main board: Sync, CLE, Sync INT (CXD2301Q) and BLK (CXD1171M),
OE, SEL (not used). For the pins function, refer to the specifications. The difference between Sync pin and
Sync INT pin is that you input a pulse above 3.5Vp-p to Sync INT pin. The pulse threshold is set through
VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line
between Sync pin and Sync INT pin.
At the PCB shipment the main board pins are set as follows.
• OE ........ Low
• SEL ...... Low
• Sync ..... Line junction with Sync INT pin
• CLE ...... Low (Clamp function ON)
• BLK ...... Low (Blanking OFF)
6. Clamp pulse input method
The clamp pulse is directly input to CXD2301Q as show in Application Circuit examples (1) and (2). Use the
direct input that is set at the PCB shipment.
Points on the PCB Pattern Layout
1. Set the layout not to have Digital current flow into Analog GND (Part 1). (For 1, see P.17 Component side
diagram.)
2. At CXD2301Q sub board, C2 and C3 capacitors serve the important role of bringing out CXD2301Q's full
performance.
These are over 0.1µF (ceramic) capacitors with good high frequency characteristics. Layout as close to the
IC as possible.
3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage and power source. Keeping ADC's
DVSS (Part 2) as close as possible to the voltage supply source will provide better results. That is, a layout
where ADC is close to the voltage supply source, is recommended. (For 2, see P.17 Component side
diagram.)
4. ADC samples analog signals at the clock falling edge point. Accordingly clocks supplied to ADC should not
have any jitter.
5. The PCB layout shows ADC and DAC's Analog GND independently from the voltage supply source. The
layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual
board, common use will not cause any problems.
– 20 –
CXD2301Q
Notes on Operation
1. Reference voltage
By shorting VRT and VRTS, VRB and VRBS, CXD2301 has the self bias function that generates VRT = about
2.6V and VRB = about 0.5V. On the PCB, either self bias or the external reference voltage can be selected
depending on the junction method of the jumper line. At shipment from the factory, reference voltage is
provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (VRT – VRB) to
above 1.8Vp-p.
2. Clock input
There are 2 modes for the PCB clock input.
1) Provided from the external signal generator (External clock)
2) Using the crystal oscillator (built-in clock driver). (Internal clock)
The 2 modes are selected using the switch on the PCB.
3. The 2 Latch IC's (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is,
operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data
is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an
example layout of Digital signal processing IC. When the ADC output data is used, use the output of the
latch IC.
4. When clamp is not used
Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2 on
the main board and DC voltage on the ADC side of C2 turns to about (VRT + VRB). To transfer DC elements
of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can
also be used as buffer. Use the open space for the bias circuit.
5. Clamp pulse latch
On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to the CLP pin.
This is to minimize Vsag due the synchronizing of noise and clamp pulse beat elements with GND sampling
clock around ADC. If there are no problems with Vsag, latch is not necessary.
6. Peripheral through hole
There is a group of through holes on the Analog input, output and Logic. These are to be used when
mounting additional circuits to the PCB. Use when necessary.
The connector hole on DAC part is used to mount the test chassis and the mount jack.
– 21 –
CXD2301Q
Silk Side
Component Side
Soldering Side (Diagram seen from the component side)
– 22 –
CXD2301Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 ± 0.2
24
0.1
+ 0.35
1.5 – 0.15
+ 0.3
7.0 – 0.1
17
16
32
9
(8.0)
25
1
+ 0.2
0.1 – 0.1
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
+ 0.1
0.127 – 0.05
0° to 10°
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP032-P-0707-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.2g
JEDEC CODE
– 23 –
0.50
8