CXD2302Q 8-bit 50MSPS Video A/D Converter with Clamp Function Description The CXD2302Q is an 8-bit CMOS A/D converter for video with synchronizing clamp function. The adoption of 2 step-parallel method achieves low power consumption and a maximum conversion rate of 50MSPS. Features • Resolution: 8 bit ± 1/2LSB (DL) • Maximum sampling frequency: 50MSPS • Low power consumption: 125mW (at 50MSPS typ.) (reference current excluded) • Synchronizing clamp function • Clamp ON/OFF function • Reference voltage self-bias circuit • Input CMOS/TTL compatible • 3-state TTL compatible output • Single 5V power supply or dual 5V/3.3V power supply • Low input capacitance: 15pF • Reference impedance: 370Ω (typ.) Applications Wide range of applications that require high-speed A/D conversion such as TV and VCR. Structure Silicon gate CMOS IC 32 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 7 V • Supply voltage VDD • Reference voltage VRT,VRB VDD + 0.5 to Vss – 0.5V • Input voltage VIN VDD + 0.5 to Vss – 0.5V (Analog) • Input voltage VI VDD + 0.5 to Vss – 0.5V (Digital) • Output voltage VO (Digital) • Storage temperature Tstg VDD + 0.5 to Vss – 0.5V –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVss 4.75 to 5.25 V DVDD, DVss 3.0 to 5.5 V | DVss – AVss | 0 to 100 mV • Reference input voltage VRB 0 and above V VRT 2.7 and below V • Analog input VIN 1.7Vp-p above • Clock pulse width TPW1, TPW0 9ns (min) to 1.1µs (max) • Operating ambient temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94102E78-PS CXD2302Q Block Diagram DVss 28 OE 30 Reference supply DVss D0 (LSB) 1 D1 2 D2 3 D3 4 D4 Lower data latch 6 D6 7 D7 (MSB) 8 DVDD 10 TEST (OPEN) 11 CLK 12 Lower encoder (4 BIT) Lower encoder (4 BIT) 5 D5 TEST (OPEN) 25 VRBS 24 VRB 23 AVss 22 AVss 21 VIN 20 AVDD 19 AVDD 18 VRT 17 VRTS 16 AVDD 15 CLP 14 NC 13 NC 31 Upper data latch Upper encoder (4 BIT) Lower sampling comparator (4 BIT) Lower sampling comparator (4 BIT) Upper sampling comparator (4 BIT) Clock generator 9 NC 32 D-FF 29 27 26 CLE CCP VREF –2– CXD2302Q Pin Description Pin No. Symbol Equivalent circuit Description DVDD Di 1 to 8 D0 (LSB) to D7 (MSB) output D0 to D7 DVSS DVDD 9 9 TEST Leave open for normal use. DVSS 10 DVDD Digital power supply +5V or +3.3V 11 TEST Leave open for normal use. Pull-up resistor is built in. Input the clamp pulse. Clamps the signal voltage during Low interval. Pull-up resistor is built in. AVDD 15 CLP 11 15 The clamp function is enabled when CLE = Low. The clamp function is set to off and the converter functions as a normal A/D converter when CLE = High. Pull-up resistor is built in. 29 29 AVSS CLE AVDD 12 CLK Clock input. Set to Low level when no clock is input. 12 AVSS 13, 14, 32 NC 16, 19, 20 AVDD Analog power supply +5V –3– CXD2302Q Pin No. Symbol 17 VRTS 18 VRT Equivalent circuit Generates approximately +2.5V when shorted with AVDD. AVDD 17 Reference voltage (top) RT 18 24 Rref 24 VRB 25 VRBS Description 25 RB Reference voltage (bottom) Generates approximately +0.6V when shorted with AVSS. AVSS AVDD 21 VIN 21 Analog input AVSS 22, 23 Analog ground AVSS AVDD 26 VREF Clamp reference voltage input. Clamps so that the reference voltage and the input signal during clamp interval are equal. 26 AVSS AVDD 27 CCP Integrates the clamp control voltage. The relationship between the changes in CCP voltage and in VIN voltage is positive phase. 27 AVSS 28, 31 DVSS Digital ground AVDD 30 OE Data is output when OE = Low. Pins D0 to D7 are at high impedance when OE = High. Pull-down resistor is built in. 30 AVSS –4– CXD2302Q Digital output The following table shows the relationship between analog input voltage and digital output code. Input signal voltage Step VRT : : : : VRB 0 : 127 128 : 255 Digital output code MSB LSB 1 1 1 1 1 : 1 0 0 0 0 0 1 1 1 1 : 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 Timing Chart I TPW1 TPW0 Clock 1.3V Analog input N N+1 N–3 Data output N–2 N+2 N+3 N+4 N–1 N N+1 O: Analog signal sampling point Timing Chart I-1. tr 4ns tf 4ns 3V 90% Clock 1.3V 10% Data output 0V 0.7DVDD 0.3DVDD tpLH, tpHL Timing Chart I-2. tr = 4.5ns tf = 4.5ns 3V 90% OE input 1.3V 10% tpLZ 0V tpZL VOH Output 1 1.3V 10% VOL (≠ DVSS) tpHZ tpZH VOH (≠ DVDD) 90% 1.3V Output 2 VOL Timing Chart I-3. –5– CXD2302Q Electrical Characteristics Analog characteristics Item (Fc = 50MHz, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Symbol Conditions AVDD = 4.75 to 5.25V Ta = –40 to +85°C, VIN = 0.5 to 2.5V fIN = 1kHz triangular wave Max. conversion rate Fc max. Min. conversion rate Fc min. Analog input band width BW Differential non-linearity error ED Integral non-linearity error EL Offset voltage∗1 EOT Potential difference to VRT EOB Potential difference to VRB Differential gain error DG Differential phase error DP NTSC 40 IRE mod ramp Fc =14.3MSPS Sampling delay tsd Clamp offset voltage∗2 Signal-to-noise ratio Spurious free dynamic range EOC SNR FSDR Envelope RIN = 33Ω Min. Typ. 50 65 Unit MSPS 0.5 –1dB 60 –3dB 100 MHz ±0.3 ±0.5 +0.7 ±1.5 –70 –50 –30 20 40 60 End point VIN = DC VREF = 0.5V CIN = 10µF tpcw = 2.75µs Fc = 14.3MHz VREF = 2.5V Fclp = 15.75kHz Max. 0 LSB mV 3 % 1.5 deg 0 ns 20 40 mV 0 20 FIN = 100kHz 45 FIN = 500kHz 44 FIN = 1MHz 44 FIN = 3MHz 43 FIN = 10MHz 38 FIN = 25MHz 32 FIN = 100kHz 51 FIN = 500kHz 46 FIN = 1MHz 49 FIN = 3MHz 46 FIN = 10MHz 45 FIN = 25MHz 45 40 dB dB ∗1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”. EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2LSB of the voltage when the output data changes from “11111111” to “11111110”. ∗2 Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be generated. –6– CXD2302Q DC characteristics (Fc = 50MHz, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Item Symbol IAD + IDD Supply current Analog IAD Digital IDD Conditions NTSC ramp wave input CLE = 0V Min. DVDD = 5V DVDD = 3.3V Typ. Max. 25 36 23 33 2 3 Unit mA Reference current IREF 4.1 5.4 7.7 mA Reference resistance (VRT – VRB) RREF 260 370 480 Ω 0.52 0.56 0.60 1.80 1.92 2.04 Self-bias voltage Analog input resistance Input capacitance Output capacitance Digital input voltage VRB VRT – VRB RIN Shorts VRTS and AVDD Shorts VRBS and AVSS VIN Fc = 50MHz 13 Fc = 35MHz 16 Fc = 20MHz 30 VIN, VIN = 1.5V + 0.07Vrms CAI2 VRTS, VRT, VRB, VRBS, VREF 11 CDIN TEST, CLK, CLP, CLE, OE 11 CAO CCP 11 CDO D0 to D7, TEST 11 VIH AVDD = 4.75 to 5.25V DVDD = 3 to 5.5V Ta = –40 to +85°C CLK Digital input current kΩ CAI1 VIL IIH IIL VI = 0V to AVDD TEST, Ta = –40 to +85°C CLP, CLE OE IOH OE = 0V DVDD = 5V 15 pF V 0.8 –240 240 –240 40 –40 240 µA –2 mA Ta = –40 to +85°C VOL = 0.4V IOH OE = 0V DVDD = 3.3V 4 VOH = DVDD – 0.8V –1.2 mA IOL Ta = –40 to +85°C VOL = 0.4V 2.4 IOZH VOH = DVDD OE = 3V DVDD = 3 to 5.5V Ta = –40 to +85°C VOL = 0V –40 40 –40 40 IOZL pF 2.2 VOH = DVDD – 0.8V IOL Digital output current V µA Note) The voltage of up to (AVDD + 0.5V) can be input when DVDD = 3.3V. But the output pin voltage is less than the DVDD voltage. When the digital output is in the high impedance mode, the IC may be damaged by applying the voltage which is more than the (DVDD + 0.5V) voltage to the digital output. –7– CXD2302Q (Fc = 50MHz, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Timing Item Symbol tpLH tpHL tpLH tpHL tpZH tpZL tpZH tpZL tpHZ tpLZ tpHZ tpLZ Output data delay Tri-state output enable time Tri-state output disable time Clamp pulse width∗ tCPW Conditions Min. DVDD = 5V 5.5 Typ. 9.5 Max. 12.0 8.5 CL = 15pF OE = 0V DVDD = 3.3V 4.3 11.8 Unit ns 16.3 7.6 RL = 1kΩ CL = 15pF OE = 3V → 0V DVDD = 5V 2.5 4.5 8.0 6.0 DVDD = 3.3V 3.0 ns 7.0 9.0 5.0 RL = 1kΩ CL = 15pF OE = 0V → 3V DVDD = 5V 3.5 DVDD = 3.3V 5.5 7.5 2.5 5.5 8.0 1.75 2.75 3.75 ns Fc = 14.3MHz, CIN = 10µF for NTSC wave µs ∗ The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) for other processing systems to equal the values for NTSC. Electrical Characteristics Measurement Circuit Output data delay measurement circuit Tri-state output measurement circuit Measurement point To output pin DVDD Measurement point RL CL To output pin CL Note) CL includes capacitance of probes. –8– RL CXD2302Q Integral non-linearity error Differential non-linearity error Offset voltage } Analog input resistance test circuit test circuit +5V 2.5V +V VDD VRT S2 S1: ON IF A < B S2: ON IF B > A VIN S1 VRB CLK 0.5V –V VIN GND A<B A>B COMPARATOR A8 B8 to to A1 B1 A0 B0 8 DUT CXD2302Q 8 "0" DVM BUFFER "1" 8 CLK (50MHz) CONTROLLER Differential gain error Differential phase error } 000 · · · 00 TO 111 · · · 10 test circuit CX20202A-1 NTSC SIGNAL SOURCE VIN IAE 100 40 IRE MODULATION TTL 8 ECL 2.5V 8 10bit D/A VECTOR SCOPE 620 –5.2V BURST CLK D.G D.P. 0 –40 S.G. (CW) CXD 2302Q AMP 0.5V SYNC 620 TTL FC –5.2V ECL Digital output current test circuit 2.5V 0.5V VDD VRT D0 VIN to VRB D7 CLK OE GND 2.5V IOL 0.5V VOL VDD VRT VIN D0 to VRB D7 CLK OE GND + – –9– IOH VOH + – CXD2302Q Timing Chart II Vi (1) Vi (2) Vi (3) Vi (4) Analog input External clock Upper comparators block (1) (2) S (1) Upper data Lower data B Digital output C (2) (4) S (3) MD (1) RV (0) H (1) C (3) C (1) C (0) C (4) MD (3) RV (2) RV (3) S (3) H (3) LD (–1) H (0) S (4) MD (2) RV (1) S (1) Lower data A Lower comparators B block S (2) MD (0) Lower reference voltage Lower comparators A block C (1) (3) C (3) LD (1) S (2) LD (–2) H (2) C (2) LD (0) Out (–2) Out (–1) S (4) H (4) LD (2) Out (0) Out (1) Operation (See Block Diagram and Timing Chart II) 1. The CXD2302Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparator block and 2 lower comparator blocks of 4-bit each. The reference voltage that is equal to the voltage between VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower 4-bit comparator block. VRTS and VRBS pins serve for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom), and they are also used as the sence pins as shown in the Application Circuit examples I-4 and I-5. – 10 – CXD2302Q 2. This IC uses an offset cancel type comparator which operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart II with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. 3. The operation of respective parts is as indicated in the Timing Chart II. For instance input voltage Vi (1) is sampled with the falling edge of the external clock (1) by means of the upper comparator block and the lower comparator A block. The upper comparator block finalizes comparison data MD (1) with the rising edge of the external clock (2). Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator A block finalizes comparison data LD (1) with the rising edge of the external clock (3). MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the external clock (4). Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. Operation Notes 1. VDD, VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the respective GND’s. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be prevented by insetting a resistance of about 33Ω in series between the amplifier output and A/D input. When the VIN signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no effect on the characteristics of A/D conversion. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VDD and VRTS, VSS and VRBS respectively, the self-bias function that generates VRT=about 2.5V and VRB=about 0.6V, is activated. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data synchronized with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 9ns (DVDD = 5V). 6. OE pin Pins 1 to 8 (D0 to D7) are in the output mode by leaving OE open or connecting it to DVSS, and they are in the high impedance mode by connecting it to DVDD. – 11 – CXD2302Q Application Circuit I. Single +5V Power Supply I-1. When clamp is used (self-bias used) +5V (Digital) ACO4 0.1µ CLOCK IN OPEN 16 CLAMP PULSE IN 0.01µ +5V (Analog) VIDEO IN 15 14 13 12 10 11 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 10µ 33Ω 0.1µ 10p +5V (Analog) 0.01µ 25 26 27 VREF 28 29 31 30 32 0.01µ 20K GND (Digital) GND (Analog) I-2. Digital clamp (self-bias used) +5V (Digital) 0.1µ ACO4 CLOCK IN OPEN 16 0.01µ +5V (Analog) VIDEO IN 10µ 15 14 13 12 11 10 9 17 8 18 7 19 6 20 5 21 4 22 3 23 2 24 1 33Ω 0.1µ 10p 0.01µ 25 26 27 28 ∗ The relationship between the changes in CCP voltage (Pin 27) and in VIN voltage is positive phase. ∗ ∆Vin/∆Vccp = 3.0 (fs = 20MSPS) 29 30 31 Clamp level setting data 32 GND (Digital) GND (Analog) Subtracter · Comparator · etc. DAC · PWM · etc. ← Information other than that for clamp interval is at high impedance. – 12 – CXD2302Q I-3. When clamp is not used (self-bias used) +5V (Digital) ACO4 0.1µ CLOCK IN OPEN 15 16 0.01µ +5V (Analog) VIDEO IN 14 13 12 11 10 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 33Ω 0.1µ 10p 0.01µ 25 26 27 28 29 30 31 32 GND (Digital) GND (Analog) I-4. When clamp is used (self-bias not used) +5V (Digital) ACO4 0.1µ CLOCK IN OPEN 16 CLAMP PULSE IN VRT 0.01µ +5V (Analog) VIDEO IN 15 14 13 12 11 10 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 10µ 33Ω 0.1µ 10p 0.01µ VRB 25 +5V (Analog) 26 27 VREF 20K 28 29 30 31 32 0.01µ GND (Digital) GND (Analog) – 13 – CXD2302Q I-5. When clamp is not used (self-bias not used) +5V (Digital) 0.1µ ACO4 CLOCK IN OPEN 16 VRT 0.01µ 15 14 13 12 11 10 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 +5V (Analog) VIDEO IN 33Ω 0.1µ 10p 0.01µ VRB 25 26 27 28 29 30 31 32 GND (Digital) GND (Analog) II. Dual +5V/+3.3V Power Supply II-1. When clamp is used (self-bias used) +3.3V (Digital) 0.1µ ACO4 CLOCK IN OPEN 16 CLAMP PULSE IN 0.01µ +5V (Analog) VIDEO IN 15 14 13 12 11 10 9 17 8 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 D0 10µ 33Ω 0.1µ 10p +5V (Analog) 0.01µ 25 26 27 VREF 28 29 30 31 32 0.01µ 20K GND (Digital) GND (Analog) – 14 – CXD2302Q Example of Representative Characteristics Supply voltage vs. Supply current Fc = 50MHz NTSC ramp wave input AVDD = DVDD = 5V 26 Supply current [mA] Supply current [mA] Ambient temperature vs. Supply current 25 24 –20 0 25 50 27 25 Fc = 50MHz NTSC ramp wave input AVDD = DVDD Ta = 25°C 23 75 4.75 5 5.25 Ambient temperature [°C] Supply voltage [V] Sampling frequency vs. Supply current Input frequency vs. Supply current Supply current [mA] Supply current [mA] Fc = 50MHz 25 20 NTSC ramp wave input AVDD = DVDD = 5V Ta = 25°C 15 10 20 30 40 50 35 Sine wave 1.9Vp-p AVDD = DVDD = 5V Ta = 25°C 30 25 0.01 0.1 1 10 25 Ambient temperature vs. Maximum operating frequency Supply voltage vs. Maximum operating frequency 65 60 –20 0 25 50 75 67 Fc = 50MHz NTSC ramp wave input AVDD = DVDD 65 63 4.75 5 5.25 Ambient temperature [°C] Supply voltage [V] Ambient temperature vs. Sampling delay Analog input band Fc = 50MHz AVDD = DVDD = 5V 1 0 –1 Output level [dB] Sampling delay [ns] Fc = 50MHz fin = 1kHz, triangular wave input AVDD = DVDD = 5V 70 Maximum operating rate [MSPS] Input frequency [MHz] Maximum operating rate [MSPS] Sampling frequency [MSPS] Fc = 50MHz Sine wave 1Vp-p input AVDD = DVDD = 5V Ta = 25°C 0 –1 –3 –20 0 25 50 75 0.1 Ambient temperature [°C] 1 10 100 Analog input frequency [MHz] – 15 – CXD2302Q 6 5 40 60 FSDR [dB] 7 Analog input frequency vs. FSDR Fc = 50MHz AVDD = DVDD = 5V VIN = 2Vp-p Ta = 25°C 50 8 SNR [dB] Effective bit [bit] Analog input frequency vs. SNR, effective bit Fc = 50MHz AVDD = DVDD = 5V VIN = 2Vp-p Ta = 25°C 50 40 30 30 0.01 0.1 1 10 0.1 0.01 Analog input frequency [MHz] 12 10 tpLH 8 tpHL 6 –20 0 25 50 tpLH 12 Fc = 10MHz AVDD = 5V DVDD = 3.3V CL = 15pF 10 8 tpHL 6 75 –20 Ambient temperature [°C] Output data delay [ns] Output data delay [ns] 10 tpHL 8 6 10 15 50 75 Load capacitance vs. Output data delay 20 12 Fc = 10MHz AVDD = 5V DVDD = 3.3V Ta = 25°C tpLH 10 8 tpHL 6 0 25 5 10 15 20 25 Load capacitance [pF] Load capacitance [pF] DVDD supply voltage vs. Output data delay Analog input voltage vs. Input current Fc = 10MHz AVDD = 5V CL = 15pF Ta = 25°C tpLH 12 10 8 tpHL 6 3 3.5 4.5 5 Analog input current IAI [µA] Output data delay [ns] tpLH 5 25 14 Fc = 10MHz AVDD = DVDD = 5V Ta = 25°C 0 0 Ambient temperature [°C] Load capacitance vs. Output data delay 12 10 Ambient temperature vs. Output data delay Output data delay [ns] Output data delay [ns] Ambient temperature vs. Output data delay Fc = 10MHz AVDD = DVDD = 5V CL = 15pF 1 Analog input frequency [MHz] 80 0 Fc = 50MHz AVDD = DVDD = 5V VRT = 2.5V VRB = 0.5V Ta = 25°C –80 0.5 5.5 1.5 Analog input voltage VIN [V] DVDD supply voltage [V] – 16 – 2.5 CXD2302Q 8-bit 50MSPS ADC and DAC Evaluation Board Evaluation boards are available for the high speed, low power consumption CMOS converters CXD2302Q (8-bit 50MHz A/D) and CXD1171M (8-bit 40MHz D/A). The evaluation boards are composed of a main board, CXD2302Q sub board and CXD1171M sub board. The each board is connected with sockets. An input interface, clock buffer and latches are mounted on the main board. The CXD2302Q and CXD1171M are mounted on each of the sub boards. Those ICs are mounted according to recommended print patterns designed to provide maximum performance to the A/D and D/A converters. Block Diagram ANALOG CIRCUIT MOUNT PORTION 8 ADC SOCKET V REF V IN ANALOG INPUT INTERFACE DIGITAL CIRCUIT MOUNT PORTION DATA LATCH DAC SOCKET V OUT 8 4 CLOCK BUFFER OSC ANALOG CIRCUIT MOUNT PORTION SW GND +5V –5V CLOCK OE SEL SYNC CLE Unnecessary at self bias use Characteristics • Resolution • Maximum conversion rate • Digital input level • Supply voltage 8bit 50MHz CMOS level ±5.0V (Single +5V power supply possible at self bias use) Supply voltage Item Min. Typ. +5V –5V Clock input CMOS compatible Pulse width TCW1 TCW0 Max. Unit 185 20 mA 10ns (min) 10ns (min) – 17 – BLK CXD2302Q Analog Output (CXD1171M) Item Analog output (RL > 10kΩ) Min. Typ. Max. Unit 1.8 2.0 2.1 V Output Format (CXD2302Q) The table shows the output format of AD Converter. Analog input voltage Step VRT : : : : VRB 0 : 127 128 : 255 Digital output code MSB LSB 1 1 1 1 0 0 0 1 1 0 0 0 1 1 : 0 0 1 1 : 0 0 1 1 1 0 1 0 1 0 1 0 0 0 Timing Chart Analog input Tpw0 External clock Tpw1 Tdc AD clock tPD (AD) AD output tDD Latch output DA input ts th DA clock tPD (DA) DA output Item Symbol Min. Typ. Max. Unit Clock High time TPW1 10 ns Clock Low time TPW0 10 ns Clock Delay Tdc Data delay AD tPD (AD) tDD tS th tPD (DA) Data delay (latch) Settling time Hold time Data delay DA 24 9 ns ns 17 ns 5 ns 10 ns 10 – 18 – ns R1 100k C1 470µ VIDEO INPUT VR1 2k Q3 R6 510 R4 510 VRB ADJUST VR2 2k Q1 R2 75 Q2 CLAMP VOLTAGE ADJUST AVSS C2 R3 10µ 33 AVDD AVSS R5 510 AVDD VRT ADJUST C4 0.01 C3 0.01 47µ VR3 20k C5 0.1 OUTPUT GAIN ADJUST VR4 20k V out SW3 SW2 (R) R7 200 (16R) R8 3.3k –5V +5V GND AVDD DVDD – 19 – BLK 9 15 AVSS 16 AVSS D4 5 D3 4 20 AVDD 21 IO D0 1 24 DVDD D6 9 D5 8 D4 7 20 AVDD 21 AVDD 22 VIN D0 3 28 CLE 0.01 OE 1 27 VREF DVSS 2 26 VRB D1 4 D2 5 24 AVSS 25 D3 23 AVSS 6 D7 10 DVDD DVSS DVDD DVDD 11 18 VRT 19 13 CLK 12 17 NC 14 13 12 11 10 9 8 16 15 14 12 13 11 10 0.01µ 74S174 (LATCH) 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 16 0.01µ 74S174 (LATCH) 0.01µ 15 14 13 12 11 10 9 16 NC DVDD CLK DVDD CLK 14 DVSS 15 CLP SW1 D1 2 23 NC D2 3 D5 6 19 AVDD 22 IO D6 7 18 VREF D7 8 CLK 10 14 NC 17 IREF NC 12 DVSS 11 13 NC DVDD 74S04 OR 74HC04 (INV BUFFER) CMOS ADC/DAC Peripheral Circuit Board (Main Board) DVSS CLEAR DVSS CLEAR DVSS OE SEL CLE BLK SYNC OSC SWITCH EXT/INT OSC out R9 75 VR5 20k 47µ R10 75 SYNC INT (RIN = 75Ω) EXTERNAL CLOCK INPUT 8 7 DVSS 1 0.01µ 14 DVDD CXD2302Q CXD2302Q CMOS ADC/DAC Peripheral Circuit Board (Sub Board) CLP 15 14 13 NC 16 16 15 NC 17 14 13 12 11 10 9 JT 12 CLK 18 17 8 11 DVDD VRT 19 18 7 10 D7 AVDD 20 19 6 9 D6 5 8 D5 21 4 7 D4 22 3 6 D3 AVSS 24 23 2 5 D2 VRB 25 24 1 4 D1 3 D0 2 DVSS 1 OE 12 NC 11 DVSS C3 0.1µ AVDD 21 20 CXD2302Q VIN 22 AVSS 23 C5 C4 26 25 26 JB 27 28 29 30 31 32 C2 0.1µ VREF 27 CLE 28 C1 0.01µ NC 13 13 12 NC 14 14 11 AVSS 15 15 10 10 CLK AVSS 16 16 9 9 BLK 17 8 8 D7 7 7 D6 IREF 17 VREF 18 C3 C2 18 C4 CXD1171M AVDD 19 19 6 6 D5 AVDD 20 20 5 5 D4 IO 21 21 4 4 D3 IO 22 22 3 3 D2 NC 23 23 2 2 D1 DVDD 24 24 1 1 D0 C1 – 20 – CXD2302Q List of Parts resistance R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 VR1 VR2 VR3 VR4 VR5 100K 75Ω 75Ω 510Ω 510Ω 510Ω R = 200 18R ≈ 3.3K 75Ω 75Ω 2K 2K 20K 20K 20K transistor Q1 2SC2785 Q2 2SC2785 Q3 2SC2785 IC IC1 IC2 IC3 74S174 74S174 74S04 oscillator OSC others connector BNC071 SW AT1D2M3 capacitance C1 470µF/6.3V (chemical) C2 10µF/16V (chemical) C3 0.01µF C4 0.01µF C5 0.1µF C6 0.1µF C7 0.1µF C8 0.1µF C9 0.1µF C10 0.1µF C11 47µF/10V (chemical) C12 47µF/10V (chemical) C13 47µF/10V (chemical) C14 0.1µF Adjustment 1. Vref adjustment (VR1, VR2) Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2. When self bias is used, there is no need for adjustment. Reference voltage is set through self bias delivery. 2. Setting of clamp reference voltage (VR3) Clamp reference voltage is set. 3. DAC output full scale adjustment (VR4) Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is adjusted to approx. 2V. 4. Sync (clamp) pulse interface (VR5) This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V. – 21 – CXD2302Q 5. OE, SEL, Sync, BLK, CLE, Sync INT The following pins are set on the main board: OE, Sync, CLE, Sync INT (CXD2302Q), BLK (CXD1171M) and SEL (not used). For the pins function, refer to the Pin Description. The difference between Sync pin and Sync INT pin is that a pulse above 3.5Vp-p should be input to Sync INT pin. The pulse threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line between Sync and Sync INT pin. At the PCB shipment the main board pins are set as follows. • OE : Low (A/D output ON) • SEL : Low • Sync : Line junction Sync INT pin • CLE : Low (Clamp function ON) • BLK : Low (Blanking OFF) 6. Clamp pulse input method Directly input the clamp pulse as shown in Application Circuit example I-1. As SW1 is set to direct input at the PCB shipment, use it in this position. Points on the PCB Pattern Layout 1. Set the layout not to have Digital current flow into Analog GND (For 1, see p.24 “Component side diagram”.). 2. The C2 and C3 capacitors for the CXD2302Q sub board serve the important role of bringing out ICs full performance. Connect over 0.1µF (ceramic) capacitors with good high frequency characteristics as close to the IC as possible. 3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage supply source. Keeping ADC’s DVSS (For 2, see p.24 “Component side diagram”.) as close to the voltage supply source as possible will provide better characteristics. That is, a layout where ADC is close to the voltage supply source, is recommended. 4. ADC samples analog signals at the clock falling edge. Accordingly it is important that clocks supplied to ADC do not have any jitter. 5. The PCB layout shows ADC and DAC’s Analog GND independently from the voltage supply source. The layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual board, common use will not cause any problems. – 22 – CXD2302Q Notes on Operation 1. Reference voltage Shorting AVDD and VRTS, AVSS and VRBS will activate the self-bias function that generates VRT = about 2.6V and VRB=about 0.5V. On the PCB, either self bias or the external reference voltage can be selected depending on the junction method of the jumper line. At shipment from the factory, reference voltage is provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (VRT – VRB) to above 1.8Vp-p. 2. Clock input There are 2 modes for the PCB clock input 1) Provided from the external signal generator. (External clock) 2) Using the crystal oscillator (built-in clock driver). (Internal clock) The 2 modes are selected using the switch on the PCB. 3. The 2 Latch ICs (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is, operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an example layout of Digital signal processing IC. Use the Latch IC output when the ADC output data is used. 4. When clamp is not used Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2 on the main board and DC voltage on the ADC side of C2 turns to about (VRT+VRB)/2. To transfer DC elements of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can also be used as buffer. Use the open space for the bias circuit. 5. Clamp pulse latch On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to CLP pin. However, the latch is incorporated in CLP pin of the CXD2302Q, so that the external latch is not required. 6. Peripheral through hole There is a group of through holes on the Analog input, output and Logic. There are to be used when mounting additional circuits to the PCB. Use when necessary. The connector hole on DAC part is used to mount the test chassis mount jack. – 23 – CXD2302Q Silk Side Component Side Soldering Side (Diagram seen from the component side) – 24 – CXD2302Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 ± 0.12 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP032-P-0707-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE – 25 – 0.50 8