SONY CXD3422GA

CXD3422GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
The CXD3422GA is a timing generator and CCD
signal processor IC for the ICX284, ICX432/434
CCD image sensor.
Features
• Timing generator functions
• Horizontal drive frequency 18 to 24.3MHz
(Base oscillation frequency 36 to 48.6MHz)
• Supports frame readout/draft (sextuple speed)/
AF (Auto focus drive) (ICX432 mode)
• Supports frame readout/draft (quadruple speed)/
AF (Auto focus drive) (ICX434 mode)
• High-speed/low-speed shutter function
• Horizontal and vertical drivers for CCD image
sensor
• CCD signal processor functions
• Correlated double sampling
• Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
• 10-bit A/D converter
• Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
96 pin LFLGA (Plastic)
Absolute Maximum Ratings
• Supply voltage
VDDa, VDDb, VDDc, VDDd VSS – 0.3 to +7.0
V
VDDe, VDDf, VDDg
VSS – 0.3 to +4.0
V
VL
–10.0 to VSS
V
VH
VL – 0.3 to +26.0
V
• Input voltage (analog)
VSS – 0.3 to VDD + 0.3 V
VIN
• Input voltage (digital)
VI
VSS – 0.3 to VDD + 0.3 V
• Output voltage
VO1
VSS – 0.3 to VDD + 0.3 V
VO2
VL – 0.3 to VSS + 0.3 V
VO3
VL – 0.3 to VH + 0.3
V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +125
°C
Applications
Digital still cameras
Applicable CCD Image Sensors
ICX284 (Type 1/2.7, 2020K pixels)
ICX432 (Type 1/2.7, 3240K pixels)
ICX434 (Type 1/3.2, 2020K pixels)
Recommended Operating Conditions
• Supply voltage
VDDa, VDDb, VDDc, VDDd,
VDDe, VDDf, VDDg
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
• Operating temperature
Topr
–20 to +75
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02125-PS
CXD3422GA
DVSS2
E2 F2 F3
DVSS1
B5
DVDD2
DVDD1
A3 A4 B4
DVSS3
TEST5
TEST3
A5 C4
SEN2
SSI2
SCK2
AVSS5
AVSS4
AVSS3
AVDD4
B8 B6 B9 A6 C5
TEST4
A1 A2 C7 D8 D7
AVDD3
C1
C2
C3
NC
NC
Block Diagram
E3 F1
C4 C8
AVDD5 A9
Serial Port
Register
DAC
AVSS6 A8
C7 B7
C8 A7
B3
D0 (LSB)
B2
D1
B1
D2
C3 D3
C9 C6
C2 D4
CDS
CCDIN C9
ADC
PGA
Latch
C1 D5
AVDD1 E9
D3 D6
AVDD2 E8
D2 D7
AVSS1 D9
D1 D8
AVSS2 E7
XSHPI
F9
XSHDI
F8
PBLKI
F7
XSHP
G9
XSHD
G8
PBLK
G7
E1
Black Level
Auto Zero
Dummy Pixel
Auto Zero
Preblanking
G1
G2
G3
H1
H2
VDD4 H8
H3
VDD2 K7
J3
RG K8
VSS2 K9
L1
VDD3 H9
K1
Pulse Generator
H1 J8
J1
H2 J9
VSS3 J7
1/2
ID/EXP N9
Latch
D9 (MSB)
ADCLKI
CLPOBI
CLPDMI
ADCLK
CLPOB
CLPDM
VSS4
OSCI
OSCO
CKI
J2
CKO
K2
MCKO
Selector
N8 SNCSL
Serial Port
Register
M1 SCK1
WEN/FLD M9
L2
VH L5
V Driver
SSI1
N1 SEN1
VM M3
VL M6
–2–
SSG
K3 L7
N3
VDD5
VSS5
VSS1
L9
VD
N2 M2
VDD1
L8
HD
SUB
V6/V4
V5A/V3A
V3B/V1B
V3A/V1A
V1/NC
V2/NC
V5B/V3B
TEST2
L4 M5 N5 M4 L6 N6 N4 N7 M7
V4/V2
L3 M8
RST
H7
TEST1
Selector
SSGSL
CXD3422GA
Pin Configuration (Top View)
A
NC
NC
SCK2
SSI2
TEST3
AVSS4
C8
AVSS6
AVDD5
B
D2
D1
D0
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
C
D5
D4
D3
TEST4
AVSS5
C9
C3
C4
CCDIN
D
D8
D7
D6
C1
C2
AVSS1
E
D9
DVDD1
DVSS1
AVSS2
AVDD2
AVDD1
F
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
G
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
H
ADCLK
CLPOB
CLPDM
TEST1
VDD4
VDD3
J
CKI
CKO
VSS4
VSS3
H1
H2
K
OSCO
MCKO
VDD5
VDD2
RG
VSS2
L
OSCI
SSI1
TEST2
V4 (V2)
VH
V3A (V1A)
VSS1
SSGSL
VDD1
M
SCK1
VD
VM
V2 (NC)
V5B (V3B)
VL
SUB
RST
WEN/FLD
N
SEN1
HD
VSS5
V5A (V3A)
V1 (NC)
V3B (V1B)
V6 (V4)
SNCSL
ID/EXP
1
2
3
4
5
6
7
8
9
Note) The symbol in parenthesis is for ICX434 mode.
–3–
CXD3422GA
Pin Description
Pin
No.
Symbol
I/O
Description
A1
NC
—
No connected. (Open)
A2
NC
—
No connected. (Open)
A3
SCK2
I
CCD signal processor block serial interface clock input. (Schmitt trigger)
A4
SSI2
I
CCD signal processor block serial interface data input. (Schmitt trigger)
A5
TEST3
I
CCD signal processor block test input 3. Connect to DVSS.
A6
AVSS4
—
CCD signal processor block analog GND.
A7
C8
—
Capacitor connection.
A8
AVSS6
—
CCD signal processor block analog GND.
A9
AVDD5
—
CCD signal processor block analog power supply.
B1
D2
O
ADC output.
B2
D1
O
ADC output.
B3
D0
O
ADC output (LSB).
B4
SEN2
I
CCD signal processor block serial interface enable input. (Schmitt trigger)
B5
TEST5
I
CCD signal processor block test input 5. Connect to DVDD.
B6
AVDD4
—
CCD signal processor block analog power supply.
B7
C7
—
Capacitor connection.
B8
AVDD3
—
CCD signal processor block analog power supply.
B9
AVSS3
—
CCD signal processor block analog GND.
C1
D5
O
ADC output.
C2
D4
O
ADC output.
C3
D3
O
ADC output.
C4
TEST4
I
CCD signal processor block test input 4. Connect to DVSS.
C5
AVSS5
—
CCD signal processor block analog GND.
C6
C9
—
Capacitor connection.
C7
C3
—
Capacitor connection.
C8
C4
—
Capacitor connection.
C9
CCDIN
I
CCD output signal input.
D1
D8
O
ADC output.
D2
D7
O
ADC output.
D3
D6
O
ADC output.
D7
C1
—
Capacitor connection.
D8
C2
—
Capacitor connection.
D9
AVSS1
—
CCD signal processor block analog GND.
E1
D9
O
ADC output (MSB).
E2
DVDD1
—
CCD signal processor block digital power supply. (Power supply for ADC)
E3
DVSS1
—
CCD signal processor block digital GND. (GND for ADC)
E7
AVSS2
—
CCD signal processor block analog GND.
–4–
CXD3422GA
Pin
No.
Symbol
I/O
Description
E8
AVDD2
—
CCD signal processor block analog power supply.
E9
AVDD1
—
CCD signal processor block analog power supply.
F1
DVSS2
—
CCD signal processor block digital GND.
F2
DVSS3
—
CCD signal processor block digital GND.
F3
DVDD2
—
CCD signal processor block digital power supply.
F7
PBLKI
I
Pulse input for horizontal and vertical blanking period pulse cleaning.
(Schmitt trigger)
F8
XSHDI
I
CCD data level sample-and-hold pulse input. (Schmitt trigger)
F9
XSHPI
I
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
G1
ADCLKI
I
Clock input for analog/digital conversion. (Schmitt trigger)
G2
CLPOBI
I
CCD optical black signal clamp pulse input. (Schmitt trigger)
G3
CLPDMI
I
CCD dummy signal clamp pulse input. (Schmitt trigger)
G7
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning.
G8
XSHD
O
CCD data level sample-and-hold pulse output.
G9
XSHP
O
CCD precharge level sample-and-hold pulse output.
H1
ADCLK
O
Clock output for analog/digital conversion.
Logical phase adjustment possible using the serial interface data.
H2
CLPOB
O
CCD optical black signal clamp pulse output.
Horizontal and vertical OB pattern charge possible using the serial interface data.
H3
CLPDM
O
CCD dummy signal clamp pulse output.
H7
TEST1
I
Timing generator block test input 1.
Normally fix to GND. (With pull-down resistor)
H8
VDD4
—
Timing generator block digital power supply. (Power supply for CDS block)
H9
VDD3
—
Timing generator block digital power supply. (Power supply for H1/H2)
J1
CKI
I
Inverter input.
J2
CKO
O
Inverter output.
J3
VSS4
—
Timing generator block digital GND.
J7
VSS3
—
Timing generator block digital GND.
J8
H1
O
CCD horizontal register clock output.
J9
H2
O
CCD horizontal register clock output.
K1
OSCO
O
Inverter output for oscillation. When not used, leave open or connect a capacitor.
K2
MCKO
O
System clock output for signal processor IC.
K3
VDD5
—
Timing generator block digital power supply. (Power supply for common logic block)
K7
VDD2
—
Timing generator block digital power supply. (Power supply for RG)
K8
RG
O
CCD reset gate pulse output.
K9
VSS2
—
Timing generator block digital GND.
L1
OSCI
I
Inverter input for oscillation. When not used, fix to low.
L2
SSI1
I
Timing generator block serial interface data input. Schmitt trigger input.
–5–
CXD3422GA
Pin
No.
Symbol
I/O
Description
L3
TEST2
I
Timing generator block test input 2.
Normally fix to GND. (With pull-down resistor)
L4
V4 (V2)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
L5
VH
—
Timing generator block 15.0V power supply. (Power supply for vertical driver)
L6
V3A (V1A)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
L7
VSS1
—
Timing generator block digital GND.
L8
SSGSL
L9
VDD1
—
M1
SCK1
I
M2
VD
I/O
Vertical sync signal input/output.
M3
VM
—
Timing generator block GND. (GND for vertical driver)
M4
V2 (NC)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
M5
V5B (V3B)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
M6
VL
—
Timing generator block –7.5V power supply. (Power supply for vertical driver)
M7
SUB
O
CCD electric shutter pulse.
I
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid (With pull-down resistor)
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block serial interface clock input.
Schmitt trigger input.
M8
RST
I
Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input.
M9
WEN/FLD
O
Memory write timing pulse output/field discrimination pulse output.
Switching possible using the serial interface data. (Default: WEN output)
N1
SEN1
I
Timing generator block serial interface strobe input.
Schmitt trigger input.
N2
HD
I/O
Horizontal sync signal input/output.
N3
VSS5
—
Timing generator block digital GND.
N4
V5A (V3A)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
N5
V1 (NC)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
N6
V3B (V1B)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
N7
V6 (V4)
O
CCD vertical register clock output. The symbol in parenthesis is for ICX434 mode.
N8
SNCSL
I
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync (With pull-down resistor)
N9
ID/EXP
O
Vertical direction line identification pulse output/Exposure time idenfication pulse
output.
Switching possible using the serial interface data. (Default: ID output)
–6–
CXD3422GA
Electrical Characteristics
Timing Generator Block Electrical Characteristics
DC Characteristics
Item
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1
VDD2
VDDa
3.0
3.3
3.6
V
Supply voltage 2
VDD3
VDDb
3.0
3.3
3.6
V
Supply voltage 3
VDD4
VDDc
3.0
3.3
3.6
V
Supply voltage 4
VDD1, VDD5
VDDd
3.0
3.3
3.6
V
Input
voltage 1∗1
RST, SSI1,
SCK1, SEN1
VI+
Input
voltage 2∗2
TEST1, TEST2, VIH1
SNCSL, SSGSL VIL1
0.7VDDd
VIH2
0.8VDDd
Input/output
voltage
VD, HD
VI–
VOL1
Pull-in current where IOL = 2.4mA
VOH2
Feed current where IOH = –14.0mA VDDb – 0.8
VOL2
Pull-in current where IOL = 9.6mA
VOH3
Feed current where IOH = –3.3mA
VOL3
Pull-in current where IOL = 2.4mA
Output
voltage 2
RG
Output
voltage 3
XSHP, XSHD,
VOH4
PBLK,
CLPOB,
CLPDM,
VOL4
ADCLK
Output
voltage 4
CKO
Output
voltage 5
MCKO
Output
voltage 6
ID/EXP,
WEN/FLD
Output
current 2
V1, V2,
V3A, V3B,
V4, V5A,
V5B, V6
SUB
Feed current where IOH = –3.3mA
VDDd – 0.8
VOH5
Feed current where IOH = –6.9mA
VOL5
Pull-in current where IOL = 4.8mA
VOH6
Feed current where IOH = –3.3mA
VOL6
Pull-in current where IOL = 2.4mA
VOH7
Feed current where IOH = –2.4mA
VOL7
Pull-in current where IOL = 4.8mA
IOL
V1, V2, V3A/B, V4, V5A/B, V6
= –8.25V
IOM1
V1, V2, V3A/B, V4, V5A/B, V6
= –0.25V
IOM2
V1, V3A/B, V5A/B = 0.25V
IOH
V1, V3A/B, V5A/B = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
∗1 This input pin is a schmitt trigger input.
∗2 These input pins are with pull-down resistor in the IC.
Note) The above table indicates the condition for 3.3V drive.
–7–
V
V
0.4
V
V
0.4
VDDa – 0.8
V
V
0.4
VDDc – 0.8
Pull-in current where IOL = 2.4mA
V
V
0.2VDDd
Feed current where IOH = –1.2mA
V
V
0.3VDDd
VOH1
H1, H2
V
0.2VDDd
VIL2
Output
voltage 1
Output
current 1
0.8VDDd
V
V
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
10.0
V
mA
–5.0
5.0
mA
mA
–7.2
5.4
mA
mA
–4.0
mA
CXD3422GA
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input
voltage
OSCI
Output
voltage
OSCO
Feedback
resistor
Oscillation
frequency
Symbol
(Within the recommended operating conditions)
Conditions
Min.
LVth
Typ.
Max.
VDDd/2
VIH
V
0.7VDDd
V
VIL
0.3VDDd
VOH
Feed current where IOH = –3.6mA
VOL
Pull-in current where IOL = 2.4mA
OSCI,
OSCO
RFB
VIN = VDDd or VSS
OSCI,
OSCO
f
VDDd – 0.8
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Symbol
Logical Vth
LVth
Input
voltage
VIH
CKI
Input
amplitude
Conditions
Min.
Typ.
VDDd/2
V
0.3VDDd
fmax 50MHz sine wave
Unit
V
0.7VDDd
VIL
VIN
Max.
0.3
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source.
Input amplitude is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
(VH = 15.0V, VM = GND, VL = –7.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
–8–
CXD3422GA
Switching Waveforms
TTMH
TTHM
VH
V1 (V3A, V3B, V5A, V5B)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V2 (V4, V6)
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–9–
R1
C2
C2
C1
C2
C2
R2
C1
C2
C1
C2
3300pF
30Ω
R1
C1
C2
C2 C2
C1 C2
C1
R1
C2
C1
C2
R1
C2
R1
C2
R2
560pF
10Ω
C3
C3
CKI
CKO
VDD5
OSCO
OSCI
VDD2
AVSS4
RG
TEST3
VSS2
SSI2
SSI1
NC
MCKO
ADCLK H1
AVDD5
CLPOBI G2
TEST5
M6 VL
AVDD4
CLPDMI G3
CXD3422GA
VDD3
C7
L5 VH
H2
820pF
N5 V1
N9 ID/EXP
N8 SNCSL
L7 VSS1
M7 SUB
N6 V3B
N4 V5A
N3 VM
N2 HD
N1 SEN1
M9 WEN/FLD
M8 RST
L3 TEST2
L6 V3A
M5 V5B
M4 V2
C3 C7
C4 C8
CCDIN C9
D8 D1
D7 D2
D6 D3
C1 D7
C2 D8
AVDD2 E8
DVDD1 E2
DVSS1 E3
DVSS2 F1
AVSS2 E7
AVSS1 D9
AVDD1 E9
ADCLKI G1
DVSS3 F2
M3 VM
DVDD2 F3
M2 VD
PBLKI F7
M1 SCK1
L9 VDD1
SCK2
XSHPI F9
C8
XSHDI F8
AVSS6
L8 SSGSL
AVDD3
N7 V6
C4
8pF
C5
180pF
C6
10pF
A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6
D2
C2
H1
D1
C2
VSS3
D0
R1
VSS4
SEN2
R1
C6
VDD4
AVSS3
L4 V4
E1 D9
C5 C5
TEST1
N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7
C4
CLPDM
D5
–7.5V
C6
CLPOB
D4
+3.3V
VSS4
D3
+15.0V
XSHP
TEST4
VD
CKI
PBLK
HD
VSS5
NC
Serial interface data
XSHD
AVSS5
– 10 –
C9
Measurement Circuit
CXD3422GA
CXD3422GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDd
SSI1
0.2VDDd
0.8VDDd
SCK1
ts1
SEN1
th1
0.2VDDd
ts3
0.8VDDd
SEN1
ts2
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
SSI1 setup time, activated by the rising edge of SCK1
20
ns
th1
SSI1 hold time, activated by the rising edge of SCK1
20
ns
ts2
SCK1 setup time, activated by the rising edge of SEN1
20
ns
ts3
SEN1 setup time, activated by the rising edge of SCK1
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VD
HD
V1A
Enlarged view
HD
0.2VDDd
V1A
ts1
SEN1
th1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal
period during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
SEN1 setup time, activated by the falling edge of HD
0
ns
th1
SEN1 hold time, activated by the falling edge of HD
123
µs
– 11 –
CXD3422GA
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VD
HD
Enlarged view
VD
0.2VDDd
HD
ts1
SEN1
th1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
SEN1 setup time, activated by the falling edge of VD
0
ns
th1
SEN1 hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3422GA at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3422GA and controlled at the rising edge of SEN1. See "Description of Operation".
SEN1
0.8VDDd
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN1
– 12 –
5
Typ.
Max.
Unit
100
ns
CXD3422GA
RST loading characteristics
RST
0.8VDDd
0.2VDDd
tw1
(Within the recommended operating conditions)
Symbol
tw1
Definition
Min.
RST pulse width
Typ.
Max.
35
Unit
ns
VD and HD loading characteristics
VD, HD
0.2VDDd
0.2VDDd
ts1
th1
0.8VDDd
MCKO
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
VD and HD setup time, activated by the rising edge of MCKO
13
ns
th1
VD and HD hold time, activated by the rising edge of MCKO
0
ns
Output variation characteristics
MCKO
0.8VDDd
WEN/FLD,
ID/EXP
tpd1
WEN/FLD and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
20
– 13 –
Typ.
Max.
Unit
60
ns
CXD3422GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics
Item
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Pins
Conditions
Symbol
Min.
Typ. Max. Unit
Supply voltage 1 DVDD1
VDDe
3.0
3.3
3.6
V
Supply voltage 2 DVDD2
VDDf
3.0
3.3
3.6
V
AVDD1,
AVDD2,
Supply voltage 3 AVDD3,
AVDD4,
AVDD5
VDDg
3.0
3.3
3.6
V
Analog input
capacitance
CCDIN
CIN
15
pF
1.8
V
Input voltage
SCK2, SSI2,
VI+
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI, VI–
CLPOBI,
CLPDMI, PBLKI
1.1
V
A/D clock duty
ADCLKI
50
%
Output voltage
D0 to D9
VOH
Feed current where IOH = –2.0mA VDDe – 0.9
VOL
Pull-in current where IOL = 2.0mA
0.4
V
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Analog Characteristics
Item
V
Pins
Conditions
Min.
900
Typ.
Max. Unit
CCDIN input voltage amplitude
VIN
PGA gain = 0dB, output full scale
PGA maximum gain
Gmax
PGA gain setting data = "3FFh"
42
dB
PGA minimum gain
Gmin
PGA gain setting data = "000h"
–6
dB
10
bit
ADC resolution
1100 mV
ADC maximum conversion rate
Fc max
24.3
ADC integral non-linearity error
EL
PGA gain = 0dB
±1.0 ±5.0 LSB
ADC differential non-linearity error
ED
PGA gain = 0dB
±0.5 ±1.0 LSB
Signal-to-noise ratio
SNR
PGA gain = 0dB
CCDIN input voltage clamp level
CLP
CCD optical black signal clamp
level
OB
OBLVL = "8h"
PGA gain = 0dB
– 14 –
MHz
77
dB
1.5
V
32
LSB
CXD3422GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDD
SSI2
0.2VDD
0.8VDD
SCK2
ts1
SEN2
th1
0.2VDD
ts3
0.8VDD
SEN2
ts2
∗ The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise
of SEN2.
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
Definition
Min.
Typ.
Max.
Unit
tp1
SCK2 clock period
100
ns
ts1
SSI2 setup time, activated by the rise of SCK2
30
ns
th1
SSI2 hold time, activated by the rise of SCK2
30
ns
ts2
SCK2 setup time, activated by the rise of SEN2
30
ns
ts3
SEN2 setup time, activated by the rise of SCK2
30
ns
– 15 –
CXD3422GA
CDS/ADC Timing Chart
N
N+1
N+2
N+3
CCDIN
XSHPI
XSHDI
tw1
ADCLKI
DL
D0 to D9
N – 10
N–9
N–8
N–7
∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
(Fc = 24.3MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
tw1
DL
Definition
Min.
ADCLKI clock period
Typ.
41
Max.
Unit
ns
ADCLKI clock duty
50
%
Data latency
9
clocks
Preblanking Timing Chart
PBLKI
11 Clocks
ADCLKI
11 Clocks
All "0"
D0 to D9
– 16 –
CXD3422GA
Description of Operation
Pulses output from the CXD3422GA's timing generator block are controlled mainly by the RST pin and by the
serial interface data. The Pin Status Table is shown below, and the details of serial interface control are
described on page 19 and thereafter.
Pin Status Table
Pin
No.
Symbol
CAM
SLP
STB
RST
Pin
No.
Symbol
CAM
SLP
STB
RST
A1
NC
—
D8
C2
—
A2
NC
—
D9
AVSS1
—
A3
SCK2
—
E1
D9
—
A4
SSI2
—
E2
DVDD1
—
A5
TEST3
—
E3
DVSS1
—
A6
AVSS4
—
E7
AVSS2
—
A7
C8
—
E8
AVDD2
—
A8
AVSS6
—
E9
AVDD1
—
A9
AVDD5
—
F1
DVSS2
—
B1
D2
—
F2
DVSS3
—
B2
D1
—
F3
DVDD2
—
B3
D0
—
F7
PBLKI
—
B4
SEN2
—
F8
XSHDI
—
B5
TEST5
—
F9
XSHPI
—
B6
AVDD4
—
G1
ADCLKI
—
B7
C7
—
G2
CLPOBI
—
B8
AVDD3
—
G3
CLPDMI
—
B9
AVSS3
—
G7
PBLK
ACT
L
L
H
C1
D5
—
G8
XSHD
ACT
L
L
ACT
C2
D4
—
G9
XSHP
ACT
L
L
ACT
C3
D3
—
H1
ADCLK
ACT
L
L
ACT
C4
TEST4
—
H2
CLPOB
ACT
L
L
H
C5
AVSS5
—
H3
CLPDM
ACT
L
L
H
C6
C9
—
H7
TEST1
—
C7
C3
—
H8
VDD4
—
C8
C4
—
H9
VDD3
—
C9
CCDIN
—
J1
CKI
ACT
ACT
ACT
ACT
D1
D8
—
J2
CKO
ACT
ACT
L
ACT
D2
D7
—
J3
VSS4
—
D3
D6
—
J7
VSS3
—
D7
C1
—
J8
H1
L
ACT
– 17 –
ACT
L
CXD3422GA
Pin
No.
Symbol
CAM
SLP
STB
RST
Pin
No.
Symbol
CAM
SLP
STB
RST
ACT
L
L
H
J9
H2
ACT
L
L
ACT
M2
VD∗1
K1
OSCO
ACT
ACT
ACT
ACT
M3
VM
K2
MCKO
ACT
ACT
L
ACT
M4
V2 (NC)
ACT
VM
VM
VM
K3
VDD5
—
M5
V5B (V3B)
ACT
VH
VH
VL
K7
VDD2
—
M6
VL
K8
RG
M7
SUB
ACT
VH
VH
VL
K9
VSS2
M8
RST
ACT
ACT
ACT
L
L1
OSCI
ACT
ACT
ACT
ACT
M9
WEN/FLD
ACT
L
L
L
L2
SSI1
ACT
ACT
ACT
DIS
N1
ACT
ACT
ACT
DIS
L3
TEST2
N2
SEN1
HD∗1
ACT
L
L
H
L4
V4 (V2)
N3
VSS5
L5
VH
N4
V5A (V3A)
ACT
VH
VH
VL
L6
V3A (V1A)
N5
V1 (NC)
ACT
VH
VH
VM
L7
VSS1
N6
V3B (V1B)
ACT
VH
VH
VM
L8
SSGSL
N7
V6 (V4)
ACT
VH
VH
VL
L9
VDD1
N8
SNCSL
ACT
ACT
ACT
ACT
M1
SCK1
N9
ID/EXP
ACT
L
L
L
ACT
L
L
ACT
—
—
ACT
VM
VM
VM
—
ACT
VH
VH
VM
—
ACT
ACT
ACT
ACT
—
ACT
ACT
ACT
DIS
—
—
—
∗1 It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin L5), VM (Pin M3) and VL (Pin M6),
respectively, in the controlled status.
– 18 –
CXD3422GA
Timing Generator Block Serial Interface Control
The CXD3422GA's timing generator block basically loads and reflects the timing generator block serial
interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion
specifies the horizontal period during which V3A/B and V5A/B, etc. take the ternary value.
Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the
rising edge of SEN1.
SSI1
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
SCK1
SEN1
There are two categories of timing generator block serial interface data: CXD3422GA timing generator block
drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 19 –
CXD3422GA
Control Data
Data Symbol
D00
to
D07
CHIP
Chip enable
D08
CTG
Category switching
D09
to
D11
—
—
D12,
MODE
D13
D14,
D15
NTPL
D17
CCD
D18,
D19
SMD
D21
HTSG
D22
to
D30
—
RST
10000001
→ Enabled
Other values → Disabled
All
0
See D08 CTG.
0
—
All
0
See D12 , D13 MODE.
0
—
—
0
Internal SSG function switching∗1
CCD switching∗1
NTSC
PAL
0
ICX432
ICX284/434
0
—
—
—
0
OFF
ON
0
OFF
ON
0
—
—
All
0
WEN
FLD
0
OFF
ON
0
EXP
0
—
D20
Data = 1
—
Drive mode switching
—
D16
Data = 0
Function
Electronic shutter mode switching∗2
HTSG control switching∗2
—
—
D31
FLD
WEN/FLD output switching
D32
FGOB
Wide CLPOB generation switching
D33
EXP
ID/EXP output switching
ID
D34,
PTOB
D35
CLPOB waveform pattern switching
See D34 , D35 PTOB.
All
0
D36,
LDAD
D37
ADCLK logic phase adjustment
See D36 , D37 LDAD.
All
0
D38,
STB
D39
Standby control
See D38 , D39 STB.
All
0
D40
to
D47
—
FL
—
—
∗1 See D12 , D13 MODE.
∗2 See D20 SMD.
– 20 –
—
All
0
CXD3422GA
Shutter Data
Data Symbol
D00
to
D07
CHIP
D08 CTG
Function
Data = 0
Chip enable
Category switching
RST
10000001
→ Enabled
Other values → Disabled
All
0
See D08 CTG.
0
—
0
D09
—
D10
to
D19
SVD
Electronic shutter vertical period
specification
See D10 to D19 SVD.
All
0
D20
to
D31
SHD
Electronic shutter horizontal period
specification
See D20 to D31 SHD.
All
0
D32
to
D41
SPL
High-speed shutter position
specification
See D32 to D41 SPL.
All
0
—
All
0
D42
to
D47
—
—
Data = 1
—
– 21 –
CXD3422GA
Detailed Description of Each Data
Shared data: D08 CTG [Category]
Of the data provided to the CXD3422GA by the timing generator block serial interface, the CXD3422GA loads
D12 and subsequent data to each data register as shown in the table below according to D08 .
D08
Description of operation
0
Loading to control data register
1
Loading to shutter data register
Note that the CXD3422GA can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D12 , D13 MODE [Drive mode]
The CXD3422GA drive mode can be switched as follows. However, the drive mode bits are loaded to the
CXD3422GA and reflected at the falling edge of VD.
D13
D12
Description of operation
0
0
Draft mode (default)
0
1
1
0
Frame mode
AF mode∗1
1
1
Test mode
∗1 The test mode results in ICX284/434 mode.
Draft mode is the pulse elimination drive mode. This is a high frame rate drive mode that can be used for
purposes such as monitoring and moving pictures.
AF mode is the drive mode for applications with an even higher frame rate, and is used for auto focus (AF).
Frame mode is the drive mode in which the data for all lines of the ICX284/432/434 are read.
Control data: D16 NTPL [SSG function switching]
The CXD3422GA internal SSG output pattern can be switched as follows. However, the drive mode bits are
loaded to the CXD3422GA and reflected at the falling edge of VD. The default is "NTSC".
D16
Description of operation
0
NTSC equivalent pattern output (internal SSG)
1
PAL equivalent pattern output (internal SSG)
– 22 –
CXD3422GA
Control data: D17 CCD [Used CCD switching]
This specifies the CCD image sensor to be used. However, like the drive mode bits, the CCD switching bits are
loaded to the CXD3422GA and reflected at the falling edge of VD. The default is "ICX432".
D17
Description of operation
0
ICX432
1
ICX284/ICX434
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
Description of operation
0
Wide CLPOB generation OFF
1
Wide CLPOB generation ON
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
D34
0
0
(Normal)
0
1
(Shifted rearward)
1
0
(Shifted forward)
1
1
(Wide)
Waveform pattern
Control data: D36 , D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is "90°" relative to MCKO.
D37
D36
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3422GA and
control is applied immediately at the rising edge of SEN1.
D39
D38
Symbol
Operating mode
X
0
CAM
Normal operating mode
0
1
SLP
Sleep mode
1
1
STB
Standby mode
See the Pin Status Table for the pin status in each mode.
– 23 –
CXD3422GA
Control data/shutter data: [Electronic shutter]
The CXD3422GA realizes various electronic shutter functions by using control data D20 SMD and D21
HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below. These modes are switched using control data D20 SMD.
D20
Description of operation
0
Electronic shutter stopped mode
1
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB
D31
LSB
D30 D29 D28 D27
X
0
↓
1
0
1
1
D26 D25 D24 D23
1
↓
C
0
0
0
D22 D21 D20
0
↓
3
1
1
→ SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
Data
Description
SVD
D10 to D19
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
SHD
D20 to D31
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
SPL
D32 to D41
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
Note) The bit data definition area is assured in terms of the CXD3422GA functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD × (1V period) + {(number of HD per 1V) – (SHD + 1)} × (1H period)
+ (distance from SUB to SG during the readout period)
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
– 24 –
CXD3422GA
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
01
01
SVD
002h
000h
SHD
10Fh
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
000
001
002
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
1
1
SPL
001h
000h
SVD
002h
000h
SHD
10Fh
0A3h
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
– 25 –
CXD3422GA
[HTSG control mode]
This mode controls the ternary level outputs of V1,V3A/B,V5A/B (readout pulse block) using D21 HTSG.
D21
Description of operation
0
Readout pulse (SG) normal operation
1
HTSG control mode
VD
V1A
SUB
VCK
WEN
EXP
HTSG
0
1
0
SMD
1
0
1
Exposure time
[EXP pulse]
The ID/EXP pin (Pin N9) output can be switched between the ID pulse or the EXP pulse using D33 EXP.
The default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure
time when it is high. In principle, the transition points are the last SUB pulse falling edge and the readout
pulse falling edge, that is to say from the time the charge is completely discharged until transfer ends.
However, when the readout pulse timing differs within the same readout portion such as in draft mode, the
average value is used. Then, when there is no SUB pulse in the next field, the readout pulse falling edge is
defined as the start position, but in this case the transition points overlap and disappear, so a tentative start
position is defined.
This is shown below.
[ICX432]
[ICX284/
434]
SG↓
Tentative start position
Frame mode
1460
1480
Draft/AF mode
1682
1784
A: 1071
1091
B: 1175
1195
1123
1175
Frame mode
Draft mode
See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation.
– 26 –
ID/EXP
CLPDM
CLPOB
PBLK
CCD
OUT
WEN/FLD
– 27 –
V6
V5B
V5A
V4
V3B
V3A
V2
V1
SUB
HD
VD
[D]
588 1
High-speed sweep block
[A]
43
1
1549
1546
564
588 1
High-speed sweep block
[B]
43
B Field
564
588 1
High-speed sweep block
[C]
43
C Field
• ICX432
Frame mode
1548
1545
1236
9
6
3
8
5
1547
8
5
2
7
4
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to (high, low, low) in the horizontal periods of each readout portion (A, B, C).
∗ WEN/FLD of this chart shows WEN.
∗ The shaded portion of CLPOB shows the range over which the wide CLPOB can be set by the serial interface data.
∗ VD of this chart is indicated in NTSC equivalent pattern 587H (1H: 2760ck) + 1500ck units. For PAL equivalent pattern, it is 704H + 960ck units.
565
A Field
1550
Applicable CCD image sensor
2
MODE
6
1
3
Chart-A1 Vertical Direction Timing Chart
CXD3422GA
4
WEN/FLD
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V6
V5B
V5A
V4
V3B
263
1549
1544 1546
1537 1541
1532 1534
1525 1527
1549
1537 1541
1544 1546
1532 1534
270 1
[E]
3
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to low in the horizontal periods of each readout portion (E).
∗ WEN/FLD of this chart shows WEN.
∗ The shaded portion of CLPOB shows the range over which the wide CLPOB can be set by the serial interface data.
∗ VD of this chart is indicated in NTSC equivalent pattern 269H (1H: 3004ck) + 2734ck units. For PAL equivalent pattern, it is 323H + 1708ck units.
5
1
V3A
10
8
V2
[E]
17
13
V1
22
20
3
29
25
SUB
270 1
30
28
263
5
HD
6
4
6
4
VD
10
1
• ICX432
17
8
Draft mode
22
13
Applicable CCD image sensor
29
20
MODE
30
25
– 28 –
28
Chart-A2 Vertical Direction Timing Chart
CXD3422GA
WEN/FLD
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V6
V5B
V5A
V4
V3B
V3A
V2
V1
SUB
HD
High-speed sweep block
135 1
[E]
3
[F]
Frame shift block
27
[G]
High-speed sweep block
135 1
[E]
3
[F]
Frame shift block
27
• ICX432
AF mode
123
Applicable CCD image sensor
MODE
6
1525 1527
488 490
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to high in the horizontal periods of each readout portion (E).
∗ WEN/FLD of this chart shows WEN.
∗ The shaded portion of CLPOB shows the range over which the wide CLPOB can be set by the serial interface data.
∗ VD of this chart is indicated in NTSC equivalent pattern 134H (1H: 3004ck) + 2869ck units. For PAL equivalent pattern, it is 161H + 2356ck units.
In addition, for PAL equivalent pattern, the high-speed sweep block starts from 150H.
[G]
123
481 485
VD
6
4
– 29 –
4
Chart-A3 Vertical Direction Timing Chart
CXD3422GA
– 30 –
5
20
50
44
52
52
52
100
140
140
135
140
182
200
224
266
308
300
350
392
400
434
476
518
500
Frame mode
MODE
560
602
600
674
670
646 670
644
672
676
680
700
800
900
• ICX432
1000
Applicable CCD image sensor
These timings can be switched by the serial interface data.
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-A1.
∗ CLPOB also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-A1.
WEN/FLD
ID/EXP
CLPDM
CLPOB (wide)
CLPOB
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HD
(2760)
0
Chart-A4 Horizontal Direction Timing Chart
CXD3422GA
– 31 –
WEN/FLD
ID/EXP
CLPDM
CLPOB (wide)
CLPOB
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HD
20
50
44
52
52
52
100
140
140
135
140
171
202
200
233
264
295
300
326
357
388
419
400
450
481
512
500
543
574
605
600
636
667
698
700
729
760
791
800
822
853
890 914
918
914
888
900
1000
• ICX432
Draft/AF mode
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-A2 and A3.
∗ CLPOB also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-A2 and A3.
These timings can be switched by the serial interface data.
5
(3004)
0
Applicable CCD image sensor
MODE
916
920
924
Chart-A5 Horizontal Direction Timing Chart
CXD3422GA
– 32 –
5
52
52
100
135
140
140
158
176
158
176
#1
230
284
#2
320
302
320
302
300
284
266
266
248
248
230
212
194
212
194
200
338
356
338
356
374
392
374
392
#3
428
410
428
410
400
446
446
#1039
1970
1952
2042
2024
#1040
2060
2042
2024
2006
1988
2006
1988
1970
1952
5
52
52
100
135
140
182
200
224
• ICX432
Frame mode
(2760)
0
Applicable CCD image sensor
MODE
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
WEN/FLD
ID/EXP
CLPDM
CLPOB
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HD
(2760)
0
Chart-A6 Horizontal Direction Timing Chart
(High-speed sweep: D)
CXD3422GA
– 33 –
WEN/FLD
ID/EXP
CLPDM
CLPOB
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HD
52
52
100
135
140
171
202
200
233
264
295
300
326
357
388
419
400
450
481
512
500
#1
543
574
605
600
636
667
698
700
729
760
791
800
822
853
884
888
900
915
946
977
1039
#2
1008
1000
• ICX432
AF mode
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ Frame shift of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 24H 1096ck (#78).
5
(3004)
0
Applicable CCD image sensor
MODE
916
920
924
Chart-A7 Horizontal Direction Timing Chart
(Frame shift: F)
CXD3422GA
– 34 –
5
52
52
100
140
135
140
#1
392
#2
596
704
800
#3
896
992
1052
1040
1028
1004
1016
1000
980
968
956
944
932
920
908
888
900
884
872
860
848
836
824
812
800
788
776
764
752
740
728
716
700
692
680
668
656
644
632
620
608
600
584
572
560
548
536
524
512
500
500
488
476
464
452
440
428
416
404
400
380
368
356
344
332
320
308
296
300
284
272
260
248
236
224
212
200
188
176
164
152
200
• ICX432
AF mode
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ High-speed sweep of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 133H 2932ck (#114).
WEN/FLD
ID/EXP
CLPDM
CLPOB
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HD
(3004)
0
Applicable CCD image sensor
MODE
916
920
924
Chart-A8 Horizontal Direction Timing Chart
(High-speed sweep: G)
CXD3422GA
V2
V1
– 35 –
V2
V1
V6
V5A/B
V4
V3A/B
B Field
V6
V5A/B
V4
V3A/B
A Field
HD
[B]
[A]
(2760)
0
392
266
224
182
140
1546
1502
1460
1420
1380
1338
1296
1254
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
(2760)
0
308
• ICX432
350
Frame mode
434
Applicable CCD image sensor
476
MODE
518
Chart-A9a Horizontal Direction Timing Chart
CXD3422GA
602
560
V2
V1
V6
V5A/B
V4
V3A/B
C Field
HD
[C]
(2760)
0
392
266
224
182
140
1460
1420
1380
1338
1296
1254
1212
1170
1128
1086
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
(2760)
0
308
• ICX432
350
Frame mode
434
Applicable CCD image sensor
476
MODE
518
Chart-A9b Horizontal Direction Timing Chart
CXD3422GA
– 36 –
602
560
– 37 –
[E]
(3004)
0
481
450
357
326
295
264
233
202
171
140
1908
1877
1846
1815
1784
1744
1704
1673
1642
1611
1580
1540
1500
1469
1438
1407
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
V6
V5B
V5A
V4
V3B
V3A
V2
V1
HD
(3004)
0
388
• ICX432
419
Draft/AF mode
574
543
512
Applicable CCD image sensor
605
MODE
636
Chart-A10 Horizontal Direction Timing Chart
CXD3422GA
729
698
667
SUB
000
000
1
050h
MODE
SMD
SHR
B
050h
1
000
B
C
Close
000h
0
010
C (1st)
000h
0
010
C (2nd)
000h
0
010
C (3rd)
050h
1
000
Open
050h
1
000
D
• ICX432
Draft → Frame → Draft
D
Applicable CCD image sensor
MODE
∗ This chart is a driving timing chart example of electronic shutter normal operation.
∗ Data exposed at B includes a blooming component. For details, see the CCD image sensor data sheet.
∗ The CXD3422GA does not generate the pulse to control mechanical shutter operation.
∗ The drive mode and the electronic shutter data are not switched at the same timing.
050h
1
A
A
CCD OUT
Mechanical
shutter
– 38 –
V6
V5B
V5A
V4
V3B
V3A
V2
V1
VD
Chart-A11 Vertical Direction Sequence Chart
CXD3422GA
– 39 –
[C] High-speed sweep block
650 1
[A]
25
31
[C]
650 1
High-speed sweep block
[B]
24
6
4
2
1235
1233
1231
1229
1227
1225
27
17
15
13
11
9
7
5
3
9
7
5
3
1
1236
1234
1232
1230
1228
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to (high, low) in the horizontal periods of each readout portion (A, B).
∗ WEN/FLD of this chart shows WEN.
∗ VD of this chart is indicated in NTSC equivalent pattern 650H (1H: 1848ck) units. For PAL equivalent pattern, it is 779H + 408ck units.
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
WEN/FLD
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
1
VD
31
10
B Field
2
A Field
19
• ICX434
21
Frame mode
23
Applicable CCD image sensor
25
MODE
8
6
4
8
Chart-B1 Vertical Direction Timing Chart
CXD3422GA
12
10
– 40 –
WEN/FLD
ID/EXP
CLPDM
CLPOB
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
325 1
16
325 1
[D]
12
16
7
9
4
1231
1226
1223
1218
1215
1210
1207
1202
63
58
42
39
34
31
26
23
18
15
10
7
2
9
4
1234
1231
1226
1223
1218
1215
1210
1207
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to high in the horizontal periods of each readout portion (D).
∗ WEN/FLD of this chart shows WEN.
∗ VD of this chart is indicated in NTSC equivalent pattern 325H (1H: 1848ck) units. For PAL equivalent pattern, it is 389H + 1128ck units.
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
[D]
12
2
VD
47
• ICX434
50
Draft mode
55
Applicable CCD image sensor
1234
MODE
26
23
18
15
10
Chart-B2 Vertical Direction Timing Chart
CXD3422GA
34
31
CLPOB
WEN/FLD
ID/EXP
CLPDM
CLPOB (wide)
– 41 –
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
19
45
51
50
56
56
56
72
88
88
104
104
104
100
120
136
152
152
168
190
188
200
214
216
214
These timings can be switched by the serial interface data.
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
250
• ICX434
Frame mode
150
Applicable CCD image sensor
MODE
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-B1.
∗ CLPOB also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-B1.
(1848)
0
Chart-B3 Horizontal Direction Timing Chart
CXD3422GA
CLPOB
WEN/FLD
ID/EXP
CLPDM
CLPOB (wide)
– 42 –
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
19
45
51
50
56
56
56
56
72
72
88
88
88
104
104
104
104
100
120
120
136
136
152
152
152
168
168
190
188
200
214
216
214
These timings can be switched by the serial interface data.
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
250
• ICX434
Draft mode
150
Applicable CCD image sensor
MODE
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-B2.
∗ CLPOB also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. CLPOB (wide) is output in the shaded portions shown in Chart-B2.
(1848)
0
Chart-B4 Horizontal Direction Timing Chart
CXD3422GA
ID/EXP
CLPDM
CLPOB
PBLK
50
56
56
56
70
70
#1
84
84
88
98
98
100
112
112
126
126
#2
140
140
152
154
154
168
168
182
182
188
#3
196
196
200
210
210
224
224
238
238
#4
252
252
250
• ICX434
Frame mode
150
Applicable CCD image sensor
MODE
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-B1.
∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 22H 1848ck (#758).
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
WEN/FLD
– 43 –
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
(1848)
0
Chart-B5 Horizontal Direction Timing Chart
(High-speed sweep: C)
266
266
CXD3422GA
B Field
A Field
– 44 –
Logical alignment
56 72 88 104 120 136 152 168 184 200 216
[B]
[A]
1175
1131
1133
1091
1071
(1848)
0
56 72 88 104 120 136 152 168
• ICX434
Applicable CCD image sensor
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
V4
V3B
V3A
V2
V1B
V1A
V4
V3B
V3A
V2
V1B
V1A
HD
(1848)
0
Frame mode
MODE
1027
1029
Chart-B6 Horizontal Direction Timing Chart
CXD3422GA
– 45 –
56 72 88 104 120 136 152 168
[D]
1175
1131
1133
1111
1091
(1848)
0
∗ HD of this chart indicates the actual CXD3422GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximates (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
V4
V3B
V3A
V2
V1B
V1A
HD
(1848)
0
1027
1029
Draft mode
MODE
1071
Chart-B7 Horizontal Direction Timing Chart
56 72 88 104 120 136 152 168
• ICX434
Applicable CCD image sensor
CXD3422GA
CCD OUT
1
050h
SMD
SHR
050h
1
000
A
B
050h
1
000
B
C
050h
1
000
C
D
050h
1
000
D
Close
050h
0
010
E
050h
0
010
E
050h
1
000
Open
F
050h
1
000
F
• ICX434
Draft → Frame → Draft
E
Applicable CCD image sensor
MODE
∗ This chart is a driving timing chart example of electronic shutter normal operation.
∗ Data exposed at D includes a blooming component. For details, see the CCD image sensor data sheet.
∗ The CXD3422GA does not generate the pulse to control mechanical shutter operation.
∗ The drive mode and the electronic shutter data are not switched at the same timing.
∗ This chart shows the pin configuration for the ICX434. (See page 3.)
000
A
MODE
Mechanical
shutter
– 46 –
SUB
V4
V3B
V3A
V2
V1B
V1A
VD
Chart-B8 Vertical Direction Sequence Chart
CXD3422GA
– 47 –
XSHD
XSHP
RG
H2
H1
MCKO
ADCLK
CKO
CKI
HD'
HD
Chart-Z
MODE
56/52
188/644/888
• ICX432/ICX434
Applicable CCD image sensor
∗ HD' indicates the HD which is the actual CXD3422GA load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface data.
1
High-Speed Phase Timing Chart
CXD3422GA
CXD3422GA
CCD Signal Processor Block Serial Interface Control
The CXD3422GA's CCD signal processor block basically loads the CCD signal processor block serial interface
data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the
operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.
SSI2
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
SCK2
SEN2
There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, and input pulse polarity setting data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value has been reflected to operation 6 ADCKLI clocks after that, then
transmit the next category.
The details of each data are described below.
Standby Control Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D14
FIXED
D15
STB
Data = 0
Data = 1
Set to "0".
D01 to D03 CTG
—
Set to "all 0".
Standby control
Normal operation mode
Standby mode
Data = 0
Data = 1
PGA Gain Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04,
FIXED
D05
D06
to
D15
GAIN
Set to "0".
D01 to D03 CTG
—
Set to "all 0".
PGA gain setting data
See D06 to D15 GAIN.
– 48 –
CXD3422GA
OB Clamp Level Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D11
FIXED
D12
to
D15
OBLVL
Data = 0
Data = 1
Set to "0".
D01 to D03 CTG
—
Set to "all 0".
OB clamp level setting data
See D12 to D15 OBLVL.
Input Pulse Polarity Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D12
FIXED
D13
to
D15
POL
Data = 0
Data = 1
Set to "0".
D01 to D03 CTG
—
Set to "all 0".
Input pulse polarity setting data
– 49 –
Set to "all 0".
CXD3422GA
Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3422GA by the CCD signal processor block serial interface, the CXD3422GA
loads D04 and subsequent data to each data register as shown in the table below according to the
combination of D01 to D03 .
Description of operation
D01
D02
D03
0
0
0
Loading to standby control data register
0
0
1
Loading to PGA gain setting data register
0
1
0
Loading to OB clamp level setting data register
0
1
1
Loading to input pulse polarity setting data register
1
x
x
Access prohibited
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
D15
Description of operation
0
Normal operating mode
1
Standby mode
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3422GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
MSB
LSB
D06 D07 D08 D09
0
↓
1
1
1
1
D10 D11 D12 D13
↓
C
0
0
0
0
↓
3
D14
D15
1
1
→ GAIN is expressed as 1C3h .
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are –6dB, 0dB, +20dB, +34dB and +42dB.
– 50 –
CXD3422GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp level]
The CXD3422GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal
processor block control data D12 to D15 OBLVL.
The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.
MSB
LSB
D12 D13 D14
D15
0
1
↓
6
1
0
→ OBLVL is expressed as 6h .
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values
are 0LSB, 4LSB, 32LSB and 60LSB.
– 51 –
V6
V1
SUB
V4
V3B
V3A
V2
V5B
V5A
RG
H2
H1
C4
C3
C2
N7
N5
M7
L4
N6
L6
M4
M5
N4
K8
J9
J8
C8
C7
D8
D7
C9
J1
XSHPI
OSCO
XSHDI
K1
PBLKI
L1
CLPOB
CLPDM
PBLK
XSHP
H7 L3 A5 C4 B5
TG/CDS/PGA/ADC
CXD3422GA
ADCLKI
B7
A7
C6
L2 N1 M1 A4 B4 A3
G1
C9 0.1µF
SNCSL
SSGSL
N8
L8
Controller
RST
WEN/FLD
ID/EXP
HD
VD
MCKO
CKO
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
NC
NC
M8
M9
N9
N2
M2
K2
J2
E1
D1
D2
D3
C1
C2
C3
B1
B2
B3
A1
A2
This is the block diagram indicating the connection relations between this IC and each circuit block, and not the actual circuit
diagram. Regarding the concrete connection circuit example with the CCD image sensor, see the data sheet of the CCD image
sensor.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
240pF
390pF
390pF
C1
CKI
1µF
TEST1
ADCLK
G9 G8 G7 H3 H2 H1
TEST2
CLPDMI
OSCI
XSHD
TEST3
CLPOBI
F9 F8 F7 G3 G2
SSI1
CCDIN
SEN1
1µF
TEST4
C7 0.1µF
SCK1
CCDOUT
TEST5
C8 0.1µF
SSI2
CCD
ICX432
ICX434/ICX284
SEN2
– 52 –
SCK2
Application Circuit Block Diagram
Signal
Processor
Block
CXD3422GA
CXD3422GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins and CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4, and AVDD5 pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin
from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block VDD4, pin supply voltage 3 VDDc and the CCD
signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2
VDDf and 3 VDDg should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4,
VSS5 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4, AVSS5
and AVSS6 should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
– 53 –
CXD3422GA
Package Outline
Unit: mm
0.2
96PIN LFLGA
S A
8.0
PIN 1 INDEX
1.3 MAX
0.2
0.2
S
S B
12.0
0.10MAX
0.10 S
X
x4
S
0.15
0.5
A
N
M
L
K
J
H
G
F
E
D
φ0.08 M S A B
B
C
B
0.9
96 -φ0.45 ± 0.05
0.8
0.8
0.9
(0.3)
DETAIL X
(0.3)
3 – φ0.50
0.5
(0.3)
1 2 3 4 5 6 7 8 9
0.8
0.5
1.2
(0.3)
0.5
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
ORGANIC SUBSTRATE
SONY CODE
LFLGA-96P-02
TERMINAL TREATMENT NICKEL & GOLD PLATING
EIAJ CODE
P-LFLGA96-12X8-0.8
TERMINAL MATERIAL
JEDEC CODE
PACKAGE MASS
– 54 –
COPPER
0.3g
Sony Corporation