SONY CXD3615R

CXD3615R
Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD3615R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX432/434 CCD image sensor.
48 pin LQFP (Plastic)
Features
• Base oscillation frequency 48.6/36.0MHz
• Electronic shutter function
• Supports draft, AF mode
• H/V driver for CCD
Absolute Maximum Ratings
• Supply voltage VDD
VSS – 0.3 to +7.0
V
VL
–10.0 to VSS
V
VH
VL – 0.3 to +26.0
V
• Input voltage
VI
VSS – 0.3 to VDD + 0.3 V
VSS – 0.3 to VDD + 0.3 V
• Output voltage VO1
VO2
VL – 0.3 to VSS + 0.3 V
VO3
VL – 0.3 to VH + 0.3 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
• ICX432 (Type 1/2.7, 3240K pixels)
• ICX434 (Type 1/3.2, 2020K pixels)
VSS5
HR
VR
SEN
SCK
SSI
MCKO
VDD5
OSCI
OSCO
CKI
CKO
Pin Configuration
36
35
34
33
32
31
30
29
28
27
26
25
VM
37
24 VSS4
V4
38
23 ADCLK
V2
39
22 OBCLP
V5A
40
21 TEST2
VH
41
20 CLPDM
V5B
42
19 PBLK
V1
43
18 TEST1
V3A
44
17 XSHD
VL
45
16 XSHP
V3B
46
15 VDD4
V6
47
14 VDD3
SUB
48
Recommended Operating Conditions
• Supply voltage VDDa, VDDb, VDDc
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
• Operating temperature
Topr
–20 to +75
V
V
V
V
°C
∗ Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
2
3
4
5
6
7
8
9
10
11
12
VSS1
RST
SNCSL
ID/EXP
WEN/FLD
SSGSL
VDD1
VDD2
RG
VSS2
VSS3
H1
13 H2
1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02216-PS
CXD3615R
VDD2
RG
VSS2
XSHP
10
16 17 23
28
27
Sel
OSCO
CKG
26
19 PBLK
1/2
1/2
20 CLPDM
Sel
CKI
ADCLK
VDD3
9
H2
8
H1
11 12 13 14
VSS3
OSCI
XSHD
Block Diagram
H/VTM
SHT
MCKO 30
CKO 25
SNCSL
3
Selector
Latch
4
ID/EXP
5
WEN/FLD
39 V2
SSI 31
SCK 32
22 OBCLP
38 V4
47 V6
Register
43 V1
SEN 33
SSGSL
6
RST
2
Selector
44 V3A
V Driver
46 V3B
40 V5A
42 V5B
48 SUB
SSG
37 VM
35 34
HR
–2–
VR
15 29
VDD5
7
VDD4
24 36
VSS5
1
VDD1
45 VL
VSS1
41 VH
TEST2 21
VSS4
TEST1 18
CXD3615R
Pin Description
Pin
No.
Symbol
I/O
Description
1
VSS1
—
2
RST
I
3
SNCSL
I
4
ID/EXP
O
Vertical direction line identification pulse output/exposure time identification pulse
output.
Switching possible using the serial interface data. (Default: ID)
5
WEN/FLD
O
Memory write timing pulse output/field discrimination pulse output.
Switching possible using the serial interface data. (Default: WEN)
6
SSGSL
I
7
VDD1
—
3.3V power supply. (Power supply for common logic block)
8
VDD2
—
3.3V power supply. (Power supply for RG)
9
RG
O
CCD reset gate pulse output.
10
VSS2
—
GND
11
VSS3
—
GND
12
H1
O
CCD horizontal register clock output.
13
H2
O
CCD horizontal register clock output.
14
VDD3
—
3.3V power supply. (Power supply for H1/H2)
15
VDD4
—
3.3V power supply. (Power supply for CDS)
16
XSHP
O
CCD precharge level sample-and-hold pulse output.
17
XSHD
O
CCD data level sample-and-hold pulse output.
18
TEST1
I
IC test pin 1; normally fixed to GND.
19
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning
20
CLPDM
O
CCD dummy signal clamp pulse output.
21
TEST2
—
IC test pin 2; normally fixed to GND.
22
OBCLP
O
CCD optical black signal clamp pulse output.
The horizontal/vertical OB pattern can be changed using the serial interface data.
23
ADCLK
O
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
24
VSS4
—
GND
25
CKO
O
Inverter output.
26
CKI
I
Inverter input.
27
OSCO
O
Inverter output for oscillation. When not used, leave open or connect a capacitor.
28
OSCI
I
Inverter input for oscillation. When not used, fix to low.
29
VDD5
—
3.3V power supply. (Power supply for common logic block)
30
MCKO
O
System clock output for signal processing IC.
GND
Internal system reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input
Control input used to switch sync system.
Internal SSG enable.
High: CKI sync, Low: MCKO sync
With pull-down resistor
High: Internal SSG valid, Low: External sync valid
With pull-down resistor
–3–
With pull-down resistor
With pull-down resistor
CXD3615R
Pin
No.
Symbol
I/O
Description
Serial interface data input for internal mode settings.
31
SSI
I
32
SCK
I
33
SEN
I
34
VR
I/O
Vertical sync signal input/output.
35
HR
I/O
Horizontal sync signal input/output.
36
VSS5
—
GND
37
VM
—
GND (GND for vertical driver)
38
V4
O
CCD vertical register clock output/V2 for ICX434.
39
V2
O
CCD vertical register clock output/open for ICX434.
40
V5A
O
CCD vertical register clock output/V3A for ICX434.
41
VH
—
15.0V power supply. (Power supply for vertical driver)
42
V5B
O
CCD vertical register clock output/V3B for ICX434.
43
V1
O
CCD vertical register clock output/open for ICX434.
44
V3A
O
CCD vertical register clock output//V1A for ICX434.
45
VL
—
–7.5V power supply. (Power supply for vertical driver)
46
V3B
O
CCD vertical register clock output/V1B for ICX434.
47
V6
O
CCD vertical register clock output//V4 for ICX434.
48
SUB
O
CCD electronic shutter pulse output.
Schmitt trigger input
Serial interface clock input for internal mode settings.
Schmitt trigger input
Serial interface strobe input for internal mode settings.
Schmitt trigger input
–4–
CXD3615R
Electrical Characteristics
DC Characteristics
Item
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1 VDD3
VDDa
3.0
3.3
3.6
V
Supply voltage 2 VDD2
VDDb
3.0
3.3
3.6
V
VDDc
3.0
3.3
3.6
V
Supply voltage 3
VDD1, VDD4,
VDD5
RST, SSI,
Input voltage 1∗1
SCK, SEN
Vt+
0.8VDDc
Vt–
0.2VDDc
TEST1, TEST2, VIH1
Input voltage 2∗2
SNCSL, SSGSL VIL1
0.7VDDc
VIH2
0.8VDDc
Input/output
voltage
VR, HR
Output voltage 1 H1, H2
Output voltage 2 RG
Feed current where IOH = –1.2mA VDDc – 0.8
VOL1
Pull-in current where IOL = 2.4mA
VOH2
Feed current where IOH = –14.0mA VDDa – 0.8
VOL2
Pull-in current where IOL = 9.6mA
VOH3
Feed current where IOH = –3.3mA VDDb – 0.8
VOL3
Pull-in current where IOL = 2.4mA
Output voltage 4 CKO
Output voltage 5 MCKO
Output voltage 6
ID/EXP,
WEN/FLD
V1, V3A, V3B,
Output current 1 V5A, V5B, V2,
V4, V6
Output current 2 SUB
Feed current where IOH = –3.3mA VDDc – 0.8
Pull-in current where IOL = 4.8mA
VOH6
Feed current where IOH = –3.3mA VDDc – 0.8
VOL6
Pull-in current where IOL = 2.4mA
VOH7
Feed current where IOH = –2.4mA VDDc – 0.8
VOL7
Pull-in current where IOL = 4.8mA
IOL
V1, V2, V3A/B, V4, V5A/B, V6
= –8.25V
IOM1
V1, V2, V3A/B, V4, V5A/B, V6
= –0.25V
IOM2
V1, V3A/B, V5A/B = 0.25V
IOH
V1, V3A/B, V5A/B = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
∗1 These input pins are Schmitt trigger inputs.
∗2 This input pin is with pull-down register in the IC.
–5–
V
V
0.4
VOL5
V
V
0.4
Feed current where IOH = –6.9mA VDDc – 0.8
V
V
0.4
VOH5
V
V
0.4
Pull-in current where IOL = 2.4mA
V
V
0.2VDDc
VOH1
V
V
0.3VDDc
VIL2
XSHP, XSHD, VOH4
PBLK, OBCLP,
Output voltage 3
CLPDM,
VOL4
ADCLK
V
V
V
0.4
V
V
0.4
V
V
0.4
10.0
V
mA
–5.0
5.0
mA
mA
–7.2
5.4
mA
mA
–4.0
mA
CXD3615R
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input voltage
OSCI
Output voltage
OSCO
Feedback
resistor
Oscillation
frequency
(Within the recommended operating conditions)
Symbol
Min.
Conditions
Typ.
LVth
Max.
VDDc/2
V
0.7VDDc
VIH
V
VIL
0.3VDDc
VOH
Feed current where IOH = –3.6mA VDDc – 0.8
VOL
Pull-in current where IOL = 2.4mA
OSCI,
OSCO
RFB
VIN = VDDc or VSS
OSCI,
OSCO
f
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Logical Vth
Symbol
Conditions
Min.
LVth
Input voltage
CKI
Input amplitude
Typ.
VDDc/2
VIH
V
0.3VDDc
fmax 50MHz sine wave
Unit
V
0.7VDDc
VIL
VIN
Max.
0.3
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
(VH = 15.0V, VM = GND, VL = –7.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Notes)
1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
–6–
CXD3615R
Switching Waveforms
TTMH
TTHM
VH
V1 (V3A, V3B, V5A, V5B)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V2 (V4, V6)
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–7–
CXD3615R
Measurement Circuit
Serial interface data
CKI
VR
HR
C6
+3.3V
–7.5V
C6
+15.0V
36 35 34 33 32 31 30 29 28 27 26 25
R1
C2
C2
R1
R1
C1 C2
C1
C2
C2
R1
C2 C2
C2
C1
R1
C1
C2
R2
C2
R1
24
38
23
39
22
40
21
41
20
42
19
CXD3615R
43
C2
C2
C2
C1
C2
C1
C2
37
C3
17
45
16
46
15
47
14
48
13
2
3
4
5
6
7
8
9
10 11 12
C4
C1: 3300pF
R1: 30Ω
C2: 560pF
R2: 10Ω
C3: 820pF
C4: 8pF
–8–
C6
C6
C6
18
44
1
C6
C5: 140pF
C5
C6: 10pF
C6
C6
C5
CXD3615R
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDc
SSI
0.2VDDc
0.8VDDc
0.2VDDc
ts1
SCK
SEN
th1
0.2VDDc
ts3
0.8VDDc
SEN
ts2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI setup time, activated by the rising edge of SCK
20
ns
SSI hold time, activated by the rising edge of SCK
20
ns
SCK setup time, activated by the rising edge of SEN
20
ns
SEN setup time, activated by the rising edge of SCK
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VR
HR
V1
Enlarged view
HR
0.2VDDc
V1
ts1
SEN
th1
0.8VDDc
0.2VDDc
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HR in the horizontal period
during which V1, V3A/B and V5A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of HR
0
ns
SEN hold time, activated by the falling edge of HR
123
µs
∗ Restriction for the ICX432 operating frequency of 24.3MHz in draft mode
–9–
CXD3615R
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VR
HR
Enlarged view
VR
0.2VDDc
HR
ts1
SEN
th1
0.8VDDc
0.2VDDc
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VR.
(Within the recommended operating conditions)
Definition
Symbol
ts1
th1
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of VR
0
ns
SEN hold time, activated by the falling edge of VR
200
ns
∗ Restriction for the ICX432 operating frequency of 24.3MHz in draft mode
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3615R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3615R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDc
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN
– 10 –
5
Typ.
Max.
Unit
100
ns
CXD3615R
RST loading characteristics
RST
0.2VDDc
0.2VDDc
tw1
(Within the recommended operating conditions)
Definition
Symbol
tw1
Min.
RST pulse width
Typ.
Max.
35
Unit
ns
VR and HR phase characteristics
VR
0.2VDDc
0.2VDDc
ts1
th1
HR
0.2VDDc
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
VR setup time, activated by the falling edge of HR
0
ns
VR hold time, activated by the falling edge of HR
0
ns
HR loading characteristics
HR
0.2VDDc
0.2VDDc
ts1
th1
0.8VDDc
MCKO
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
HR setup time, activated by the rising edge of MCKO
13
ns
HR hold time, activated by the rising edge of MCKO
0
ns
Output variation characteristics
MCKO
0.8VDDc
WEN/FLD,
ID/EXP
tpd1
WEN/FLD and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
20
– 11 –
Typ.
Max.
Unit
60
ns
CXD3615R
Description of Operation
Pulses output from the CXD3615R are controlled mainly by the RST pin and by the serial interface data. The
Pin Status Table is shown below, and the details of serial interface control are described on the following
pages.
Pin Status Table
Pin
No.
Symbol
CAM
SLP
SST
STB
RST
—
Pin
No.
Symbol
CAM
SLP
SST
STB
RST
25
CKO
ACT
ACT
L
L
ACT
1
VSS1
2
RST
ACT
ACT
ACT
ACT
L
26
CKI
ACT
ACT
ACT
ACT
ACT
3
SNCSL
ACT
ACT
ACT
ACT
ACT
27
OSCO
ACT
ACT
ACT
ACT
ACT
4
ID/EXP
ACT
L
L
L
L
28
OSCI
ACT
ACT
ACT
ACT
ACT
5
WEN/FLD ACT
L
L
L
L
29
VDD5
6
SSGSL
ACT
ACT
ACT
ACT
30
MCKO
ACT
ACT
L
L
ACT
7
VDD1
—
31
SSI
ACT
ACT
ACT
ACT
DIS
8
VDD2
—
32
SCK
ACT
ACT
ACT
ACT
DIS
9
RG
33
ACT
ACT
ACT
ACT
DIS
10
VSS2
—
34
SEN
VR∗1
ACT
L
L
L
H
11
VSS3
—
35
HR∗1
ACT
L
L
L
H
12
H1
ACT
L
L
L
ACT
36
VSS5
—
13
H2
ACT
L
L
L
ACT
37
VM
—
14
VDD3
—
38
V4
ACT
VM
VM
VM
VM
15
VDD4
—
39
V2
ACT
VM
VM
VM
VM
16
XSHP
ACT
L
L
L
ACT
40
V5A
ACT
VH
VM
VH
VL
17
XSHD
ACT
L
L
L
ACT
41
VH
18
TEST1
42
V5B
ACT
VH
VM
VH
VL
19
PBLK
ACT
L
L
L
H
43
V1
ACT
VH
VM
VH
VM
20
CLPDM
ACT
L
L
L
H
44
V3A
ACT
VH
VM
VH
VM
21
TEST2
45
VL
22
OBCLP
ACT
L
L
L
H
46
V3B
ACT
VH
VM
VH
VM
23
ADCLK
ACT
L
L
L
ACT
47
V6
ACT
VM
VM
VM
VL
24
VSS4
48
SUB
ACT
VH
VL
VH
VL
ACT
ACT
L
L
L
ACT
—
—
—
—
—
—
∗1 It is for output. For input, all items are “ACT”.
Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output
level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 41), VM (Pin 37) and VL (Pin 45),
respectively, in the controlled status.
– 12 –
CXD3615R
Serial Interface Control
The CXD3615R basically loads and reflects the serial interface data sent in the following format in the readout
portion at the falling edge of HR. Here, readout portion specifies the horizontal period during which V1, V3A/B
and V5A/B, etc. take the ternary value.
Note that some items reflect the serial interface data at the falling edge of VR or the rising edge of SEN.
SSI
00
01
02
03
04
05
06
41
42
43
44
45
46
47
SCK
SEN
These are two categories of serial interface data: the CXD3615R drive control data (hereafter “control data”)
and electronic shutter data (hereafter “shutter data”).
The details of each data are described below.
– 13 –
CXD3615R
Control Data
Data
D00
to
D07
Symbol
CHIP
D08 CTG
D09
to
D11
NTPL
D17
CCD
D18,
D19
SMD
D21
HTSG
D22
to
D30
—
RST
All
0
Category switching
See the category section.
0
—
—
Drive mode switching
—
See the drive mode section.
—
Internal SSG function switching∗1
CCD switching∗1
—
—
D20
Data = 1
10000001 → Enabled
Other values → Disabled
—
D16
Data = 0
Chip enable
—
D12,
MODE
D13
D14,
D15
Function
Electronic shutter mode switching∗2
HTSG control switching∗2
—
All
0
0
—
—
0
NTSC
PAL
0
ICX432
ICX434
0
—
—
0
OFF
ON
0
OFF
ON
0
—
—
All
0
D31
FLD
WEN/FLD output switching
WEN
FLD
0
D32
FGOB
Wide OBCLP generation switching
OFF
ON
0
D33
EXP
ID/EXP output switching
ID
EXP
0
D34,
PTOB
D35
OBCLP waveform pattern switching
D36,
LDAD
D37
ADCLK logic phase adjustment
D38,
STB
D39
Standby control
D40
to
D47
—
—
∗1 See the drive mode section.
∗2 See the electronic shutter section.
– 14 –
See the OBCLP waveform pattern section.
All
0
See the ADCLK logic phase section.
All
0
See the standby section.
All
0
—
All
0
—
CXD3615R
Shutter Data
Data
D00
to
D07
CHIP
D08 CTG
D09
Function
Symbol
—
Data = 0
Data = 1
RST
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
Category switching
See the category section.
0
—
—
—
0
D10
to
SVR
D19
Electronic shutter vertical period
specification
See the electronic shutter section.
All
0
D20
to
D31
SHR
Electronic shutter horizontal period
specification
See the electronic shutter section.
All
0
D32
to
D41
SPL
High-speed shutter position
specification
See the electronic shutter section.
All
0
D42
to
D47
—
—
—
– 15 –
—
All
0
CXD3615R
Detailed Description of Each Data
Shared data: D08 CTG [Category]
Of the data provided to the CXD3615R by the serial interface, the CXD3615R loads D09 and subsequent
data to each data register as shown in the table below according to D08 .
D08
Description of operation
0
Loading to control data register
1
Loading to shutter data register
Note that the CXD3615R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D12 and D13 MODE [Drive mode]
The CXD3615R realizes various drive modes using control data D12 and D13 MODE, D16 NTPL and D17
CCD. The drive mode-related bits are loaded to the CXD3615R and reflected at the falling edge of VR. The
details are described below.
First, the various basic drive modes are shown below. These modes are switched using control data D12 and
D13 MODE.
D13
D12
Description of operation
0
0
Draft mode (default)
0
1
1
0
Frame mode
AF mode∗1
1
1
Test mode
∗1 These are both test mode for the ICX434.
Draft mode is the pulse elimination drive mode in the ICX432/434.
AF mode is the pulse eliminator drive mode based on draft mode, and is a high frame rate drive mode that can
be used for purposes such as auto focus (AF).
Frame mode is the ICX432/434 drive mode in which the data for all lines are read.
In addition to these modes, the CXD3615R has functions for switching the applicable CCD with D17 CCD,
and for switching VR/HR to NTSC equivalent or PAL equivalent with D16 NTPL.
Control data: D31 FLD [WEN/FLD output switching]
The WEN/FLD pin (Pin 5) output can be switched to the WEN pulse or the FLD pulse. The default is "WEN".
See the Timing Charts for the WEN pulse. The FLD pulse rises in the readout block in the A Field, and falls in
the horizontal period immediately thereafter. That is to say, FLD is a 1H high-active pulse. The transition points
are the same as for ID/WEN.
HR
VCK
FLD
– 16 –
CXD3615R
Control data: D32 FGOB [Wide OBCLP generation]
This controls wide OBCLP generation during the vertical OPB period. When this function is on, the D34 and
D35 PTOB setting is invalid for the output block. See the Timing Charts for the actual operation. The default is
"OFF".
D32
Description of operation
0
Wide OBCLP generation OFF
1
Wide OBCLP generation ON
Control data D34 and D35 PTOB [OBCLP waveform pattern]
This designates the OBCLP waveform pattern. The default is "Normal". See the Timing Charts for details of the
decoding values.
D35
D34
0
0
0
Waveform pattern
ICX432
ICX434
(Normal)
20 to 44
19 to 45
1
(Shifted rearward)
14 to 38
13 to 39
1
0
(Shifted forward)
26 to 50
25 to 51
1
1
(Wide)
14 to 50
13 to 51
Control data: D36 and D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is "90°" relative to MCKO.
D37
D36
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
Control data: D38 and D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3615R and control
is applied immediately at the rising edge of SEN.
D39
D38
Symbol
Operating mode
0
0
CAM
Normal operating mode
0
1
SLP
Sleep mode
1
0
SST
Siesta mode
1
1
STB
Standby mode
See the Pin Status Table for the pin status in each mode.
– 17 –
CXD3615R
Control data/shutter data: [Electronic shutter]
The CXD3615R realizes various electronic shutter functions by using control data D20 SMD and D21
HTSG and shutter data D10 to D19 SVR, D20 to D31 SHR and D32 to D41 SPL. These functions are
described in detail below.
First, the various modes are shown below. These modes are switched using control data D20 SMD.
D20
Description of operation
0
Electronic shutter stopped mode
1
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHR as an example.
However, MSB (D31) is a reserved bit for the future specification, and is handled as a dummy bit on this IC.
MSB
LSB
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20
X
0
↓
1
0
1
1
1
↓
C
0
0
0
0
↓
3
1
1
→ SHR is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
Data
Description
SVR
Shutter: D10 to D19
Number of vertical periods specification (000h ≤ SVR ≤ 3FFh)
SHR
Shutter: D20 to D31
Number of horizontal periods specification (000h ≤ SHR ≤ 7FFh)
SPL
Shutter: D32 to D41
Vertical period specification for high-speed shutter operation
(000h ≤ SPL ≤ 3FFh)
Note) The bit data definition area is assured in terms of the CXD3615R functions, and does not assure the
CCD characteristics.
The period during which SVR and SHR are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VR and HR periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVR × (1V period) + {(number of HR per 1V) – (SHR + 1)} × (1H period)
+ (distance from SUB to SG during the readout period)
Concretely, when specifying high-speed shutter, SVR is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVR is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHR can be considered as (number of SUB pulses – 1). The readout period is
normally the horizontal period during which V1, V3A/B and V5A/B (for the ICX432) are ternary values, and SG
indicates these ternary level readout pulses.
– 18 –
CXD3615R
VR
SHR
SVR
V3A
SUB
WEN
EXP
SMD
1
1
SVR
002h
000h
SHR
10Fh
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHR at the SPL vertical period out of (SVR + 1) vertical periods.
SPL
000
001
VR
002
SVR
SHR
V3A
SUB
WEN
EXP
SMD
1
1
SPL
001h
000h
SVR
002h
000h
SHR
10Fh
0A3h
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVR.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
– 19 –
CXD3615R
[HTSG control mode]
This mode controls the V1, V3A/B and V5A/B (for the ICX432) ternary level outputs (readout pulse block) using
D21 HTSG.
D21
Description of operation
0
Readout pulse (SG) normal operation
1
HTSG control mode
VR
V3A
SUB
WEN
EXP
HTSG
0
1
0
SMD
1
0
1
Exposure time
[EXP pulse]
The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when
it is high. In principle, the transition points are the last SUB pulse falling edge and the readout pulse falling edge,
that is to say from the time the charge is completely discharged until transfer ends. However, when the readout
pulse timing differs within the same readout block such as in draft mode, the average value is used. Then, when
there is no SUB pulse in the next field, the readout pulse falling edge is defined as the start position. However, in
this case the transition points overlap and disappear, so a tentative start position is defined.
This is shown below.
[ICX432]
[ICX434]
SG ↓
Tentative start position
Frame mode
1460
1480
Draft/AF mode
1682
1784
A: 1071
1091
B: 1175
1195
1123
1175
Frame mode
Draft mode
See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation.
– 20 –
ID/EXP
CLPDM
OBCLP
PBLK
CCD
OUT
WEN/FLD
– 21 –
V6
V5B
V5A
V4
V3B
V3A
V2
V1
SUB
HR
VR
D
588 1
High-speed sweep block
A
43
1
1549
564
588 1
High-speed sweep block
B
43
B Field
564
588 1
High-speed sweep block
C
43
C Field
• ICX432
Frame mode
1548
1545
1236
9
6
3
8
5
1547
8
5
2
7
4
1546
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to (high, low, high) in the horizontal periods of each readout block (A, B, C).
∗ WEN/FLD of this chart shows WEN.
∗ The shaded portion of OBCLP shows the range over which the wide OBCLP can be set by the serial interface data.
∗ VR of this chart is NTSC equivalent pattern 587H (1H: 2760ck) + 1500ck units. For PAL equivalent pattern, it is 704H + 960ck units.
565
A Field
1550
Applicable CCD image sensor
2
MODE
3
Vertical Direction Timing Chart
6
1
Chart-A1
CXD3615R
4
WEN/FLD
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V6
V5B
V5A
V4
V3B
263
1549
1544 1546
1537 1541
1532 1534
1525 1527
1549
1537 1541
1544 1546
1532 1534
270 1
E
3
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to low in the horizontal periods of each readout block (E).
∗ WEN/FLD of this chart shows WEN.
∗ The shaded portion of OBCLP shows the range over which the wide OBCLP can be set by the serial interface data.
∗ VR of this chart is NTSC equivalent pattern 269H (1H: 3004ck) + 2734ck units. For PAL equivalent pattern, it is 323H + 1708ck units.
5
1
V3A
10
8
V2
E
17
13
V1
3
22
20
SUB
270 1
29
25
263
30
28
HR
5
VR
6
4
6
4
• ICX432
10
1
Draft mode
17
8
Applicable CCD image sensor
22
13
MODE
29
20
Vertical Direction Timing Chart
30
25
– 22 –
28
Chart-A2
CXD3615R
WEN/FLD
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V6
V5B
V5A
V4
V3B
V3A
V2
V1
SUB
HR
VR
High-speed sweep block
135 1
E
3
F
Frame shift block
27
G
High-speed sweep block
135 1
E
3
F
Frame shift block
27
• ICX432
AF mode
123
Applicable CCD image sensor
MODE
6
1525 1527
488 490
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to high in the horizontal periods of each readout block (E).
∗ WEN/FLD of this chart shows WEN.
∗ The shaded portion of OBCLP shows the range over which the wide OBCLP can be set by the serial interface data.
∗ VR of this chart is NTSC equivalent pattern 134H (1H: 3004ck) + 2869ck units. For PAL equivalent pattern, it is 161H + 2356ck units.
In addition, for PAL equivalent pattern, the high-speed sweep block starts from 150H.
G
123
481 485
Vertical Direction Timing Chart
6
4
– 23 –
4
Chart-A3
CXD3615R
HR
– 24 –
5
20
50
44
52
52
52
100
140
140
135
140
182
200
224
266
308
300
350
392
400
434
476
518
500
Frame mode
MODE
560
602
600
674
670
646 670
644
672
676
680
700
800
900
• ICX432
1000
Applicable CCD image sensor
These timings can be switched by the serial interface data.
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-A1.
∗ OBCLP also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-A1.
WEN/FLD
ID/EXP
CLPDM
OBCLP (wide)
OBCLP
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
(2760)
0
Horizontal Direction Timing Chart
MCKO
Chart-A4
CXD3615R
– 25 –
WEN/FLD
ID/EXP
CLPDM
OBCLP (wide)
OBCLP
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HR
20
50
44
52
52
52
100
140
140
135
140
171
202
200
233
264
295
300
326
357
388
419
400
450
481
512
543
574
605
600
636
667
698
700
729
760
791
800
822
853
890 914
918
914
888
900
1000
• ICX432
Draft/AF mode
500
Applicable CCD image sensor
MODE
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-A2 and A3.
∗ OBCLP also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-A2 and A3.
These timings can be switched by the serial interface data.
5
(3004)
0
Horizontal Direction Timing Chart
916
920
924
Chart-A5
CXD3615R
HR
– 26 –
5
52
52
100
135
140
140
158
176
158
176
#1
230
284
#2
320
302
320
302
300
284
266
266
248
248
230
212
194
212
194
200
338
356
338
356
374
392
374
392
#3
428
410
428
410
400
446
446
#1039
1970
1952
2042
2024
#1040
2060
2042
2024
2006
1988
2006
1988
1970
1952
5
52
52
100
135
140
182
200
224
• ICX432
Frame mode
(2760)
0
Applicable CCD image sensor
MODE
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
WEN/FLD
ID/EXP
CLPDM
OBCLP
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
(2760)
0
Horizontal Direction Timing Chart
(High-speed sweep: D)
MCKO
Chart-A6
CXD3615R
– 27 –
WEN/FLD
ID/EXP
CLPDM
OBCLP
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HR
52
52
100
135
140
171
202
200
233
264
295
300
326
357
388
419
400
450
481
512
#1
543
574
605
600
636
667
698
700
729
760
791
800
822
853
884
888
900
915
946
977
1039
#2
1008
1000
• ICX432
AF mode
500
Applicable CCD image sensor
MODE
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ Frame shift of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 24H 1096ck (#78).
5
(3004)
0
Horizontal Direction Timing Chart
(Frame shift: F)
916
920
924
Chart-A7
CXD3615R
– 28 –
5
52
52
100
140
135
140
#1
392
#2
596
704
800
#3
896
992
1052
1040
1028
1004
1016
1000
980
968
956
944
932
920
908
888
900
884
872
860
848
836
824
812
800
788
776
764
752
740
728
716
700
692
680
668
656
644
632
620
608
600
584
572
560
548
536
524
512
500
488
476
464
452
440
500
• ICX432
AF mode
428
416
404
400
380
368
356
344
332
320
308
296
300
284
272
260
248
236
224
212
200
188
176
164
152
200
Applicable CCD image sensor
MODE
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ High-speed sweep of V1, V2, V3A/B, V4, V5A/B and V6 is performed up to 133H 2932ck (#114).
WEN/FLD
ID/EXP
CLPDM
OBCLP
PBLK
SUB
V6
V5A/B
V4
V3A/B
V2
V1
H2
H1
MCKO
HR
(3004)
0
Horizontal Direction Timing Chart
(High-speed sweep: G)
916
920
924
Chart-A8
CXD3615R
V2
V1
– 29 –
V2
V1
V6
V5A/B
V4
V3A/B
B Field
V6
V5A/B
V4
V3A/B
A Field
HR
[B]
[A]
(2760)
0
392
266
224
182
140
1546
1502
1460
1420
1380
1338
1296
1254
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
(2760)
0
308
• ICX432
350
Frame mode
434
Applicable CCD image sensor
476
MODE
518
Horizontal Direction Timing Chart
560
Chart-A9a
CXD3615R
602
V2
V1
V6
V5A/B
V4
V3A/B
C Field
HR
[C]
(2760)
0
392
266
224
182
140
1460
1420
1380
1338
1296
1254
1212
1170
1128
1086
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
(2760)
0
308
• ICX432
350
Frame mode
434
Applicable CCD image sensor
476
MODE
518
Horizontal Direction Timing Chart
560
Chart-A9b
CXD3615R
– 30 –
602
– 31 –
[E]
(3004)
0
481
450
357
326
295
264
233
202
171
140
1908
1877
1846
1815
1784
1744
1704
1673
1642
1611
1580
1540
1500
1469
1438
1407
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 2.2 to 26.5µs (when the drive frequency is 24.3MHz). This chart shows a period of 104ck (4.3µs).
V6
V5B
V5A
V4
V3A
V3A
V2
V1
HR
(3004)
0
388
• ICX432
419
Draft/AF mode
574
543
512
Applicable CCD image sensor
605
MODE
636
Horizontal Direction Timing Chart
667
Chart-A10
CXD3615R
729
698
SUB
00
00
1
050h
MODE
SMD
SHR
B
050h
1
00
B
C
Close
000h
0
10
C (1st)
000h
0
10
C (2nd)
000h
0
10
C (3rd)
050h
1
00
Open
050h
1
00
D
• ICX432
Draft → Frame → Draft
D
Applicable CCD image sensor
MODE
∗ This chart is a drive timing chart example of electronic shutter normal operation.
∗ Data exposed at B includes the blooming component. For details, see the CCD image sensor data sheet.
∗ The CXD3615R does not generate the pulse to control mechanical shutter operation.
∗ The switching timing of drive mode and electronic shutter data is not the same.
050h
1
A
A
Vertical Direction Sequence Chart
CCD OUT
Mechanical
shutter
– 32 –
V6
V5B
V5A
V4
V3B
V3A
V2
V1
VR
Chart-A11
CXD3615R
– 33 –
C
650 1
High-speed sweep block
A
25
31
C
650 1
High-speed sweep block
B
24
6
4
2
1235
1233
1231
1229
1227
1225
27
17
15
13
11
9
7
5
3
7
5
3
1
1236
1234
1232
1230
1228
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to (low, high) in the horizontal periods of each readout portion (A, B).
∗ WEN/FLD of this chart shows WEN.
∗ VR of this chart is NTSC equivalent pattern 650H (1H: 1848ck) units. For PAL equivalent pattern, it is 779H + 408ck units.
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
WEN/FLD
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HR
9
VR
1
B Field
31
10
A Field
19
• ICX434
21
Frame mode
23
Applicable CCD image sensor
25
MODE
2
Vertical Direction Timing Chart
10
8
6
4
8
Chart-B1
CXD3615R
12
– 34 –
WEN/FLD
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HR
325 1
16
325 1
D
12
16
7
4
1231
1226
1223
1218
1215
1210
1207
1202
63
58
42
39
34
31
26
23
18
15
10
7
2
9
4
1234
1231
1226
1223
1218
1215
1210
1207
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
In this drive mode, ID is reset to high in the horizontal period of the readout portion.
∗ WEN/FLD of this chart shows WEN.
∗ VR of this chart is NTSC equivalent pattern 325H (1H: 1848ck) units. For PAL equivalent pattern, it is 389H + 1128ck units.
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
D
12
9
VR
47
• ICX434
50
Draft mode
55
Applicable CCD image sensor
1234
MODE
2
Vertical Direction Timing Chart
31
26
23
18
15
10
Chart-B2
CXD3615R
34
OBCLP
WEN/FLD
ID/EXP
CLPDM
OBCLP (wide)
– 35 –
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HR
Chart-B3
19
45
51
50
56
56
56
72
88
88
104
104
104
100
120
136
152
152
168
190
188
200
214
216
214
These timings can be switched by the serial interface data.
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
250
• ICX434
Frame mode
150
Applicable CCD image sensor
MODE
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-B1.
∗ OBCLP also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-B1.
(1848)
0
Horizontal Direction Timing Chart
CXD3615R
OBCLP
WEN/FLD
ID/EXP
CLPDM
OBCLP (wide)
– 36 –
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HR
Chart-B4
19
45
51
50
56
56
56
56
72
72
88
88
88
104
104
104
104
100
120
120
136
136
152
152
152
168
168
190
188
200
214
216
214
These timings can be switched by the serial interface data.
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
250
• ICX434
Draft mode
150
Applicable CCD image sensor
MODE
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-B2.
∗ OBCLP also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. OBCLP (wide) is output in the shaded portions shown in Chart-B2.
(1848)
0
Horizontal Direction Timing Chart
CXD3615R
ID/EXP
CLPDM
OBCLP
PBLK
(1848)
0
50
56
56
56
Horizontal Direction Timing Chart
(High-speed sweep: C)
70
70
#1
84
84
88
98
98
100
112
112
126
126
#2
140
140
152
154
154
168
168
182
182
188
#3
196
196
200
210
210
224
224
238
238
#4
252
252
250
266
266
• ICX434
Frame mode
150
Applicable CCD image sensor
MODE
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-B1.
∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 22H 1848ck (#758).
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
WEN/FLD
– 37 –
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HR
Chart-B5
CXD3615R
B Field
A Field
– 38 –
Logical alignment
56 72 88 104 120 136 152 168 184 200 216
[B]
[A]
Frame mode
MODE
1175
1131
1133
1091
1071
(1848)
0
56 72 88 104 120 136 152 168
• ICX434
Applicable CCD image sensor
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
V4
V3B
V3A
V2
V1B
V1A
V4
V3B
V3A
V2
V1B
V1A
HR
(1848)
0
Horizontal Direction Timing Chart
1027
1029
Chart-B6
CXD3615R
– 39 –
56 72 88 104 120 136 152 168
[D]
1175
1131
1133
1111
1091
(1848)
0
56 72 88 104 120 136 152 168
• ICX434
Applicable CCD image sensor
∗ HR of this chart indicates the actual CXD3615R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HR.
∗ The HR fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 104ck (5.8µs).
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
V4
V3B
V3A
V2
V1B
V1A
HR
(1848)
0
Draft mode
MODE
1027
1029
Horizontal Direction Timing Chart
1071
Chart-B7
CXD3615R
CCD OUT
1
050h
SMD
SHR
050h
1
00
A
B
050h
1
00
B
C
050h
1
00
C
D
050h
1
00
D
Close
050h
0
10
E
050h
0
10
E
050h
1
00
Open
F
050h
1
00
F
• ICX434
Draft → Frame → Draft
E
Applicable CCD image sensor
MODE
∗ This chart is a driving timing chart example of electronic shutter normal operation.
∗ Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet.
∗ The CXD3615R does not generate the pulse to control mechanical shutter operation.
∗ The switching timing of drive mode and electronic shutter data is not the same.
∗ This chart shows the pin configuration for the ICX434. (See page 4.)
00
A
Vertical Direction Sequence Chart
MODE
Mechanical
shutter
– 40 –
SUB
V4
V3B
V3A
V2
V1B
V1A
VR
Chart-B8
CXD3615R
– 41 –
XSHD
XSHP
RG
H2
H1
MCKO
ADCLK
CKO
CKI
HR'
HR
Chart-Z
MODE
56/52
188/644/888
• ICX432/ICX434
Applicable CCD image sensor
∗ HR' indicates the HR which is the actual CXD3615R load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface data.
1
High-Speed Phase Timing Chart
CXD3615R
CXD3615R
Application Circuit Block Diagram
D0 to D9
CCD OUT
S/H
A/D
V5B
V1
V3A
V3B
V6
SUB
ADCLK
OBCLP
CLPDM
PBLK
39
40
TG
CXD3615R
42
V-Dr
43
35
4
5
44
MCKO
VR
HR
ID/EXP
Signal
Processor
Block
WEN/FLD
2
RST
46
3
SNCSL
47
6
SSGSL
48
∗ V1 and V2 only for ICX432
26
18 21
31 32 33
SEN
V5A
SSG
SSI
V2
34
38
SCK
V4
30
CKO
9
TEST2
RG
25
13
TEST1
H2
23
16 17 19 20 22
12
CKI
H1
XSHD
10
XSHP
CCD
ICX432
ICX434
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on
Of the three –7.5V, +15.0V, +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in
the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
– 42 –
CXD3615R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
48
B
(0.22)
0.5 ± 0.2
A
(8.0)
24
37
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
0.13 M
+ 0.2
1.5 – 0.1
0.1
S
0.5 ± 0.2
0.18 ± 0.03
0˚ to 10˚
0.127 ± 0.04
0.1 ± 0.1
DETAIL B: PALLADIUM
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
PALLADIUM PLATING
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
EIAJ CODE
P-LQFP48-7x7-0.5
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 43 –
Sony Corporation