CXD2498R Timing Generator for Frame Readout CCD Image Sensor Description The CXD2498R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX282 CCD image sensor. Features • Base oscillation frequency 45MHz • Electronic shutter function • Supports various drive modes such as draft and AF mode • Horizontal driver for CCD image sensor • Vertical driver for CCD image sensor 48 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.3 to +7.0 V VL –10.0 to VSS V VH VL – 0.3 to +26.0 V • Input voltage VI VSS – 0.3 to VDD + 0.3 V • Output voltage VO1 VSS – 0.3 to VDD + 0.3 V VO2 VL – 0.3 to VSS + 0.3 V VO3 VL – 0.3 to VH + 0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX282 (Type 2/3, 5070K pixels) Recommended Operating Conditions • Supply voltage VDDa, VDDb, VDDc 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75 V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00X63-PS CXD2498R H2B VSS2 VSS3 XSHP 14 18 19 H2A 9 H1B 11 16 10 12 13 15 H1A VDD2 8 VDD3 RG XSHD Block Diagram VCO 17 VDD4 20 PBLK CKI 21 CLPDM 26 22 OBCLP CKO 25 MCKO 30 SNCSL 3 Pulse Generator 23 ADCLK 1/2 24 VSS4 Latch Selector 5 WEN 42 V1B 43 V1C SCK 32 Register 38 V2 SEN 33 44 V3A 6 SSG 2 46 V3B Selector RST ID/EXP 40 V1A SSI 31 SSGSL 4 V Driver 47 V3C 39 V4 TEST1 27 48 SUB TEST2 28 41 VH 37 VM 1 36 –2– VDD5 VSS1 VSS5 35 34 VD 29 HD 7 VDD1 45 VL CXD2498R VSS5 HD VD SEN SCK SSI MCKO VDD5 TEST2 TEST1 CKI CKO Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 VH 41 20 PBLK V1B 42 19 XSHD V1C 43 18 XSHP V3A 44 17 VDD4 VL 45 16 VDD3 V3B 46 15 H2B V3C 47 14 VSS3 SUB 48 13 H2A 1 2 3 4 5 6 7 8 9 10 11 12 H1B 21 CLPDM VDD2 40 H1A V1A VSS2 22 OBCLP RG 39 VDD1 V4 SSGSL 23 ADCLK WEN 38 ID/EXP V2 SNCSL 24 VSS4 RST 37 VSS1 VM ∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible. –3– CXD2498R Pin Description Pin No. Symbol I/O Description 1 VSS1 — 2 RST I 3 SNCSL I 4 ID/EXP O Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID) 5 WEN O Memory write timing pulse output. 6 SSGSL I 7 VDD1 — 3.3V power supply. (Power supply for common logic block) 8 RG O CCD reset gate pulse output. 9 VSS2 — GND 10 H1A O CCD horizontal register clock output. 11 VDD2 — 3.3V power supply. (Power supply for H block) 12 H1B O CCD horizontal register clock output. 13 H2A O CCD horizontal register clock output. 14 VSS3 — GND 15 H2B O CCD horizontal register clock output. 16 VDD3 — 3.3V power supply. (Power supply for H block) 17 VDD4 — 3.3V power supply. (Power supply for CDS block) 18 XSHP O CCD precharge level sample-and-hold pulse output. 19 XSHD O CCD data level sample-and-hold pulse output. 20 PBLK O Pulse output for horizontal and vertical blanking period pulse cleaning. 21 CLPDM O CCD dummy signal clamp pulse output. 22 OBCLP O CCD optical black signal clamp pulse output. The horizontal OB pattern can be changed using the serial interface data. 23 ADCLK O Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. 24 VSS4 — GND 25 CKO O Inverter output. 26 CKI I Inverter input. 27 TEST1 I IC test pin 1; normally fixed to GND. With pull-down resistor 28 TEST2 I IC test pin 2; normally fixed to GND. With pull-down resistor 29 VDD5 — 3.3V power supply. (Power supply for common logic block) 30 MCKO O System clock output for signal processing IC. 31 SSI I GND Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input Control input used to switch sync system. Internal SSG enable. High: CKI sync, Low: MCKO sync With pull-down resistor High: Internal SSG valid, Low: External sync valid With pull-down resistor Serial interface data input for internal mode settings. Schmitt trigger input –4– CXD2498R Pin No. Symbol I/O Description Serial interface clock input for internal mode settings. 32 SCK I 33 SEN I 34 VD I/O Vertical sync signal input/output. 35 HD I/O Horizontal sync signal input/output. 36 VSS5 — GND 37 VM — GND (GND for vertical driver) 38 V2 O CCD vertical register clock output. 39 V4 O CCD vertical register clock output. 40 V1A O CCD vertical register clock output. 41 VH — 15.0V power supply. (Power supply for vertical driver) 42 V1B O CCD vertical register clock output. 43 V1C O CCD vertical register clock output. 44 V3A O CCD vertical register clock output. 45 VL — –7.5V power supply. (Power supply for vertical driver) 46 V3B O CCD vertical register clock output. 47 V3C O CCD vertical register clock output. 48 SUB O CCD electronic shutter pulse output. Schmitt trigger input Serial interface strobe input for internal mode settings. Schmitt trigger input –5– CXD2498R Electrical Characteristics DC Characteristics Item (Within the recommended operating conditions) Pins Symbol Conditions Min. Typ. Max. Unit Supply voltage 1 VDD2, VDD3 VDDa 3.0 3.3 3.6 V Supply voltage 2 VDD4 VDDb 3.0 3.3 3.6 V Supply voltage 3 VDD1, VDD5 VDDc 3.0 3.3 3.6 V Input voltage RST, SSI, SCK, SEN 1∗1 Vt+ 0.8VDDc Vt– 0.2VDDc Input voltage TEST1, TEST2, VIH1 SNCSL, SSGSL VIL1 2∗2 0.7VDDc VIH2 0.8VDDc Input/output voltage VD, HD VIL2 Feed current where IOH = –1.2mA VDDc – 0.8 VOL1 Pull-in current where IOL = 2.4mA VOH2 Feed current where IOH = –22.0mA VDDa – 0.8 VOL2 Pull-in current where IOL = 14.4mA VOH3 Feed current where IOH = –3.3mA VDDc – 0.8 VOL3 Pull-in current where IOL = 2.4 mA Output voltage 2 RG Output voltage 3 XSHP, XSHD, VOH4 PBLK, OBCLP, CLPDM, ADCLK VOL4 Feed current where IOH = –3.3mA VDDb – 0.8 Output voltage 4 CKO VOH5 Feed current where IOH = –6.9mA VDDc – 0.8 VOL5 Pull-in current where IOL = 4.8mA Output voltage 5 MCKO VOH6 Feed current where IOH = –3.3mA VDDc – 0.8 VOL6 Pull-in current where IOL = 2.4mA Output voltage 6 ID/EXP, WEN VOH7 Feed current where IOH = –2.4mA VDDc – 0.8 VOL7 Pull-in current where IOL = 4.8mA IOL V1A/B/C, V2, V3A/B/C, V4 = –8.25V IOM1 V1A/B/C, V2, V3A/B/C, V4 = –0.25V IOM2 V1A/B/C, V3A/B/C = 0.25V IOH V1A/B/C, V3A/B/C = 14.75V IOSL SUB = –8.25V IOSH SUB = 14.75V Output current 2 V1A, V1B, V1C, V3A, V3B, V3C, V2, V4 SUB ∗1 This input pin is a schmitt trigger input. ∗2 This input pin is with pull-down registor in the IC. –6– V V 0.4 V V 0.4 Pull-in current where IOL = 2.4mA V V 0.4 H1A, H1B, H2A, H2B V V 0.2VDDc VOH1 V V 0.2VDDc Output voltage 1 Output current 1 V V V 0.4 V V 0.4 V V 0.4 V V 0.4 10.0 V mA –5.0 5.0 mA mA –7.2 5.4 mA mA –4.0 mA CXD2498R Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Pins Logical Vth Input voltage Symbol Conditions Min. Unit V 0.7VDDc VIH V VIL VIN Input amplitude Max. VDDc/2 LVth CKI Typ. 0.3VDDc fmax = 50MHz sine wave V Vp-p 0.3 Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Rise time Fall time Output noise voltage (VH = 15.0V, VM = GND, VL = –7.5V) Symbol Conditions Min. Typ. Max. Unit TTLM VL to VM 200 350 500 ns TTMH VM to VH 200 350 500 ns TTLH VL to VH 30 60 90 ns TTML VM to VL 200 350 500 ns TTHM VH to VM 200 350 500 ns TTHL VH to VL 30 60 90 ns VCLH 1.0 V VCLL 1.0 V VCMH 1.0 V VCML 1.0 V Note) 1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –7– CXD2498R Switching Waveforms TTMH TTHM VH V1A (V1B, V1C, V3A, V3B, V3C) TTLM 90% 90% 10% 10% TTML VM 90% 90% 10% 10% TTML TTLM VL VM 90% 90% V2 (V4) 10% 10% TTLH TTHL 90% VL VH 90% SUB 10% 10% VL Waveform Noise VM VCMH VCML VCLH VCLL VL –8– CXD2498R Measurement Circuit Serial interface data CKI VD HD C6 +3.3V –7.5V C6 +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 R1 C2 C2 R1 R1 C1 C2 C1 C2 C2 R1 C1 C2 C2 C2 C1 C2 C2 C1 R1 C1 C2 C2 R2 R1 24 38 23 39 22 40 21 41 20 42 19 CXD2498R 43 C2 C2 C2 37 18 44 17 45 16 46 15 47 14 48 13 1 C3 2 3 4 5 6 7 8 9 10 11 12 C4 C1: 3300pF R1: 30Ω C2: 560pF R2: 10Ω C3: 820pF –9– C4: 8pF C5: 320pF C5 C5 C6: 10pF C6 C6 C6 C6 C6 C6 C5 C5 CXD2498R AC Characteristics AC characteristics between the serial interface clocks 0.8VDDc SSI 0.2VDDc 0.8VDDc SCK ts1 SEN th1 0.2VDDc ts3 0.8VDDc SEN ts2 (Within the recommended operating conditions) Symbol ts1 th1 ts2 ts3 Definition Min. Typ. Max. Unit SSI setup time, activated by the rising edge of SCK 20 ns SSI hold time, activated by the rising edge of SCK 20 ns SCK setup time, activated by the rising edge of SEN 20 ns SEN setup time, activated by the rising edge of SCK 20 ns Serial interface clock internal loading characteristics (1) Example: During frame mode VD HD V1A Enlarged view HD 0.2VDDc V1A ts1 th1 0.8VDDc SEN 0.2VDDc ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period during which V1A/B/C and V3A/B/C values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit SEN setup time, activated by the falling edge of HD 0 ns SEN hold time, activated by the falling edge of HD 134 µs ∗ Restriction in draft mode with an operating frequency of 22.5MHz. – 10 – CXD2498R Serial interface clock internal loading characteristics (2) Example: During frame mode VD HD Enlarged view VD 0.2VDDc HD ts1 SEN th1 0.8VDDc 0.2VDDc ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit SEN setup time, activated by the falling edge of VD 0 ns SEN hold time, activated by the falling edge of VD 200 ns ∗ Restriction with an operating frequency of 22.5MHz. Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2498R at the timing shown in “Serial interface clock internal loading characteristics (1)” above. However, one exception to this is when the data such as STB is loaded to the CXD2498R and controlled at the rising edge of SEN. See ”Description of Operation”. SEN 0.8VDDc Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. tpdPULSE Output signal delay, activated by the rising edge of SEN – 11 – 5 Typ. Max. Uniy 70 ns CXD2498R RST loading characteristics RST 0.8VDDc 0.2VDDc tw1 (Within the recommended operating conditions) Symbol tw1 Definition Min. RST pulse width Typ. Max. 22 Unit ns VD and HD phase characteristics VD 0.2VDDc 0.2VDDc ts1 th1 HD 0.2VDDc (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. VD setup time, activated by the falling edge of HD Typ. Max. 0 Unit ns VD hold time, activated by the falling edge of HD 44 ns HD loading characteristics HD 0.2VDDd 0.2VDDd ts1 th1 0.8VDDd MCKO MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit HD setup time, activated by the rising edge of MCKO 31 ns HD hold time, activated by the rising edge of MCKO 0 ns – 12 – CXD2498R Output variation characteristics 0.8VDDc MCKO WEN, ID/EXP tpd1 WEN and ID/EXP load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Min. Time until the above outputs change after the rise of MCKO – 13 – 23 Typ. Max. Unit 33 ns CXD2498R Description of Operation Pulses output from the CXD2498R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. Symbol CAM SLP STB RST — Pin No. Symbol CAM SLP STB RST 25 CKO ACT ACT L ACT ACT ACT ACT ACT 1 VSS1 2 RST ACT ACT ACT L 26 CKI 3 SNCSL ACT ACT ACT ACT 27 TEST1 — 4 ID/EXP ACT L L L 28 TEST2 — 5 WEN ACT L L L 29 VDD5 — 6 SSGSL ACT ACT ACT ACT 30 MCKO ACT ACT L ACT 7 VDD1 31 SSI ACT ACT ACT DIS 8 RG 32 SCK ACT ACT ACT DIS 9 VSS2 33 ACT ACT ACT DIS 10 H1A 34 SEN VD∗1 ACT L L H 11 VDD2 35 HD∗1 ACT L L H 12 H1B ACT L L ACT 36 VSS5 — 13 H2A ACT L L ACT 37 VM — 14 VSS3 38 V2 ACT VM VM VM 15 H2B 39 V4 ACT VM VM VL 16 VDD3 — 40 V1A ACT VH VH VM 17 VDD4 — 41 VH 18 XSHP ACT L L ACT 42 V1B ACT VH VH VM 19 XSHD ACT L L ACT 43 V1C ACT VH VH VM 20 PBLK ACT L L H 44 V3A ACT VH VH VL 21 CLPDM ACT L L H 45 VL 22 OBCLP ACT L L H 46 V3B ACT VH VH VL 23 ADCLK ACT L L ACT 47 V3C ACT VH VH VL 24 VSS4 48 SUB ACT VH VH VL — ACT L L ACT — ACT L L ACT — — ACT L L — ACT — — ∗1 It is for output. For input, all items are “ACT”. Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 41), VM (Pin 37) and VL (Pin 45), respectively, in the controlled status. – 14 – CXD2498R Serial Interface Control The CXD2498R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B/C and V3A/B/C, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN. SSI 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 SCK SEN These are two categories of serial interface data : the CXD2498R drive control data (hereafter “control data”) and electronic shutter data (hereafter “shutter data”). The details of each data are described below. – 15 – CXD2498R Control Data Data Symbol Function Data = 0 Data = 1 RST D00 to D07 CHIP Chip enable 10000001 → Enabled Other values → Disabled All 0 D08 to D09 CTG Category switching See D08 to D09 CTG. All 0 D10 to D11 MODE Drive mode switching See D10 to D11 MODE. All 0 D12 — D13 SMD D14 HTSG D15 D16 to D17 — Electronic shutter mode switching∗1 HTSG control switching∗1 — — Drive mode pattern switching PTMD D18 to D32 — — — — 0 OFF ON 0 OFF ON 0 — — 0 See D16 to D17 PTMD. — — All 0 ID EXP 0 D33 EXP ID/EXP output switching D34 to D35 PTOB OBCLP waveform pattern switching See D34 to D35 PTOB. D36 to D37 LDAD ADCLK logic phase adjustment See D36 to D37 LDAD. D38 to D39 STB D40 to D47 All 0 All 0 1 0 Standby control — See D38 to D39 STB. — — ∗1 See D13 SMD. – 16 – — All 0 All 0 CXD2498R Shutter Data Data Symbol Function Data = 0 Data = 1 RST D00 to D07 CHIP Chip enable 10000001 → Enabled Other values → Disabled All 0 D08 to D09 CTG Category switching See D08 to D09 CTG. All 0 D10 to D19 SVD Electronic shutter vertical period specification See D10 to D19 SVD. All 0 D20 to D31 SHD Electronic shutter horizontal period specification See D20 to D31 SHD. All 0 D32 to D41 SPL High-speed shutter position specification See D32 to D41 SPL. All 0 D42 to D47 — — – 17 – — 0 CXD2498R Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD2498R by the serial interface, the CXD2498R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 D08 Description of operation 0 0 Loading to control data register 0 1 Loading to shutter data register 1 X Test mode Note that the CXD2498R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D34 to D35 PTOB [OBCLP waveform pattern] This specifies the OBCLP waveform pattern. The default is “Normal”. See the Timing Charts for details. D35 D34 Waveform pattern 0 0 (Normal) 0 1 (Rearward) 1 0 (Forward) 1 1 (Wide) Control data: D36 to D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO. D37 D36 Degree of adjustment (°) 0 0 0 0 1 90 1 0 180 1 1 270 Control data: D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD2498R and control is applied immediately at the rising edge of SEN. D39 D38 Symbol Operating mode X 0 CAM Normal operating mode 0 1 SLP Sleep mode 1 1 STB Standby mode See the Pin Status Table for the pin status in each mode. – 18 – CXD2498R Control data: [Drive mode] The CXD2498R realizes various drive modes by using control data D10 to D11 MODE and D16 to D17 PTMD. The drive mode bits are loaded to the CXD2498R and reflected at the falling edge of VD. These details are described below. First, the basic drive mode is assigned using the control data D10 to D11 MODE. D11 D10 Description of operation 0 0 Draft mode (default) 0 1 Progressive scan mode 1 0 Double speed mode 1 1 Frame mode Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX282. This is a high frame rate drive mode that can be used for purposes such as monitoring and auto focus (AF). Progressive scan mode is the pulse eliminator drive mode called double speed mode (1) in the ICX282. Pulse elimination is performed, but the frame data is obtained over one field period and corresponds to progressive scan drive, so it is called progressive scan mode in this data sheet. Double speed mode is the pulse eliminator drive mode called double speed mode (2) in the ICX282. Readout is applied with two lines added to provide an image which appears like frame mode with an increased frame rate. This drive mode is comprised of A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so on. Frame mode is the ICX282 drive mode in which the data for all lines are read. This drive mode is also comprised of A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so on like double speed mode. [Special drive modes] Of the above basic drive modes, when a drive mode other than double speed mode is specified, special drive modes can be specified using the control data D16 to D17 PTMD. Description of operation D17 D16 0 X Draft mode Progressive scan mode Frame mode 1 0 AF1 mode Center scan 1 mode Center scan 1 mode 1 1 AF2 mode Center scan 2 mode Center scan 2 mode Draft mode Progressive scan mode Frame mode See the Timing Charts for details of all drive modes. Note that center scan modes (3) and (4) in the ICX282 correspond to center scan 1 and 2 in frame mode, and center scan modes (1) and (2) in the ICX282 correspond to center scan 1 and 2 in progressive scan mode. – 19 – CXD2498R Control data/shutter data: [Electronic shutter] The CXD2498R realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 SMD. D13 Description of operation 0 Electronic shutter stopped mode 1 Electronic shutter mode The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB D31 D30 X D29 D28 0 0 1 D27 D26 1 D25 D24 1 0 0 LSB D23 D22 D21 D20 0 0 1 ↓ ↓ ↓ 1 C 3 1 SHD is expressed as 1C3H . [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [Electronic shutter mode] During this mode, the shutter data items have the following meanings. Symbol Data Description SVD D10 to D19 Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) SHD D20 to D31 Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) SPL D32 to D41 Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh) Note) The bit data definition area is assured in terms of the CXD2498R functions, and does not assure the CCD characteristics. The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors. (Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)} Concretely, when specifying high-speed shutter, SVD is set to “000h”. (See the figure.) During low-speed shutter, or in other words when SVD is set to “001h” or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). – 20 – CXD2498R VD SHD SVD V1A SUB WEN EXP SMD 1 1 SVD 002h 000h SHD 10Fh 050h Exposure time Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods. SPL 000 001 VD 002 SVD SHD V1A SUB WEN EXP SMD 1 1 SPL 001h 000h SVD 002h 000h SHD 10Fh 0A3h Exposure time Incidentally, SPL is counted as “000h”, “001h”, “002h” and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. – 21 – CXD2498R [HTSG control mode] This mode controls the V1A/B/C and V3A/B/C ternary level outputs (readout pulse block) using D14 HTSG. When control is applied, V pulse modulation does not occur during the readout period, and only normal V transfer is performed. D14 Description of operation 0 Readout pulse (SG) normal operation 1 HTSG control mode VD V1A SUB Vck WEN EXP HTSG 0 1 0 SMD 1 0 1 Exposure time [EXP pulse] The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The default is the “ID” pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time when it is high. The transition point is midpoint value (1515ck) of the last SUB pulse falling edge and each V1A/ B/C and V3A/B/C ternary output falling edge. When there is no SUB pulse, the later ternary output falling edge (1590ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for an image of operation. – 22 – Chart-1 Applicable CCD image sensor • ICX282 MODE Frame mode Vertical Direction Timing Chart A Field B Field VD 1013 1017 1 73 1059 1 78 27 32 HD SUB C High-speed sweep block A D High-speed sweep block B V1A V1B V1C V2 – 23 – V3A V3B V3C 1959 1957 1955 1953 1951 1949 1947 1945 1943 1 3 5 7 1 3 5 7 9 11 13 15 1941 1960 1958 1956 1954 CCD OUT 1952 V4 2 4 6 8 2 4 6 8 10 12 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 1059H in the A Field and 1017H in the B Field (2894ck in both cases). The B Field 1016H only has a 950ck period. Chart-2 Applicable CCD image sensor • ICX282 MODE Progressive scan mode Vertical Direction Timing Chart VD 1038 1 49 1038 1 54 49 54 HD SUB C High-speed sweep block E C High-speed sweep block E V1A V1B V1C V2 – 24 – V3A V3B V3C 1958 1957 1954 1953 1950 1949 2 5 6 1 2 5 6 9 10 13 14 1946 1958 1957 1954 1953 1950 CCD OUT 1949 V4 2 5 6 1 2 5 6 9 10 13 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 1038H period (2894ck). 1037H only has a 1922ck period. Chart-3 Applicable CCD image sensor • ICX282 MODE Double speed mode Vertical Direction Timing Chart A Field B Field VD 519 527 1 69 563 1 72 25 28 HD SUB H High-speed sweep block F I High-speed sweep block G V1A V1B V1C V2 – 25 – V3A V3B V3C 1957 1959 1953 1955 3 7 3 7 11 15 19 23 27 31 35 39 1 5 1 5 9 13 17 21 25 29 33 37 1949 1951 CCD OUT 1958 1960 V4 4 8 4 8 12 16 20 24 28 32 2 6 2 6 10 14 18 22 26 30 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 563H in the A Field and 527H in the B Field (3102ck in both cases). The B Field 525H has a 1700ck period and 526H has a 1699ck period. Chart-4 Vertical Direction Timing Chart Applicable CCD image sensor • ICX282 MODE Draft mode VD 249 1 2 249 1 2 HD SUB J J V1A V1B V1C V2 – 26 – V3A V3B V3C 1953 1957 1946 1950 6 5 14 21 30 37 2 1 10 17 26 33 1937 1941 1953 1957 1946 1950 CCD OUT 1937 1941 V4 6 5 14 21 30 37 2 1 10 17 26 33 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 249H (3022ck) period. 248H only has a 1294ck period. Chart-5 Applicable CCD image sensor • ICX282 MODE Frame mode (center scan 1) Vertical Direction Timing Chart A Field B Field VD 530 1 71 576 1 91 25 45 HD SUB C High-speed sweep block A K D Frame shift block High-speed sweep block B K Frame shift block V1A V1B V1C V2 – 27 – V3A V3B V3C 2 498 501 1 499 CCD OUT 497 V4 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 576H in the A Field and 530H in the B Field (2894ck in both cases). Chart-6 Applicable CCD image sensor • ICX282 MODE Frame mode (center scan 2) Vertical Direction Timing Chart A Field B Field VD 302 1 71 347 1 100 25 54 HD SUB C High-speed sweep block A K D Frame shift block High-speed sweep block B K Frame shift block V1A V1B V1C V2 – 28 – V3A V3B V3C 2 736 739 1 737 CCD OUT 735 V4 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 347H in the A Field and 302H in the B Field (2894ck in both cases). The B Field 301H only has a 1563ck period. Chart-7 Applicable CCD image sensor • ICX282 MODE Progressive scan mode (center scan 1) Vertical Direction Timing Chart VD 519 1 12 519 1 33 12 33 HD SUB C High-speed sweep block E K C Frame shift block High-speed sweep block E K Frame shift block V1A V1B V1C V2 V3B V3C 502 2 501 2 505 CCD OUT 502 V4 501 – 29 – V3A PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 519H (2894ck) period. 518H only has a 2408ck period. Chart-8 Applicable CCD image sensor • ICX282 MODE Progressive scan mode (center scan 2) Vertical Direction Timing Chart VD 295 1 17 295 1 47 17 47 HD SUB C High-speed sweep block E K C Frame shift block High-speed sweep block E K Frame shift block V1A V1B V1C V2 – 30 – V3A V3B V3C 738 2 737 741 2 738 CCD OUT 737 V4 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 295H (2894ck) period. Chart-9 Applicable CCD image sensor • ICX282 MODE Draft mode (AF1) Vertical Direction Timing Chart VD 125 1 9 125 1 19 9 19 HD SUB High-speed sweep block M High-speed sweep block J L M Frame shift block J L Frame shift block V1A V1B V1C V2 – 31 – V3A V3B V3C 577 581 2 570 574 6 561 565 2 577 581 6 570 574 CCD OUT 561 565 V4 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 125H (3022ck) period. 124H only has a 647ck period. Chart-10 Applicable CCD image sensor • ICX282 MODE Draft mode (AF2) Vertical Direction Timing Chart VD 63 1 63 1 27 13 13 HD SUB M High-speed sweep block J L M Frame shift block High-speed sweep block J L Frame shift block V1A V1B V1C V2 – 32 – V3A V3B V3C 2 865 869 6 858 862 CCD OUT 849 853 V4 6 2 PBLK OBCLP CLPDM ID/EXP WEN CXD2498R ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is 63H (3022ck) period. 62H only has a 324ck period. Chart-11 MODE Frame mode (including center scan 1 and 2) Progressive scan mode (including center scan 1 and 2) Horizontal Direction Timing Chart (2894) 0 50 100 150 200 250 300 350 400 Applicable CCD image sensor • ICX282 450 500 550 HD MCKO 62 4 270 298 310 314 H1A/B H2A/B 166 89 V1A/B/C 219 141 V2 193 62 V3A/B/C 245 115 V4 – 33 – 176 234 SUB 62 296 PBLK 52 24 OBCLP (1) 44 16 OBCLP (2) 32 60 OBCLP (3) 16 60 OBCLP (4) 272 296 CLPDM 115 ID/EXP 115 WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1, 2, 5, 6, 7 and 8. CXD2498R ∗ ∗ ∗ ∗ ∗ Chart-12 (3102) 0 50 100 Applicable CCD image sensor • ICX282 MODE Double speed mode Horizontal Direction Timing Chart 150 200 250 300 350 400 450 500 550 HD MCKO 62 4 478 506 518 522 H1A/B H2A/B 166 89 374 297 V1A/B/C 219 141 427 349 V2 193 62 401 270 V3A/B/C 115 245 453 323 V4 – 34 – 384 442 SUB 62 504 PBLK 52 24 OBCLP (1) 44 16 OBCLP (2) 32 60 OBCLP (3) 16 60 OBCLP (4) 480 504 CLPDM 115 ID/EXP 115 WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3. CXD2498R ∗ ∗ ∗ ∗ ∗ Chart-13 (3022) 0 50 100 Applicable CCD image sensor • ICX282 MODE Draft mode (including AF1 and 2) Horizontal Direction Timing Chart 150 200 250 300 350 400 450 500 550 HD MCKO 62 4 398 426 438 442 H1A/B H2A/B 104 73 188 157 272 241 356 325 V1A/B/C 126 94 210 178 294 262 378 346 V2 115 62 199 146 283 230 367 314 V3A/B/C 136 84 168 220 252 304 388 336 V4 – 35 – 307 365 SUB 62 424 PBLK 52 24 OBCLP (1) 44 16 OBCLP (2) 32 60 OBCLP (3) 16 60 OBCLP (4) 400 424 CLPDM 115 ID/EXP 115 WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-4, 9 and 10. CXD2498R ∗ ∗ ∗ ∗ ∗ Chart-14 Horizontal Direction Timing Chart (High-speed sweep: C) (2894) 0 50 MODE Frame mode (including center scan 1 and 2) Progressive scan mode (including center scan 1 and 2) 100 150 200 250 300 350 400 Applicable CCD image sensor • ICX282 450 500 550 HD MCKO 62 4 270 298 310 314 H1A/B H2A/B 114 62 218 166 322 270 530 478 426 374 V1A/B/C 88 192 140 244 296 400 348 504 452 556 V2 114 62 218 166 322 270 530 478 426 374 V3A/B/C 88 192 140 244 296 348 400 452 504 556 – 36 – V4 #1 #2 176 #3 #4 #5 234 SUB 62 PBLK 24 52 OBCLP CLPDM ID/EXP 115 WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. PBLK, OBCLP, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1, 2, 5, 6, 7 and 8. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 70H 2362ck (#1970) in the A Field of frame mode (including center scan 1 and 2), 47H 2884ck (#1335) in progressive scan mode, 10H 2842ck (#305) in progressive scan mode (center scan 1), and 16H 2846ck (#472) in progressive scan mode (center scan 2). CXD2498R ∗ ∗ ∗ ∗ ∗ ∗ Chart-15 Horizontal Direction Timing Chart (High-speed sweep: D) (2894) 0 50 100 Applicable CCD image sensor • ICX282 MODE Frame mode (including center scan 1 and 2) 150 200 250 300 350 400 450 500 550 HD MCKO 62 4 270 298 310 314 H1A/B H2A/B 62 98 134 206 170 242 314 278 350 422 386 530 494 458 V1A/B/C 80 116 152 224 188 260 332 296 368 440 404 548 512 476 V2 62 98 134 206 170 242 314 278 350 422 386 530 494 458 V3A/B/C – 37 – 80 116 152 188 224 260 332 296 368 404 440 476 548 512 V4 #1 #2 176 #3 #4 #5 #6 #7 234 SUB 62 PBLK 24 52 OBCLP CLPDM ID/EXP 115 WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. PBLK, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1, 5, and 6. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 24H 1670ck (#986) in the B Field of frame mode (including center scan 1 and 2). CXD2498R ∗ ∗ ∗ ∗ ∗ ∗ Chart-16 Horizontal Direction Timing Chart (High-speed sweep: H) (3102) 0 50 Applicable CCD image sensor • ICX282 MODE Double speed mode 100 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 478 506 518 522 H1A/B H2A/B 62 114 166 218 270 322 374 426 478 530 V1A/B/C 88 140 192 296 244 400 348 504 452 556 V2 62 114 166 218 270 322 374 426 478 530 V3A/B/C 88 140 192 244 296 400 348 452 504 556 – 38 – V4 #1 #2 #3 #4 384 #5 442 SUB PBLK OBCLP CLPDM ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 66H 314ck (#1970). CXD2498R ∗ ∗ ∗ ∗ ∗ Chart-17 Horizontal Direction Timing Chart (High-speed sweep: I) (3102) 0 50 100 Applicable CCD image sensor • ICX282 MODE Double speed mode 150 200 250 300 350 400 450 500 550 HD MCKO 62 4 506 518 522 478 H1A/B H2A/B 62 98 134 206 170 242 278 314 350 386 422 458 530 494 V1A/B/C 80 116 152 224 188 260 296 332 368 404 440 512 476 548 V2 62 98 134 206 170 242 278 314 350 386 422 458 530 494 V3A/B/C 80 116 152 188 224 260 296 332 368 404 440 476 512 548 V4 – 39 – #1 #2 #3 #4 #5 384 #6 #7 442 SUB 62 PBLK 24 52 OBCLP CLPDM ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 22H 2810ck (#986). CXD2498R ∗ ∗ ∗ ∗ ∗ Chart-18 Horizontal Direction Timing Chart (High-speed sweep: M) (3022) 0 50 100 Applicable CCD image sensor • ICX282 MODE Draft mode (AF1 and 2) 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 426 438 442 398 H1A/B H2A/B 73 104 157 188 241 272 325 356 409 440 493 524 V1A/B/C 94 126 178 210 262 294 346 378 430 462 514 546 V2 62 115 146 199 230 283 314 367 398 451 482 535 V3A/B/C – 40 – 84 136 168 220 252 304 336 388 420 472 556 504 V4 #1 #2 #3 #4 307 #5 #6 365 SUB PBLK OBCLP CLPDM ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B/C, V2, V3A/B/C and V4 is performed up to 7H 2848ck (#285) in draft mode (AF1), 11H 2184ck (#421) in draft mode (AF2). CXD2498R ∗ ∗ ∗ ∗ ∗ Chart-19 Horizontal Direction Timing Chart (Frame shift : K) (2894) 0 50 100 Applicable CCD image sensor • ICX282 MODE Frame mode (including center scan 1 and 2) Progressive scan mode (including center scan 1 and 2) 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 270 298 310 314 H1A/B H2A/B 89 166 297 374 505 V1A/B/C 141 219 349 557 427 V2 62 193 270 401 478 V3A/B/C – 41 – 115 245 323 453 531 V4 #1 #2 176 #3 234 SUB PBLK OBCLP CLPDM ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. Frame shift of V1A/B/C, V2, V3A/B/C and V4 is performed up to 90H 2864ck (#250) in the A Field of frame mode (center scan 1), 44H 2864ck (#250) in the B Field, 99H 1570ck (#369) in the A Field of frame mode (center scan 2), 53H 1570ck (#369) in the B Field, 32H 2864ck (#250) in progressive scan mode (center scan 1), and 46H 1646ck (#369) in progressive scan mode (center scan 2). CXD2498R ∗ ∗ ∗ ∗ ∗ Chart-20 Horizontal Direction Timing Chart (Frame shift: L) (3022) 0 50 100 Applicable CCD image sensor • ICX282 MODE Draft mode (AF1 and 2) 150 200 250 300 350 400 450 500 550 HD MCKO 4 62 426 438 442 398 H1A/B H2A/B 73 104 157 188 241 272 325 356 409 440 524 493 V1A/B/C 94 126 178 210 262 294 346 378 430 462 514 546 V2 62 115 146 199 230 283 314 367 398 451 482 535 V3A/B/C – 42 – 84 136 168 220 252 304 336 388 420 472 556 504 V4 #1 #2 #3 #4 307 #5 #6 365 SUB PBLK OBCLP CLPDM ID/EXP WEN The HD of this chart indicates the actual CXD2498R load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. SUB is output at the timing shown above when output is controlled by the serial interface data. Frame shift of V1A/B/C, V2, V3A/B/C and V4 is performed up to 18H 2092ck (#276) in draft mode (AF1), 22H 2100ck (#420) in draft mode (AF2). CXD2498R ∗ ∗ ∗ ∗ ∗ 245 219 193 166 141 115 (2894) 0 89 Applicable CCD image sensor • ICX282 62 1710 1680 1650 1620 1590 1560 1530 1470 1440 1380 323 297 270 245 219 193 166 141 115 89 (2894) 0 1410 MODE Frame mode (including center scan 1 and 2) Horizontal Direction Timing Chart 62 Chart-21 HD [A Field] A V1A V1B V1C V2 V3A V3B – 43 – V3C V4 B [B Field] V1A V1B V1C V2 V3A V3B V3C V4 Logic alignment portion CXD2498R ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. 245 219 193 166 141 115 (2894) 0 89 Applicable CCD image sensor • ICX282 62 1710 1680 1650 1620 1590 1560 1530 1500 1470 1440 1380 323 297 270 245 219 193 166 141 115 89 (2894) 0 1410 MODE Progressive scan mode (including center scan 1 and 2) Horizontal Direction Timing Chart 62 Chart-22 HD E V1A V1B V1C V2 V3A – 44 – V3B V3C V4 ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. CXD2498R (3102) 0 62 89 115 141 166 193 219 245 270 297 323 349 374 1710 1680 1650 1620 1590 1560 1530 1470 1440 1410 1380 (3102) 0 Applicable CCD image sensor • ICX282 MODE Double speed mode Horizontal Direction Timing Chart 62 89 115 141 166 193 219 245 270 297 323 349 374 401 427 453 478 505 531 Chart-23 HD [A Field] F V1A V1B V1C V2 V3A V3B V3C – 45 – V4 G [B Field] V1A V1B V1C V2 V3A V3B V3C V4 Logic alignment portion CXD2498R ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. (3022) 0 62 73 84 94 104 115 126 136 146 157 168 178 188 199 210 220 230 241 252 262 272 283 294 304 314 1590 1560 1530 1500 1470 1440 1410 1380 1350 1320 1290 (3022) 0 Applicable CCD image sensor • ICX282 MODE Draft mode (including AF1 and 2) Horizontal Direction Timing Chart 62 73 84 94 104 115 126 136 146 157 168 178 188 199 210 220 230 241 252 262 272 283 294 304 314 325 336 346 356 367 378 388 Chart-24 HD J V1A V1B V1C V2 V3A V3B V3C – 46 – V4 ∗ The HD of this chart indicates the actual CXD2498R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.8 to 12.0µs (when the drive frequency is 22.5MHz). This chart shows an period of 115ck (5.1µs). Internal SSG is at this timing. CXD2498R Chart-25 High-Speed Phase Timing Chart Applicable CCD image sensor • ICX282 MODE HD HD' CKI CKO ADCLK 1 62 270/398/478 MCKO – 47 – H1A/B H2A/B RG XSHP XSHD ∗ HD’ indicates the HD which is the actual CXD2498R load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data. CXD2498R Chart-A1 Applicable CCD image sensor • ICX282 MODE Draft → Frame (or double speed) → Draft Vertical Direction Sequence Chart VD V1A V1B V1C V2 V3A – 48 – V3B V3C V4 SUB Mechanical shutter Close Exposure time A CCD OUT MODE C D A B C 0 0 0 E F E 0 3 This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD2498R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data are not the same. E 3 F 0 0 CXD2498R ∗ ∗ ∗ ∗ 0 B Open Chart-A2 Applicable CCD image sensor • ICX282 MODE Draft → Progressive scan → Draft Vertical Direction Sequence Chart VD V1A V1B V1C V2 V3A – 49 – V3B V3C V4 SUB Mechanical shutter Close Exposure time A CCD OUT MODE C D A B C 0 0 0 E F E 0 1 This chart is a drive timing chart example of electronic shutter normal operation. Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet. The CXD2498R does not generate the pulse to control mechanical shutter operation. The switching timing of drive mode and electronic shutter data are not the same. G F 0 0 H G H 0 0 CXD2498R ∗ ∗ ∗ ∗ 0 B Open CXD2498R Application Circuit Block diagram CCD OUT Digital OUT ADCLK OBCLP CLPDM PBLK XSHD CDS/ADC Block XSHP CCD ICX282 18 19 20 21 22 23 V1A V1B V1C V2 V3A V3B V3C V4 SUB 4 15 5 8 40 25 42 30 TG CXD2498R 43 34 SSG 38 44 35 ID/EXP WEN CKO MCKO Signal Processor Block VD HD V-Dr 46 47 39 2 RST 3 SNCSL 6 SSGSL 48 CKI 26 27 28 31 32 33 VCO SEN RG 13 SCK H2B 12 SSI H2A 10 TEST2 H1B TEST1 H1A Controller Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes for Power-on Of the three –7.5V, +15.0V, +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential. 15.0V t1 20% 0V 20% t2 t2 ≥ t1 –7.5V – 50 – CXD2498R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 S 25 13 0.5 ± 0.2 B A 48 (8.0) 24 37 (0.22) 12 1 + 0.05 0.127 – 0.02 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 0.13 M 0.1 S 0.5 ± 0.2 0.18 ± 0.03 0˚ to 10˚ 0.127 ± 0.04 0.1 ± 0.1 DETAIL B:PALLADIUM DETAIL A NOTE: Dimension “ ∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN PALLADIUM PLATING SONY CODE LQFP-48P-L01 LEAD TREATMENT EIAJ CODE LQFP048-P-0707 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 51 – Sony Corporation