CXD2492R Timing Generator for Frame Readout CCD Image Sensor For the availability of this product, please contact the sales office. Description The CXD2492R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX252 CCD image sensor. 48 pin LQFP (Plastic) Features • Base oscillation frequency 24 to 36MHz • High-speed/low-speed shutter function • Draft (sextuple speed)/AF (auto focus) drive • Horizontal driver for CCD image sensor • Vertical driver for CCD image sensor Absolute Maximum Ratings VSS – 0.3 to +7.0 • Supply voltage VDD VL –10.0 to VSS VH VL – 0.3 to +26.0 • Input voltage VI VSS – 0.3 to VDD + 0.3 • Output voltage VO1 VSS – 0.3 to VDD + 0.3 Applications Digital still cameras Structure Silicon gate CMOS IC VO2 VO3 • Operating temperature Topr • Storage temperature Tstg Applicable CCD Image Sensors ICX252 (Type 1/1.8, 3240K pixels) VSS6 HD VD SEN SCK SSI MCKO VDD5 OSCI OSCO CKI CKO Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 TEST1 37 24 VSS5 VM 38 23 ADCLK V2 39 22 OBCLP V4 40 21 VSS4 V1A 41 20 CLPDM VH 42 19 PBLK V1B 43 18 XRS V3A 44 17 XSHD 4 5 6 7 8 9 10 11 12 H1 3 VSS3 2 RG 1 VSS2 13 H2 VDD2 48 VDD1 TEST2 WEN 14 VDD3 SSGSL 15 VDD4 47 ID 46 SUB SNCSL 16 XSHP RST 45 VSS1 VL V3B V V V V VL – 0.3 to VSS + 0.3 VL – 0.3 to VH + 0.3 V V V –20 to +75 °C –55 to +150 °C Recommended Operating Conditions • Supply voltage VDDb 3.0 to 5.5 VDDa, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75 V V V V V °C ∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99730-PS CXD2492R OSCI OSCO CKI VDD4 15 16 17 18 21 VSS4 VSS2 10 XRS RG XSHP VDD2 9 28 27 19 PBLK 20 CLPDM 26 22 OBCLP CKO 25 MCKO 30 SNCSL XSHD VSS3 8 H2 14 12 13 11 H1 VDD3 Block Diagram 3 Pulse Generator 23 ADCLK 1/2 24 VSS5 Latch Selector 4 ID 5 WEN 41 V1A 43 V1B SSI 31 39 V2 SCK 32 Register 44 V3A SEN 33 6 RST 2 46 V3B V Driver Selector SSGSL SSG 40 V4 47 SUB 42 VH TEST1 37 38 VM TEST2 48 1 36 –2– VDD5 VSS1 VSS6 35 34 VD 29 HD 7 VDD1 45 VL CXD2492R Pin Description Pin No. Symbol I/O Description 1 VSS1 — 2 RST I Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side 3 SNCSL I Control input used to switch sync system. High: CKI sync, Low: MCKO sync With pull-down resistor 4 ID O Vertical direction line identification pulse output. 5 WEN O Memory write timing pulse output. 6 SSGSL I 7 VDD1 — 3.3V power supply. (Power supply for common logic block) 8 VDD2 — 3.3V power supply. (Power supply for RG) 9 RG O CCD reset gate pulse output. 10 VSS2 — GND 11 VSS3 — GND 12 H1 O CCD horizontal register clock output. 13 H2 O CCD horizontal register clock output. 14 VDD3 — 3.3 to 5.0V power supply. (Power supply for H1/H2) 15 VDD4 — 3.3V power supply. (Power supply for CDS block) 16 XSHP O CCD precharge level sample-and-hold pulse output. 17 XSHD O CCD data level sample-and-hold pulse output. 18 XRS O Sample-and-hold pulse output for analog/digital conversion phase alignment. 19 PBLK O Pulse output for horizontal and vertical blanking period pulse cleaning. 20 CLPDM O CCD dummy signal clamp pulse output. 21 VSS4 — GND 22 OBCLP O CCD optical black signal clamp pulse output. 23 ADCLK O Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. 24 VSS5 — GND 25 CKO O Inverter output. 26 CKI I Inverter input. 27 OSCO O Inverter output for oscillation. 28 OSCI I Inverter input for oscillation. 29 VDD5 — 3.3V power supply. (Power supply for common logic block) 30 MCKO O System clock output for signal processing IC. GND Internal SSG enable. High: Internal SSG valid, Low: External sync valid With pull-down resistor –3– When not used, leave open or connect a capacitor. When not used, fix low. CXD2492R Pin No. Symbol I/O Description 31 SSI I Serial interface data input for internal mode settings. Schmitt trigger input/No protective diode on power supply side 32 SCK I Serial interface clock input for internal mode settings. Schmitt trigger input/No protective diode on power supply side 33 SEN I Serial interface strobe input for internal mode settings. Schmitt trigger input/No protective diode on power supply side 34 VD I/O Vertical sync signal input/output. 35 HD I/O Horizontal sync signal input/output. 36 VSS6 — GND 37 TEST1 38 VM — GND (GND for vertical driver) 39 V2 O CCD vertical register clock output. 40 V4 O CCD vertical register clock output. 41 V1A O CCD vertical register clock output. 42 VH — 15.0V power supply. (Power supply for vertical driver) 43 V1B O CCD vertical register clock output. 44 V3A O CCD vertical register clock output. 45 VL — –7.5V power supply. (Power supply for vertical driver) 46 V3B O CCD vertical register clock output. 47 SUB O CCD electronic shutter pulse output. 48 TEST2 I IC test pin 2; normally fixed to GND. I IC test pin 1; normally fixed to GND. –4– With pull-down resistor With pull-down resistor CXD2492R Electrical Characteristics DC Characteristics (Within the recommended operating conditions) Item Pins Symbol Conditions Min. Typ. Max. Unit Supply voltage 1 VDD2 VDDa 3.0 3.3 3.6 V Supply voltage 2 VDD3 VDDb 3.0 3.3 5.5 V Supply voltage 3 VDD4 VDDc 3.0 3.3 3.6 V Supply voltage 4 VDD1, VDD5 VDDd 3.0 3.3 3.6 V Input voltage 1∗1 RST Vt+ SSI, SCK, Input voltage 2∗2 SEN, Vt+ Input voltage 3∗3 TEST1, TEST2 VIH1 SNCSL, Input voltage 4∗4 SSGSL VIH2 0.8VDDd 0.2VDDd V Vt– 0.8VDDd Vt– VD, HD 0.7VDDd VIL1 0.7VDDd VOL1 Pull-in current where IOL = 2.4mA VOH2 Feed current where IOH = –22.0mA VDDb – 0.8 VOL2 Pull-in current where IOL = 14.4mA VOH3 Feed current where IOH = –3.3mA VOL3 Pull-in current where IOL = 2.4mA Output voltage 3 XSHP, XSHD, VOH4 XRS, PBLK, OBCLP, CLPDM, VOL4 ADCLK CKO Output voltage 5 MCKO Output current 1 Output current 2 ∗1 ∗2 ∗3 ∗4 V1A, V1B, V3A, V3B, V2, V4 SUB V 0.2VDDd V Feed current where IOH = –1.2mA RG Output voltage 4 0.8VDDd VOH1 Output voltage 2 V 0.3VDDd V VIL3 H1, H2 V 0.2VDDd V VIL2 Output voltage 1 V 0.2VDDd V VIH3 Input/output voltage V Feed current where IOH = –3.3mA VDDd – 0.8 0.4 Feed current where IOH = –6.9mA VOL5 Pull-in current where IOL = 4.8mA VOH6 Feed current where IOH = –3.3mA VOL6 Pull-in current where IOL = 2.4mA IOL V1A/B, V2, V3A/B, V4 = –8.25V IOM1 V1A/B, V2, V3A/B, V4 = –0.25V IOM2 V1A/B, V3A/B = 0.25V IOH V1A/B, V3A/B = 14.75V IOSL SUB = –8.25V IOSH SUB = 14.75V V V 0.4 VDDa – 0.8 V V 0.4 VDDc – 0.8 Pull-in current where IOL = 2.4mA VOH5 V V V 0.4 VDDd – 0.8 V V 0.4 VDDd – 0.8 V V 0.4 10.0 V mA –5.0 mA mA 5.0 –7.2 mA mA 5.4 –4.0 mA This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC. These input pins are schmitt trigger inputs. These input pins are with pull-down resistor in the IC. These input pins are with pull-down resistor in the IC and they do not have protective diode of the power supply side in the IC. Note) The above table indicates the condition for 3.3V drive. –5– CXD2492R Inverter I/O Characteristics for Oscillation Item Pins Logical Vth OSCI Input voltage OSCI Output voltage OSCO Feedback resistor Oscillation frequency Symbol (Within the recommended operating conditions) Conditions Min. LVth Typ. Max. VDDd/2 VIH V 0.7VDDd V VIL 0.3VDDd VOH Feed current where IOH = –3.6mA VOL Pull-in current where IOL = 2.4mA OSCI, OSCO RFB VIN = VDDd or VSS OSCI, OSCO f VDDd – 0.8 500k Unit V V 2M 20 0.4 V 5M Ω 50 MHz Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Pins Symbol Logical Vth LVth Input voltage VIH CKI Input amplitude Conditions Min. Typ. VDDd/2 V 0.3VDDd fmax 50MHz sine wave Unit V 0.7VDDd VIL VIN Max. 0.3 V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Rise time Fall time Output noise voltage (VH = 15.0V, VM = GND, VL = –7.5V) Symbol Conditions Min. Typ. Max. Unit TTLM VL to VM 200 350 500 ns TTMH VM to VH 200 350 500 ns TTLH VL to VH 30 60 90 ns TTML VM to VL 200 350 500 ns TTHM VH to VM 200 350 500 ns TTHL VH to VL 30 60 90 ns VCLH 1.0 V VCLL 1.0 V VCMH 1.0 V VCML 1.0 V Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –6– CXD2492R Switching Waveforms TTMH TTHM VH V1A (V1B, V3A, V3B) TTLM 90% 90% 10% 10% TTML VM 90% 90% 10% 10% TTML TTLM VL VM 90% 90% V2 (V4) 10% 10% TTLH TTHL 90% VL VH 90% SUB 10% 10% VL Waveform Noise VH VCMH VCML VCLH VCLL VL –7– CXD2492R Measurement Circuit Serial interface data CKI VD HD C6 +3.3V –7.5V C6 +15.0V 36 35 34 33 32 31 30 29 28 27 26 25 R1 C2 C2 R1 R1 C1 C2 C1 C2 C2 R1 C2 C2 C2 C2 C1 C2 C1 C2 C2 C1 24 38 23 39 22 40 21 41 20 42 19 CXD2492R 43 C2 R1 C1 C2 R2 C2 37 18 44 17 45 16 46 15 47 14 13 48 C3 R1 1 2 3 4 5 6 7 8 9 10 11 12 C4 C1 R1 3300pF 30Ω C2 R2 560pF 10Ω C3 820pF C4 30pF –8– C5 215pF C6 C5 10pF C6 C6 C6 C6 C6 C6 C6 C5 CXD2492R AC Characteristics AC characteristics between the serial interface clocks 0.8VDDd SSI 0.2VDDd 0.8VDDd SCK ts1 SEN th1 0.2VDDd ts3 0.8VDDd SEN ts2 (Within the recommended operating conditions) Symbol ts1 th1 ts2 ts3 Definition Min. Typ. Max. Unit SSI setup time, activated by the rising edge of SCK 20 ns SSI hold time, activated by the rising edge of SCK 20 ns SCK setup time, activated by the rising edge of SEN 20 ns SEN setup time, activated by the rising edge of SCK 20 ns Serial interface clock internal loading characteristics (1) Example: During frame mode VD HD V1A Enlarged view HD 0.2VDDd V1A ts1 th1 0.8VDDd SEN 0.2VDDd ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit SEN setup time, activated by the falling edge of HD 0 ns SEN hold time, activated by the falling edge of HD 102 µs –9– CXD2492R Serial interface clock internal loading characteristics (2) Example: During frame mode VD HD Enlarged view VD 0.2VDDd HD ts1 th1 0.8VDDd SEN 0.2VDDd ∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD. (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit SEN setup time, activated by the falling edge of VD 0 ns SEN hold time, activated by the falling edge of VD 200 ns Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2492R at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD2492R and controlled at the rising edge of SEN. See "Description of Operation". SEN 0.8VDDd Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. tpdPULSE Output signal delay, activated by the rising edge of SEN – 10 – 5 Typ. Max. Unit 100 ns CXD2492R RST loading characteristics 0.8VDDd RST 0.2VDDd tw1 (Within the recommended operating conditions) Definition Symbol tw1 Min. RST pulse width Typ. Max. Unit ns 35 VD and HD loading characteristics VD, HD 0.2VDDd 0.2VDDd ts1 th1 0.8VDDd MCKO MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit VD and HD setup time, activated by the rising edge of MCKO 20 ns VD and HD hold time, activated by the rising edge of MCKO 5 ns Output variation characteristics MCKO 0.8VDDd WEN, ID tpd1 WEN and ID load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Min. Time until the above outputs change after the rise of MCKO 20 – 11 – Typ. Max. Unit 60 ns CXD2492R Description of Operation Pulses output from the CXD2492R are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on the following pages. Pin Status Table Pin No. Symbol CAM SLP STB RST Pin No. Symbol CAM SLP STB RST 25 CKO ACT ACT L ACT L 26 CKI ACT ACT ACT ACT ACT ACT 27 OSCO ACT ACT ACT ACT L L L 28 OSCI ACT ACT ACT ACT ACT L L L 29 VDD5 ACT ACT ACT ACT 30 MCKO ACT ACT L ACT — 31 SSI ACT ACT ACT DIS — 32 SCK ACT ACT ACT DIS 33 ACT ACT ACT DIS 34 SEN VD∗1 ACT L L H 35 HD∗1 ACT L L H ACT 36 VSS6 — ACT 37 TEST1 — — 38 VM — — 39 V2 ACT VM VM VM ACT 40 V4 ACT VM VM VL L ACT 41 V1A ACT VH VH VM L L ACT 42 VH ACT L L H 43 V1B ACT VH VH VM ACT L L H 44 V3A ACT VH VH VL 45 VL H 46 V3B ACT VH VH VL ACT 47 SUB ACT VH VH VL 48 TEST2 1 VSS1 2 RST ACT ACT ACT 3 SNCSL ACT ACT 4 ID ACT 5 WEN 6 SSGSL 7 VDD1 8 VDD2 9 RG 10 VSS2 — 11 VSS3 — 12 H1 ACT L L 13 H2 ACT L L 14 VDD3 15 VDD4 16 XSHP ACT L L 17 XSHD ACT L 18 XRS ACT 19 PBLK 20 CLPDM 21 VSS4 22 OBCLP ACT L L 23 ADCLK ACT L L 24 VSS5 — ACT L L ACT — — — — — — ∗1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45), respectively, in the controlled status. – 12 – CXD2492R Serial Interface Control The CXD2492R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN. SSI 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 SCK SEN There are two categories of serial interface data: CXD2492R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below. – 13 – CXD2492R Control Data Data Symbol Data = 0 Function D00 to D07 CHIP Chip enable D08 to D09 CTG Category switching D10 to D12 MODE Drive mode switching D13 to D14 SMD Electronic shutter mode switching D15 PTSG Internal SSG output pattern switching D16 to D23 CDAT AF drive control data Data = 1 RST 10000001 → Enabled Other values → Disabled All 0 See D08 to D09 CTG. All 0 See D10 to D12 MODE. All 0 See D13 to D14 SMD. All 0 NTSC equivalent PAL equivalent See D16 to D23 CDAT. 0 All 0 D24 to D33 — — — — All 0 D34 — — — — 1 D35 — — — — 0 D36 to D37 LDAD D38 to D39 STB D40 to D47 1 ADCLK logic phase switching See D36 to D37 LDAD. 0 Standby control — See D38 to D39 STB. — — – 14 – — All 0 All 0 CXD2492R Shutter Data Data Symbol Function D00 to D07 CHIP Chip enable D08 to D09 CTG D10 to D19 Data = 0 Data = 1 RST 10000001 → Enabled Other values → Disabled All 0 Category switching See D08 to D09 CTG. All 0 SVD Electronic shutter vertical period specification See D10 to D19 SVD. All 0 D20 to D31 SHD Electronic shutter horizontal period specification See D20 to D31 SHD. All 0 D32 to D41 SPL High-speed shutter position specification See D32 to D41 SPL. All 0 D42 to D47 — — — – 15 – — All 0 CXD2492R Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD2492R by the serial interface, the CXD2492R loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 D08 Description of operation 0 0 Loading to control data register 0 1 Loading to shutter data register 1 X Test mode Note that the CXD2492R can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D10 to D12 MODE [Drive mode] The CXD2492R drive mode can be switched as follows. However, the drive mode bits are loaded to the CXD2492R and reflected at the falling edge of VD. D12 D11 D10 Description of operation 0 0 0 Draft mode (sextuple speed: default) 0 0 1 Frame mode (A field readout) 0 1 0 Frame mode (B field readout) 0 1 1 Frame mode 1 0 X AF1 mode 1 1 X AF2 mode Control data: D15 PTSG [Internal SSG output pattern] The CXD2492R internal SSG output pattern can be switched as follows. However, the drive mode bits are loaded to the CXD2492R and reflected at the falling edge of VD. D15 Description of Operation 0 NTSC equivalent pattern 1 PAL equivalent pattern VD period in each pattern is defined as follows. NTSC equivalent pattern PAL equivalent pattern Frame mode Draft mode AF1 mode AF2 mode 918H + 1716ck 945H∗1 262H + 1144ck 131H + 572ck 65H + 1430ck 314H + 1568ck 157H + 784ck 78H + 1536ck ∗1 Only 944H and 945H are 1208ck period. See the Timing Charts for the actual operation. – 16 – CXD2492R Control data: D36 to D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO. D37 D36 Degree of adjustment (°) 0 0 0 0 1 90 1 0 180 1 1 270 Control data: D38 to D39 STB [Standby] The operating mode is switched as follows. However, the standby bits are loaded to the CXD2492R and control is applied immediately at the rising edge of SEN. D39 D38 Symbol Operating mode X 0 CAM Normal operating mode 0 1 SLP Sleep mode 1 1 STB Standby mode See the Pin Status Table for the pin status in each mode. – 17 – CXD2492R Control data: [AF drive] The CXD2492R controls the drive of the vertical cut-out area of line in AF1/AF2 mode by using control data D16 to D23 CDAT. This mode has a function on purpose to raise frame rate for auto focus (AF), and this mode cannot support operation such as electrical image stabilization. AF drive bits are loaded to the CXD2492R and reflected at the falling edge of VD. As shown in the figure below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical OB period. Then normal transfer is performed equivalent to draft mode from the frame shift of the stage specified by the serial interface data to the timing of the falling edge of the next VD. Therefore, the number of frame shift stages applied to CDAT and the control by VD period are conditions for its application. VD High-speed sweep Normal transfer Frame shift V1A Vck MODE 0 4 0 CDAT 00h FFh 00h The number of high-speed sweeps are different according to the selected mode. It is specified as follows. AF1 mode: 138 stages (0 to 7H) AF2 mode: 208 stages (0 to 11H) The frame shift data is expressed as shown in the table below using D16 to D23 CDAT. MSB D23 0 LSB D22 D21 1 ↓ 6 1 D20 0 D19 D18 1 0 D17 D16 0 1 ↓ 9 → CDAT is expressed as 69h . Its definition area is specified as follows. AF1 mode: 00h ≤ CDAT ≤ FFh (11 to 23H) AF2 mode: 00h ≤ CDAT ≤ FFh (14 to 27H) – 18 – CXD2492R Control data/shutter data: [Electronic shutter] The CXD2492R realizes various electronic shutter functions by using control data D13 to D14 SMD and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 to D14 SMD. D14 D13 0 0 0 1 1 0 1 1 Description of operation Electronic shutter stopped mode High-speed/low-speed shutter mode HTSG control mode The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as dummy on this IC. MSB LSB D31 D30 X 0 ↓ 1 D29 D28 D27 D26 0 1 1 1 ↓ C D25 D24 0 0 D23 D22 0 0 D21 D20 ↓ 3 1 1 → SHD is expressed as 1C3h . [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [High-speed/low-speed shutter mode] During this mode, the shutter data items have the following meanings. Symbol Data Description SVD D10 to D19 Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) SHD D20 to D31 Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) SPL D32 to D41 Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh) The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). However, in the frame mode A field, it matches (number of SUB pulses + 1). This is a specification for flickerless when the same mode is repeated. But this change may not occur because of flickerless by the conditions during low-speed shutter. Note) The bit data definition area is assured in terms of the CXD2492R functions, and does not assure the CCD characteristics. – 19 – CXD2492R VD SVD SHD V1A SUB WEN SMD 01 SVD 002h 000h SHD 10Fh 050h 01 Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods. SPL VD SVD SHD V1A SUB WEN 01 SMD 10 SPL 001h 000h SVD 002h 000h SHD 10Fh 0A3h Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa. – 20 – CXD2492R [HTSG control mode] During this mode, all shutter data items are invalid. The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure. VD V1A Exposure time SUB Vck WEN SMD 11 01 – 21 – 01 – 22 – WEN ID CLPDM OBCLP PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD 810 C 1 High-speed sweep block A 29 34 1 3 5 7 1 3 5 7 9 11 13 15 A Field MODE Frame mode 1549 1547 1545 1543 1541 1539 1548 1546 1544 1542 810 918 C 1 High-speed sweep block • ICX252 B 28 B Field 34 2 4 6 8 2 4 6 8 10 12 Applicable CCD image sensor ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (918H + 1716ck units). For PAL equivalent pattern, it is 945H units, but 1208ck period as for 944H and 945H. 918 Vertical Direction Timing Chart 1550 Chart-1 CXD2492R – 23 – WEN ID CLPDM OBCLP PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD Chart-2 527 534 539 546 6 3 10 15 22 27 34 4 1 8 13 20 25 32 MODE Draft mode 525 532 537 544 549 527 534 539 546 D 6 3 10 15 22 27 34 4 1 8 13 20 25 32 261 262 1 2 • ICX252 Applicable CCD image sensor ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (262H + 1144ck units). For PAL equivalent pattern, it is 314H + 1568ck units. 525 532 537 544 549 D 261 262 1 2 Vertical Direction Timing Chart CXD2492R – 24 – WEN ID CLPDM OBCLP PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD Chart-3 8 6 4 G 10 Frame shift block 8 F High-speed sweep block D 131 1 6 4 G 10 Frame shift block • ICX252 AF1 mode 25 Applicable CCD image sensor MODE 25 ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ 138 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block. ∗ VD of this chart is NTSC equivalent pattern (131H + 572ck units). For PAL equivalent pattern, it is 157H + 784ck units. F High-speed sweep block D 131 1 Vertical Direction Timing Chart CXD2492R – 25 – WEN ID CLPDM OBCLP PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD Chart-4 High-speed sweep block D 12 6 4 G 14 Frame shift block MODE AF2 mode 29 F 65 1 High-speed sweep block 6 4 D G 12 • ICX252 14 Frame shift block Applicable CCD image sensor ∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ 208 stages are fixed for high-speed sweep block; 0 to 255 stages are specified by the serial interface for frame shift block. ∗ VD of this chart is NTSC equivalent pattern (65H + 1430ck units). For PAL equivalent pattern, it is 78H + 1536ck units. F 65 1 Vertical Direction Timing Chart 29 CXD2492R – 26 – (2228) 0 10 47 52 52 52 50 70 Horizontal Direction Timing Chart 70 90 99 100 110 110 110 128 MODE Frame mode 138 148 150 157 174 172 198 198 200 • ICX252 250 Applicable CCD image sensor ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-1. WEN ID CLPDM OBCLP PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD Chart-5 CXD2492R – 27 – WEN ID CLPDM OBCLP PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD (2228) 0 10 47 52 52 52 52 50 64 71 64 71 Horizontal Direction Timing Chart 71 83 83 90 90 102 100 102 109 110 110 109 121 121 128 128 140 140 140 147 MODE Draft/AF1/AF2 mode 147 150 159 159 174 172 198 198 200 • ICX252 250 Applicable CCD image sensor ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ ID and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4. Chart-6 CXD2492R – 28 – (2228) 0 52 52 52 50 70 71 Horizontal Direction Timing Chart (High-speed sweep: C) 71 #1 81 81 100 110 110 129 129 139 138 #2 139 150 158 158 168 168 172 187 187 197 #3 197 200 216 216 226 226 245 245 255 250 • ICX252 Frame mode 100 100 Applicable CCD image sensor MODE #4 255 274 ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 26H of 768ck (#1038). WEN ID CLPDM OBCLP PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD Chart-7 274 CXD2492R – 29 – (2228) 0 10 47 52 52 52 52 50 64 71 64 71 Horizontal Direction Timing Chart (High-speed sweep: F) (Frame shift: G) 71 83 83 90 90 102 100 109 105 110 #1 102 109 121 121 128 128 MODE AF1/AF2 mode 140 140 140 147 147 150 159 159 166 166 178 172 178 185 185 197 197 204 200 204 216 • ICX252 219 216 223 #2 223 235 235 242 242 254 250 Applicable CCD image sensor 254 261 261 273 ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. ∗ SUB is output at the timing shown above when output is controlled by the serial interface data. ∗ WEN are output at the timing shown above at the position shown in Chart-3 and 4. ∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 6H of 2056ck (#138) in AF1 mode and 10H of 884ck (#208) in AF2 mode. ∗ Frame shift of V1A/B, V2, V3A/B and V4 receives the output control by the serial interface data and it can specify up to #255 for both of AF1/AF2 mode. ∗ ID is output at the timing shown with dotted line during frame shift. WEN ID CLPDM OBCLP PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD Chart-8 273 280 CXD2492R – 30 – V4 V3B V3A V2 V1B V1A V4 V3B V3A V2 V1B V1A HD 241 211 181 148 157 Logic alignment portion [B] [A] • ICX252 (2288) 0 52 128 90 99 110 70 52 Applicable CCD image sensor 148 157 128 1310 1280 1250 1190 1160 1130 ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. [B Field] [A Field] (2288) 0 1100 MODE Frame mode 70 Horizontal Direction Timing Chart 90 99 110 Chart-9 CXD2492R – 31 – [D] 1220 1190 1160 1130 1100 1070 1040 159 140 147 121 128 102 109 83 90 64 71 52 (2288) 0 • ICX252 159 140 147 121 128 1430 1400 1370 1340 1310 1280 1010 ∗ The HD of this chart indicates the actual CXD2492R load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at the timing. V4 V3B V3A V2 V1B V1A HD (2288) 0 1250 Draft /AF1/AF2 mode 52 Applicable CCD image sensor 64 71 MODE 83 90 Horizontal Direction Timing Chart 102 109 Chart-10 CXD2492R – 32 – XRS XSHD XSHP RG H2 H1 MCKO ADCLK CKO CKI HD' HD Chart-11 1 MODE 52 • ICX252 172 Applicable CCD image sensor ∗ HD' indicates the HD which is the actual CXD2492R load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data. High-speed Phase Timing Chart CXD2492R – 33 – 050h 050h SHD B 050h 01 0 B C 050h 01 0 C D 050h 01 0 E Close 000h 00 3 E MODE Draft → Frame → Draft ∗ This chart is a drive timing chart example of electronic shutter normal operation. ∗ Data exposed at D includes blooming component. For details, see CCD image sensor specification. ∗ CXD2492R does not generate the pulse to control mechanical shutter operation. ∗ The switching timing of drive mode and electronic shutter data is not the same. 01 01 SMD 0 A 0 A Vertical Direction Sequence Chart MODE CCD OUT Exposure time Mechanical shutter SUB V4 V3B V3A V2 V1B V1A VD Chart-12 000h 00 3 E • ICX252 01 0 050h Open F Applicable CCD image sensor 050h 01 0 F CXD2492R CXD2492R Application Circuit Block Diagram V3A V3B V4 SUB ADCLK OBCLP CLPDM PBLK XRS 30 9 34 41 35 43 TG CXD2492R 39 44 4 5 CKO MCKO VD HD ID WEN V-Dr 46 2 RST 40 3 SNCSL 47 6 SSGSL 37 48 OSCI CKI OSCO 26 27 28 31 32 33 SEN V2 13 SCK V1B 25 SSI V1A D0 to 9 10 23 16 17 18 19 20 22 TEST2 RG A/D CXD2311AR 12 TEST1 H2 XSHD XSHP H1 DRVOUT VRT VRB S/H CXA2006Q Signal processor Block CCD OUT CCD ICX252 Controller Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes for Power-on Of the three –7.5V, +15.0V and +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential. 15.0V t1 20% 0V 20% t2 –7.5V t2 ≥ t1 – 34 – CXD2492R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 S 25 13 0.5 ± 0.2 B A 48 (8.0) 24 37 (0.22) 12 1 + 0.05 0.127 – 0.02 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 0.13 M 0.1 S 0.5 ± 0.2 (0.18) 0° to 10° DETAIL B:SOLDER DETAIL A 0.18 ± 0.03 0.127 ± 0.04 + 0.08 0.18 – 0.03 (0.127) +0.05 0.127 – 0.02 0.1 ± 0.1 DETAIL B:PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-48P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 35 –