CXG1053FN Power Amplifier/Antenna Switch + Low Noise Amplifier/Down Conversion Mixer for PHS Description The CXG1053FN is an MMIC consisting of the power amplifier, antenna switch, low noise amplifier and down conversion mixer. This IC is designed using the Sony's GaAs J-FET process featuring a single positive power supply operation. Features • Operates at a single positive power supply: VDD = 3V • Small mold package: 26-pin HSOF 26 pin HSOF (Plastic) Absolute Maximum Ratings <Power amplifier/antenna switch transmitter block > • Low current consumption: IDD = 150mA (POUT = 20.2dBm, f = 1.9GHz) • High power gain: Gp = 39dB Typ. (POUT = 20.2dBm, f = 1.9GHz) <Antenna switch receiver block/ low noise amplifier> • Low current consumption: IDD = 2.5mA Typ. (When no signal) • Low noise: NF = 2.7dB Typ. (f = 1.9GHz) <Down conversion mixer> • High conversion gain: Gc = 9dB Typ. (f = 1.9GHz) • Low distortion: Input IP3 = +1dBm Typ. (f = 1.9GHz) Applications Japan digital cordless telephones (PHS) <Power amplifier block> • Supply voltage VDD • Voltage between gate and source VGSO • Drain current IDD • Allowable power dissipation PD 6 V 1.5 550 V mA 3 W V <Switch block> Control voltage VCTL 6 <Front-end block> • Supply voltage • Input power VDD PRF 6 +10 <Common to each block> • Channel temperature Tch • Operating temperature Topr • Storage temperature Tstg V dBm 150 –35 to +85 –65 to +150 °C °C °C Structure GaAs J-FET MMIC Note on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99852-PS CXG1053FN Block Diagram and External Circuit 2.2nH PIN 14 13 15 12 (VGG1) 1kΩ VPCTL 100pF VDD1 1nF 18nH 16 11 17 10 VGG2 1nF 2.2nH VDD2 1nF 18nH 10nF 1.8nH VDD3 (POUT) 1pF 30pF 18 (TX) 9 30pF 19 VCTL1 8 100pF ANT 7 20 (RX) 30pF 30pF RFOUT 6 21 VCTL2 100pF 100pF (RFIN) 3.9nH 22 5 23 4 24 3 25 2 3.9nH 1.5nH 100pF 2.7nH VDD (RF AMP) 1nF 1nF 100nF VDD (IF AMP) RFIN (MIX) 18pF 26 1 56nH 1nF 8pF IFOUT Pin Configuration PIN 14 13 VGG1 GND 15 12 VPCTL VDD1 16 11 VGG2 VDD2 17 10 POUT VDD3 18 9 TX GND 19 8 VCTL1 RX 20 7 ANT VCTL2 21 6 GND RFIN 22 5 RFOUT/VDD (RF AMP) CAP 23 4 GND GND 24 3 RFIN (MIX) CAP 25 2 VDD (LO AMP) IFOUT/VDD (IF AMP) 26 1 LOIN –2– 1nF VDD (LO AMP) LOIN CXG1053FN Electrical Characteristics 1. Control Pin Logic for Antenna Switch Conditions of control pin ANT – TX ANT – RX VCTL1 = 3V, VCTL2 = 0V ON OFF VCTL1 = 0V, VCTL2 = 3V OFF ON 2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are when the Sony's recommended evaluation board with the external circuit shown on page 7 is used. Therefore, the power amplifier output pin (POUT) and the antenna switch transmission input pin (Tx) are connected via an external circuit. The specifications of the power amplifier block are set including the antenna switch transmitter block. Unless otherwise specified: VDD = 3V, VPCTL = 2V, VCTL1 = 3V, VCTL2 = 0V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz, Ta = 25°C Item Symbol Current consumption IDD Gate voltage adjustment value VGG Output power POUT Power gain GP Adjacent channel leak power ratio (600 ± 100KHz) ACPR600kHz Adjacent channel leak power ratio (900 ± 100KHz) Occupied bandwidth Measurement conditions Min. 0 Measured with the ANT pin Typ. Max. Unit 150 mA 0.25 20.2 36 0.6 V dBm 39 dB Measured with the ANT pin –63 –55 dBc ACPR900kHz Measured with the ANT pin –70 –60 dBc OBW Measured with the ANT pin 250 275 KHz 2nd-order harmonic level — Measured with the ANT pin –25 dBc 3rd-order harmonic level — Measured with the ANT pin –25 dBc –3– CXG1053FN 3. Antenna Switch Receiver Block + Front-end Block These specifications are when the Sony's recommended evaluation board with the external circuit shown on page 7 is used. Therefore, the antenna switch reception pin (Rx) and the low noise amplifier input pin (RFIN_LNA) are connected via an external circuit. The specifications of the low noise amplifier block are set including the antenna switch reception block. (a) Antenna switch receiver block + low noise amplifier block Unless otherwise specified: VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF = 1.9GHz/–30dBm, Ta = 25°C Item Symbol Current consumption IDD_LNA Power gain GP Noise figure NF Input IP3 IIP3 Isolation ISO Measurement conditions Min. When no signal 12.5 ∗1 Typ. Max. Unit 2.5 3.5 mA 14.5 16.5 dB 2.7 3.5 dB –11 –8 dBm 25 30 dB ∗1 Conversion from IM3 compression ratio during FR1 = 1.9000GHz/–30dBm and FR2 = 1.9006GHz/–30dBm input. (b) Mixer Block Unless otherwise specified: VDD = 3V, RF = 1.90GHz/–25dBm, LO = 1.66GHz/–12dBm, Ta = 25°C Item Symbol Measurement conditions Min. Typ. Max. Unit LO block current consumption IDD_LO When no signal 1.7 2.5 mA IF block current consumption IDD_IF When no signal 3.3 4.5 mA Conversion gain GC 9 11 dB Noise figure NF 8.5 11.5 dB Input IP3 IIP3 ∗2 LO to ANT leak PLK ∗3 7 –2 +1 –43 dBm –38 dBm ∗2 Conversion from IM3 compression ratio during FR1 = 1.9000GHz/–25dBm and FR2 = 1.9006GHz/–25dBm input. ∗3 The RFOUT pin of the LNA and the RFIN pin of the MIX block is connected directly with the cable. And the power supply of the LNA is turned on. (c) Total of (a) + (b) Item Current consumption Symbol IDD_total Measurement conditions When no signal –4– Min. Typ. Max. Unit 7.5 10 mA CXG1053FN Example of Representative Characteristics 15 –45 –50 POUT 10 –55 5 –60 ACPR600kHz 0 –65 –5 –40 –35 –30 –25 –20 –15 –70 –10 45 –40 Gp 40 35 –50 VDD = 3V, VPCTL = var., VGG = const., VTCL1 = 3V, VCTL2 = 0V IDD = 150mA (@VPCTL = 2V), PIN = var., POUT = 20.2dBm 30 25 –60 20 –65 15 0.0 VDD = var., VPCTL = 2V, VGG = const., VTCL1 = 3V, VCTL2 = 0V IDD = 150mA (@VDD = 3V, POUT = 20.2dBm), PIN = –19.2dBm –45 –50 POUT 20 –55 19 ACPR600kHz 18 17 2.0 –60 –65 2.5 3.0 3.5 4.0 1.0 1.5 2.0 2.5 –70 3.0 4.5 –70 5.0 Gp, ACPR600kHz vs. IDD 42 41 Gp – Power gain [dB] –40 ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT – Output power [dBm] 21 0.5 VPCTL – Gain control voltage [V] POUT, ACPR600kHz vs. VDD 22 –55 ACPR600kHz PIN – Input power [dBm] 23 –45 –40 VDD = 3V, VPCTL = 2V, VGG = var., VTCL1 = 3V, VCTL2 = 0V IDD = var., PIN = var., POUT = 20.2dBm –45 40 –50 Gp 39 –55 38 ACPR600kHz 37 36 100 VDD – Supply voltage [V] –65 120 140 160 180 200 IDD – Current consumption [mA] –5– –60 –70 220 ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT – Output power [dBm] 20 –40 VDD = 3V, VPCTL = 2V, VGG = const., VTCL1 = 3V, VCTL2 = 0V IDD = 150mA (@POUT = 20.2dBm), PIN = var. Gp – Power gain [dB] 25 Gp, ACPR600kHz vs. VPCTL ACPR600kHz – Adjacent channel leak power ratio [dBc] POUT, ACPR600kHz vs. PIN ACPR600kHz – Adjacent channel leak power ratio [dBc] 1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25°C) CXG1053FN 2. Antenna Switch Receiver Block + Low Noise Amplifier, Down Conversion Mixer (Ta = 25°C) SW/LNA block: POUT, PIM3 vs. PIN VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz VCTL1 = 0V, VCTL2 = 3V POUT –20 –40 –60 PIM3 –80 Input IP3 –100 –50 –40 –30 –20 –10 0 0 VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz LO = 1.66GHz/–12dBm POUT –20 –40 –60 –80 Input IP3 –100 –40 PIN – RF input power [dBm] –30 –20 –10 0 10 PIN – RF input power [dBm] MIX block: Gc, NF vs. PLO MIX block: Input IP3, PLK vs. PLO 10.0 12 2.0 9.5 11 1.5 –25 –30 Gc 9.0 10 8.5 9 NF Input IP3 [dBm] Input IP3 NF – Noise figure [dB] Gc – Conversion gain [dB] PIM3 1.0 0.5 8 7.5 7 –0.5 0.0 6 –1.0 –25 VDD = 3V, RF = 1.90GHz/small signal, LO = 1.66GHz –20 –15 –10 –5 0 PLO – LO input power [dBm] –40 PLK 8.0 7.0 –25 –35 –45 VDD = 3V, RF = 1.90GHz/–25dBm, LO = 1.66GHz VCTL1 = 0V, VCTL2 = 3V LNA output pin and MIX input pin is directly connected with the cable. –20 –15 –10 –5 PLO – LO input power [dBm] –6– –50 –55 0 PLK – LO to ANT leak level [dBm] 0 MIX block: POUT, PIM3 vs. PIN 20 POUT – IF output power, PIM3 – 3rd-order intermodulation power [dBm] POUT – RF output power, PIM3 – 3rd-order intermodulation power [dBm] 20 CXG1053FN Recommended Evaluation Board VGG PAIN ANT VPCTL VDD-PA VCTL1 RFOUT_LNA VCTL2 VDD_LNA IFOUT RFIN_MIX VDD_LO VDD_IF Glass fabric-base epoxy board (4 layers) Thinkness between layers 1 and 2: 0.2mm Dimensions: 50mm × 50mm LOIN Enlarged Diagram of External Circuit Block R1 C5 C6 C6 R1 = 1kΩ L3 L6 L6 C1 C6 C7 C4 L3 L2 C4 C5 C4 C4 C5 L5 L5 C5 L4 C6 C8 L1 C3 C5 C2 C6 L7 C6 –7– C6 L1 = 1.5nH L2 = 1.8nH L3 = 2.2nH L4 = 2.7nH L5 = 3.9nH L6 = 18nH L7 = 56nH C1 = 1pF C2 = 8pF C3 = 18pF C4 = 30pF C5 = 100pF C6 = 1nF C7 = 10nF C8 = 100nF CXG1053FN Package Outline Unit: mm HSOF 26PIN(PLASTIC) 0.08 0.45 ± 0.15 0.9 ± 0.1 S *5.6 ± 0.05 5.5 4.2 A 0.4 0.5 (1.5) (0.7) 4.4 ± 0.1 (1.75) 14 3.8 ± 0.05 26 13 1 0.4 S 4.4 0.2 0.2 0.07 M S A (0.2) 0.2 ± 0.05 + 0.05 0.2 0 Solder Plating B + 0.05 0.14 – 0.03 DETAILB NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.06g SONY CODE HSOF-26P-01 –8–