CXG1092N SP5T GSM Triple-Band Antenna Switch For the availability of this product, please contact the sales office. Description The CXG1092N is a high power antenna MMIC switch for use in triple-band GSM handsets. One antenna can be routed to either of the 2 Tx or 3 Rx ports. 20 pin SSOP (Plastic) Features • 4 CMOS compatible control lines • Standby control • 34.5dBm power handling at 5.0V (GSM900) • Low second harmonic < –36dBm at 34.5dBm • Small package size: 20-pin SSOP (6.4 × 5.0 × 1.25mm) Applications Triple-band handsets using combinations of GSM900/DCS1800/PCS1900 and DECT Structure GaAs J-FET MMIC (The Sony JFET process is used for low insertion loss.) Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD 7 • Control voltage • Operating temperature • Storage temperature Vctl Topr Tstg V 5 V –35 to +85 °C –65 to +150 °C Note on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99Z07-PS CXG1092N Truth Table On Pass GSM900 DCS1800 PCS1900 Rx ON STDBY Ant.-Tx1 GSM900 H L L L H Ant.-Tx2 GSM1800 L H L L H Ant.-Rx1 GSM900/1800/1900 H L L H H Ant.-Rx2 GSM900/1800/1900 L H L H H Ant.-Rx3 GSM900/1800/1900 L L H H H OFF — — — — L CMOS logic values (Ta = 25°C) Logic Min. Typ. Max. Unit High 2.4 2.8 3.2 V Low 0.0 0.4 V –2– CXG1092N Electrical Characteristics Item (Ta = 25°C) Symbol Port Condition Ant-Tx1, Tx2 Insertion loss IL Ant-Rx1, Rx2, Rx3 Ant-Tx1, Tx2 Isolation VSWR HarmonicsNote) ISO. Ant-Rx1, Rx2, Rx3 Typ. Max. Unit ∗1 0.6 0.9 dB ∗2 0.7 1.0 dB ∗3 0.6 0.9 dB ∗4 0.85 1.1 dB ∗5 0.9 1.15 dB ∗3 15 dB ∗4, ∗5 14 dB ∗1 18 dB ∗2 17 dB VSWR 2fo 3fo P1dB compression input power P1dB Control current Ictl Supply current Tx mode ITX Supply current Rx mode Leakage current Min. 1.2 Ant-Tx1, Tx2 ∗1, ∗2 –36 dBm ∗1, ∗2 –30 dBm Ant-Tx1 36 Ant-Tx2 35.5 dBm 170 µA STBY = H TxON = L 1 mA IRX STBY = H RxON = H 1 mA IIK STBY = L 100 µA ∗1 Pin 1 = 34.5dBm, 880 to 915MHz, VDD = 5.0V (GSM Tx) ∗2 Pin 2 = 32dBm, 1710 to 1910MHz, VDD = 5.0V (DCS & PCS Tx) ∗3 Pin 3 = 10dBm, 925 to 960MHz (GSM Rx) ∗4 Pin 4 = 10dBm, 1805 to 1880MHz (DCS Rx) ∗5 Pin 5 = 10dBm, 1930 to 1990MHz (PCS Rx) Note) Harmonics measured with Tx inputs harmonically matched. Sony recommends the use of harmonic matching to ensure optimum device performance Application Note (1). –3– CXG1092N Recommended Circuit (RRF) (RRF) 11 ANT Tx1 10 12 GND GND 9 13 GND Tx2 8 (∗1) (RRF) 14 VDD GND 7 15 GND Rx1 6 16 GSM900 CTL GND 5 17 DCS1800 CTL Rx2 4 18 PCS1900 CTL GND 3 Rx3 2 STDBY 1 19 RX ON 20 GND Recommended PCB Layout ∗ As indicated in the diagram AC coupling capacitors are necessary to the Ant, Tx1, Tx2, Rx1, Rx2 and Rx3 pins, and decoupling capacitors are necessary to the VDD, STDBY and CTL lines. ∗ The ground plane should be included under the device and all ground pins connected to this. ∗ RRF (200kΩ) is used to stabilize the electrical characteristics at the high power signal input. These resistors are required to ensure correct operation of the switch. ∗1 See Application Note (1). –4– CXG1092N Application Note (1) Impedance matching for harmonic minimization To achieve the 2nd harmonic levels lower than –36dBm for GSM900 Design of 1.8GHz harmonic matching network and the 900MHz trap network is dependent on the board design and components. 1800MHz Matching Network 900MHz Trap ANT 11 10 GND 12 9 GND GND 13 8 Tx2 VDD 14 7 GND GND 15 6 Rx1 GSM900 CTL 16 5 GND DCS1800 CTL 17 4 Rx2 PCS1900 CTL 18 3 GND RX ON 19 2 Rx3 GND 20 1 STDBY Tx1 LPF Application Note (2) Operating the CXG1092 from a 3V supply Technique Logic lines 200k Allows use of the CXG1092N (SP5T) in handsets with 3V min. battery voltage (2.7V SW supply). The CXG1092N is for 5V nominal battery voltage but work well down to 4V. Fundamentally, the 577µs time slot waveform is used to increase the 2.7V supply to over 4V. ∗ This waveform may be taken from the PA 200k Tx1 200k Tx2 Rx1 CXG1092N ANT ramping input (or drain supply in case of drain power control) or via the TX ON/OFF logic. Rx2 Rx3 C VDD D ∗ R Additional Components C: 0603 CAPS, few µF R: 200R D: Low Turn-on voltage diode VDD @2.7V 577µs –5– ≈ 4.0V D.C. Out C CXG1092N Package Outline Unit: mm 20PIN SSOP(PLASTIC) 0.1 ∗5.0 ± 0.05 1.25MAX A 20 S 6.4 ± 0.2 ∗4.4 ± 0.05 11 A 10 1 0.1 0.5 b 0.1 S 0.1 M S A 0° to 10° (0.2) DETAIL B : SOLDER b = 0.2 ± 0.03 + 0.03 0.15 – 0.01 0.6 ± 0.15 (0.5) 0.1 ± 0.1 (0.15) b = 0.22 ± 0.05 0.25 0.17 ± 0.03 B DETAIL B : PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE SSOP-20P-L03 LEAD TREATMENT EIAJ CODE SSOP020-P-0044 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE –6– Sony Corporation