CXG1125ER High Power 6 × 4 Antenna Switch MMIC with Integrated Control Logic for PDC Full Packet Description The CXG1125ER is a high power antenna switch MMIC for PDC dual 800MHz and 1.5GHz. This IC is suited to connect 2Tx/3Rx to one of 4 antennas equipped with full packet mode. The CXG1125ER has on-chip logic circuit for operation with 6 CMOS inputs. The Sony's GaAs J-FET process is used for low insertion loss and low voltage operation. 24 pin VQFN (Plastic) Features • Low insertion loss: 0.5dB @900MHz, 0.7dB @1.5GHz • High linearity: Harmonic < – 65dBc • CMOS compatible input control • Small package: 24-pin VQFN (4.0mm × 4.0mm) Applications 6 × 4 antenna switch for digital cellular such as PDC handsets Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD • Control voltage • Operating temperature • Storage temperature Vctl Topr Tstg 7 5 –35 to +85 –65 to +150 V V °C °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02112A25-PS CXG1125ER Block Diagram F1 Ext Tx800 F2 F14 F5 Tx1.5 F6 F24 Ant F3 F23 F15 GND5 F16 F4 Dup_Out F25 F7 F12 GND1 GND2 D_Ant Rx800D F10 F8 F26 F17 Rx800A F11 F18 F27 Rx1.5 GND3 GND4 F13 D_Ext F19 –2– CXG1125ER 12 11 CRF 9 8 GND2 Ext 10 GND CRF GND CRF Tx1.5 Tx800 Pin Configuration and Recommended Circuit 7 13 Dup_Out GND5 Rx800D Ant 6 CRF CRF 14 5 GND1 15 4 GND 16 3 CRF CTLA Cbypass 17 CTLB D_Ext CRF 2 Cbypass Cbypass 18 Rx800A CTLF 1 GND3/CTLE CRF D_Ant VDD 24 GND4 23 Cbypass Cbypass 22 CTLD CTLC Rx1.5 21 Cbypass 20 CRF 19 When using this IC, the following external components should be used: CRF: This capacitor is used for RF de-coupling and must be used for all applications. 100pF is recommended. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. –3– Cbypass CXG1125ER Truth Table A: Rx/Tx B: Main/diversity C: External/antenna D: 800MHz digital/800MHz analog E: 800MHz/1.5GHz F: TDMA/duplex State On Pass A B C D E F F1 F2 F3 F4 F5 F6 F7 F8 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F23 F24 F25 F26 F27 1 Tx800 – Ext H — L — L L H L L L L L L L L L L L L H L H L H H H L L L 2 Tx800 – Ant H — H — L L L H L L L L L L L L L L H L L H L H H H L L L 3 Tx1.5 – Ext H — L — H — L L L L H L L L L L L L L L H L H H H L L L L 4 Tx1.5 – Ant H — H — H — L L L L L H L L L L L L H L L L H H H L L L L 5 Rx800D – Ext L L L L L — L L H L L L L L L L L L L H L H L H L H H L L 6 Rx800A – Ext L L L H L — L L L L L L H L H L L L L H L H L H H H L L L 7 Rx1.5 – Ext L L L — H — L L L L L L H L L H L L L L H L H H H H L L L 8 Rx800D – Ant L L H L L — L L L H L L L L L L L L H L L H L H L H H L L 9 Rx800A – Ant L L H H L — L L L L L L L H H L L L H L L H L H H H L L L 10 Rx1.5 – Ant L L H — H — L L L L L L L H L H L L H L L L H H H H L L L 11 Rx800D – D_Ext L H L L L — L L L L L L L L L L L L H H L H L L H H L L H 12 Rx800A – D_Ext L H L H L — L L L L L L L L H L L H H H L H L L H H L L L 13 Rx1.5 – D_Ext L H L — H — L L L L L L L L L H L H H L H L H L H H L L L 14 Rx800D – D_Ant L H H L L — L L L L L L L L L L L L H H L L L H H H L H L 15 Rx800A – D_Ant L H H H L — L L L L L L L L H L H L H H L L L H H H L L L 16 Rx1.5 – D_Ant L H H — H — L L L L L L L L L H H L H L H L L H H H L L L H L L L L H L L H L L L L L L L L L L H L H L H L H H L L H L H L L H L L L H L L L L L L L L H L L H L H L H H L L H H L L L H L L H L L L L L L L L L L H L H L L L H L L H H H H L L H L L L H L L L L L L L L H L L L L H L H L H L 17 18 19 20 Dup_Out – Ext Rx800D – Ext Dup_Out – Ant Rx800D – Ant Dup_Out – Ext Rx800D – D_Ext Dup_Out – Ant Rx800D – D_Ant DC Bias Condition (Ta = 25°C) Item Min. Typ. Max. Unit VDD 2.7 3.0 3.3 V Vctl (H) 2.0 3.0 3.3 V Vctl (L) 0.0 0.4 V –4– CXG1125ER Electrical Characteristics Item Insertion loss (Ta = 25°C) Symbol IL State Port 1 Tx800 – Ext Condition ∗1 2 Tx800 – Ant 3 4 Min. Typ. Max. Unit 0.50 0.80 dB ∗1 0.55 0.85 dB Tx1.5 – Ext ∗2 0.70 1.00 dB Tx1.5 – Ant ∗2 0.70 1.00 dB 1.20 1.45 dB 5 Rx800D – Ext ∗3 , ∗7 6 Rx800A – Ext ∗3 1.25 1.55 dB 7 Rx1.5 – Ext ∗4 1.40 1.60 dB 8 Rx800D – Ant ∗3 , ∗7 1.20 1.45 dB 9 Rx800A – Ant ∗3 1.15 1.45 dB 10 Rx1.5 – Ant ∗4 1.35 1.55 dB 11 Rx800D – D_Ext ∗3 0.55 0.85 dB 12 Rx800A – D_Ext ∗3 1.00 1.30 dB 13 Rx1.5 – D_Ext ∗4 1.15 1.35 dB 14 Rx800D – D_Ant ∗3 0.65 0.95 dB 15 Rx800A – D_Ant ∗3 1.20 1.50 dB 16 Rx1.5 – D_Ant ∗4 1.35 1.55 dB Dup_Out – Ext ∗1 , ∗8 0.90 1.20 dB Rx800D – Ext ∗3 , ∗7 1.20 1.50 dB Dup_Out – Ant ∗1 , ∗8 0.95 1.25 dB Rx800D – Ant ∗3 , ∗7 1.25 1.55 dB Dup_Out – Ext ∗1 0.75 1.00 dB Rx800D – D_Ext ∗3 0.55 0.85 dB Dup_Out – Ant ∗1 0.80 1.10 dB Rx800D – D_Ant ∗3 0.70 1.00 dB 17 18 19 20 –5– CXG1125ER Item Isolation Symbol ISO. State Port 2 Tx800 – Ext ∗1 25 37 dB 1 Tx800 – Ant ∗1 25 39 dB 4 Tx1.5 – Ext ∗2 25 35 dB 3 Tx1.5 – Ant ∗2 25 30 dB 8 Rx800D – Ext ∗3, ∗7 25 37 dB 9 Rx800A – Ext ∗3 25 41 dB 10 Rx1.5 – Ext ∗4 25 51 dB 5 Rx800D – Ant ∗3, ∗7 25 39 dB 6 Rx800A – Ant ∗3 25 38 dB 7 Rx1.5 – Ant ∗4 20 26 dB 14 Rx800D – D_Ext ∗3 25 37 dB 15 Rx800A – D_Ext ∗3 25 38 dB 16 Rx1.5 – D_Ext ∗4 25 33 dB 11 Rx800D – D_Ant ∗3 25 33 dB 12 Rx800A – D_Ant ∗3 25 33 dB 13 Rx1.5 – D_Ant ∗4 25 37 dB Dup_Out – Ext ∗1, ∗8 25 37 dB Rx800D – Ext ∗3, ∗7 25 37 dB Dup_Out – Ant ∗1, ∗8 25 38 dB Rx800D – Ant ∗3, ∗7 25 38 dB Dup_Out – Ext ∗1 25 37 dB Rx800D – D_Ext ∗3 25 37 dB Dup_Out – Ant ∗1 25 41 dB Rx800D – D_Ant ∗3 25 33 dB 18 17 20 19 –6– Condition Min. Typ. Max. Unit CXG1125ER Item Symbol 2fo Harmonics 3fo ±50kHz ACP ±100kHz State Port 1 Tx800 – Ext ∗5 –75 –60 dBc 2 Tx800 – Ant ∗5 –78 –60 dBc 3 Tx1.5 – Ext ∗6 –70 –60 dBc 4 Tx1.5 – Ant ∗6 –75 –60 dBc 17 Dup_Out – Ext ∗5, ∗8 –72 –60 dBc 18 Dup_Out – Ant ∗5, ∗8 –74 –60 dBc 19 Dup_Out – Ext ∗5 –73 –60 dBc 20 Dup_Out – Ant ∗5 –76 –60 dBc 1 Tx800 – Ext ∗5 –72 –60 dBc 2 Tx800 – Ant ∗5 –71 –60 dBc 3 Tx1.5 – Ext ∗6 –70 –60 dBc 4 Tx1.5 – Ant ∗6 –70 –60 dBc 17 Dup_Out – Ext ∗5, ∗8 –75 –60 dBc 18 Dup_Out – Ant ∗5, ∗8 –74 –60 dBc 19 Dup_Out – Ext ∗5 –73 –60 dBc 20 Dup_Out – Ant ∗5 –72 –60 dBc 1 Tx800 – Ext ∗5 –67 –57 dBc 2 Tx800 – Ant ∗5 –66 –57 dBc 3 Tx1.5 – Ext ∗6 –67 –57 dBc 4 Tx1.5 – Ant ∗6 –65 –57 dBc 17 Dup_Out – Ext ∗5, ∗8 –66 –57 dBc 18 Dup_Out – Ant ∗5, ∗8 –67 –57 dBc 19 Dup_Out – Ext ∗5 –67 –57 dBc 20 Dup_Out – Ant ∗5 –67 –57 dBc 1 Tx800 – Ext ∗5 –74 –65 dBc 2 Tx800 – Ant ∗5 –74 –65 dBc 3 Tx1.5 – Ext ∗6 –73 –65 dBc 4 Tx1.5 – Ant ∗6 –72 –65 dBc 17 Dup_Out – Ext ∗5, ∗8 –74 –65 dBc 18 Dup_Out – Ant ∗5, ∗8 –73 –65 dBc 19 Dup_Out – Ext ∗5 –74 –65 dBc 20 Dup_Out – Ant ∗5 –73 –65 dBc –7– Condition Min. Typ. Max. Unit CXG1125ER Item P1dB Symbol P1dB Switching speed TSW Bias current IDD Control current Ictl State Port 1 Tx800 – Ext VDD = 3.0V 32 34 dBm 2 Tx800 – Ant VDD = 3.0V 32 34 dBm 3 Tx1.5 – Ext VDD = 3.0V 32 34 dBm 4 Tx1.5 – Ant VDD = 3.0V 32 34 dBm 17 Dup_Out – Ext 32 34 dBm 18 Dup_Out – Ant VDD = 3.0V, ∗8 VDD = 3.0V, ∗8 32 34 dBm 19 Dup_Out – Ext VDD = 3.0V 32 34 dBm 20 Dup_Out – Ant VDD = 3.0V 32 34 dBm ∗1 ∗2 ∗3 ∗4 ∗5 Condition Min. Typ. Max. Unit 2 5 µs VDD = 3.0V 1.3 1.8 mA Vctl (H) = 3V 40 70 µA Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 940MHz to 958MHz Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,429MHz to 1,453MHz Pin = 7dBm, 0/3V control, VDD = 3.0V, 810MHz to 885MHz Pin = 7dBm, 0/3V control, VDD = 3.0V, 1,477MHz to 1,501MHz π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 940MHz to 958MHz, ACP (±50kHz) < – 65dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 65dBc, 3rd harmonics < – 65dBc ∗6 π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,429MHz to 1,453MHz, ACP (±50kHz) < – 65dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 65dBc, 3rd harmonics < – 65dBc ∗7 Dup_Out port open ∗8 Rx800D port open –8– CXG1125ER Package Outline Unit: mm 24PIN VQFN(PLASTIC) 0.9 ± 0.1 4.0 0.6 ± 0.1 3.6 18 A 19 0.05 S 0.7 C 13 12 B 78 9) .3 (0 4. PIN 1 INDEX 24 ˚ 45 S x4 (0 .1 5) 6 0.4 C 1 0. 6 7 1.0 0.2 S A-B C x4 0.2 ± 0.01 0.03 ± 0.03 (∗1) (Stand Off) 0.05 M S A-B C 0.225 ± 0.03 0.2 S A-B C Solder Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 TERMINAL SECTION PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.04g VQFN-24P-03 SONY CODE LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SPEC. COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm –9– Sony Corporation