CXG1104TN High Power SPDT Switch with Logic Control Description The CXG1104TN is a high power antenna switch MMIC for use in cellular handsets, for example, CDMA. The CXG1104TN has on-chip logic, which enables the switch circuit to operate by 1 CMOS control line. The Sony JFET process is used for low insertion loss and on-chip logic circuit. 10 pin TSSOP (Plastic) Features • Low insertion loss: 0.3dB @900MHz, 0.4dB @1.9GHz • High linearity: IIP3 (Typ.) = 70dBm • 1 CMOS compatible control line • Small package size: 10-pin TSSOP Applications Cellular handsets, for example, narrow band CDMA and wide band CDMA Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD • Control voltage • Operating temperature • Storage temperature Vctl Topr Tstg 7 5 –35 to +85 –65 to +150 V V °C °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. The actual ESD test data will be available later. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00X23A2Z-PS CXG1104TN Block Diagram and Recommended Circuit Rctl (1kΩ) CTL Cbypass (100pF) GND 6 5 7 4 Cbypass (100pF) VDD RF1 CRF (100pF) GND 8 3 GND GND 9 2 GND 10 1 RF2 RF3 CRF (100pF) CRF (100pF) When using this IC, the following external components should be used: Rctl: This resistor is used to improve ESD performance. 1kΩ is recommended. CRF: This capacitor is used for RF decoupling and must be used for all applications. 100pF is recommended. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table On Pass CTL RF1 – RF2 L RF1 – RF3 H DC Bias Condition Item (Ta = 25°C) Min. Typ. Max. Unit Vctl (H) 2.0 3.0 3.6 V Vctl (L) 0 — 0.8 V 2.6 3.0 4.5 V VDD –2– CXG1104TN Electrical Characteristics Item (Ta = 25°C) Symbol Insertion loss IL Isolation ISO. VSWR VSWR Harmonics Condition Min. Typ. Max. Unit 900MHz 0.30 0.55 dB 1.9GHz 0.40 0.65 dB 900MHz 20 23 dB 1.9GHz 14 16.5 dB 2fo 900MHz, 1.9GHz ∗1 –60 –75 dBc 3fo ∗1 –60 –75 dBc 32 35 dBm 60 70 dBm 1dB compression input power P1dB Input IP3 IIP3 Switching speed TSW Control current Ictl Bias current IDD VDD = 3.0V, 0/3V control ∗2 1.2 1.4 — 2 5 µs Vctl (High) = 3V 40 80 µA VDD = 3V 100 200 µA ∗1 Pin = 29dBm, 900MHz, VDD = 3.0V, 0/3V control ∗2 Pin = 25dBm (900MHz) + 25dBm (901MHz), VDD = 3.0V, 0/3V control –3– CXG1104TN Unit: mm 10PIN TSSOP (PLASTIC) 1.2MAX ∗2.8 ± 0.1 0.1 10 + 0.15 0.1 – 0.05 0.45 ± 0.15 3.2 ± 0.2 ∗2.2 ± 0.1 6 5 1 0.5 + 0.08 0.22 – 0.07 0.1 0.25 0˚ to 10˚ M (0.1) + 0.025 0.12 – 0.015 A (0.2) + 0.08 0.22 – 0.07 DETAIL A NOTE: Dimension "∗" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.02g TSSOP-10P-L01 SONY CODE 10PIN TSSOP (PLASTIC) 1.2MAX ∗2.8 ± 0.1 0.1 10 6 + 0.15 0.1 – 0.05 0.45 ± 0.15 3.2 ± 0.2 ∗2.2 ± 0.1 5 1 0.5 + 0.08 0.22 – 0.07 0.1 0.25 0˚ to 10˚ M A (0.1) + 0.025 0.12 – 0.015 Package Outline (0.2) + 0.08 0.22 – 0.07 DETAIL A NOTE: Dimension "∗" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.02g TSSOP-10P-L01 SONY CODE LEAD PLATING SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm –4– Sony Corporation