High Power DPDT Switch with Logic Control CXG1188UR Description The CXG1188UR can be used in wireless communication systems, for example, CDMA handsets with GPS. The IC has on-chip logic for operation with 1 CMOS control input. The Sony J-FET process is used for low insertion loss and on-chip logic circuit. (Applications: Dual-band cellular handsets, CDMA with GPS, dual-band CDMA) Features Low insertion loss: 0.30dB@900MHz, 0.45dB@1900MHz High linearity: IIP3 = 65dBm (Typ.) 1 CMOS compatible control line Package Small package size: 12-pin UQFN Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) Bias voltage VDD 7 Control voltage Vctl 5 V V Operation temperature Topr –35 to +85 °C Storage temperature Tstg –65 to +150 °C This IC is ESD sensitive device. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E05465-PS CXG1188UR Block Diagram and Recommended Circuit RF2 RF3 GND CRF CRF 6 5 7 GND 4 3 F2 F3 GND F1 CRF CRF RF4 8 F4 9 GND RF1 2 1 10 11 12 GND CTL GND Cbypass (100pF) VDD When using this IC, the following external components should be used: CRF: This capacitor is used for RF decoupling and must be used for all applications. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table CTL ON state OFF state F1 F2 F3 F4 L RF1 – RF2, RF3 – RF4 RF2 – RF3, RF4 – RF1 ON OFF ON OFF H RF2 – RF3, RF4 – RF1 RF1 – RF2, RF3 – RF4 OFF ON OFF ON DC Bias Conditions (Ta = 25°C) Item Min. Typ. Max. Unit Vctl (H) 2.0 3.0 3.6 V Vctl (L) 0 — 0.4 V 2.7 3.0 3.6 V VDD -2- CXG1188UR Electrical Characteristics (Ta = 25°C) Item Symbol Insertion loss IL Isolation ISO. VSWR VSWR 2fo Harmonics 3fo Input IP3 IIP3 1dB compression input power P1dB Switching speed TSW Bias current IDD Control current Ictl *1 *2 *3 *4 Condition Min. Typ. Max. Unit 900MHz 0.30 0.55 dB 1.9GHz 0.45 0.70 dB 900MHz 18 21 dB 1.9GHz 14 16 dB 50Ω 1.2 — *1 –75 –60 dBc *3 –75 –60 dBc *1 –75 –60 dBc *3 –75 –60 dBc *2 55 65 dBm *4 55 65 dBm VDD = 2.8V 32 35 dBm 1 5 µs VDD = 3.0V 55 130 µA Vctl (H) = 3.0V 40 100 µA Pin = 25dBm, 0/3V control, VDD = 3.0V, 900MHz Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/3V control, VDD = 3.0V Pin = 25dBm, 0/3V control, VDD = 3.0V, 1.9GHz Pin = 25dBm (1.9GHz) + 25dBm (1.901GHz), 0/3V control, VDD = 3.0V Pin Description Pin No. Symbol Description 1 GND Control signal input 2 RF1 RF signal input 3 GND GND 4 RF2 RF signal output 5 GND GND 6 RF3 RF signal input 7 GND GND 8 RF4 RF signal output 9 GND GND 10 VDD Power supply input 11 GND GND 12 CTL Control signal input -3- CXG1188UR Package Outline (Unit: mm) 12PIN UQFN㧔PLASTIC㧕 x4 0.1 2.0 S C 0.4 ± 0.1 0.55 ± 0.05 غ0.6 9 A-B 4-R0.2 C 7 6 12 4 B 2.0 10 A 1 0.14 3 0.4 0.18 PIN 1 INDEX Thermal Die Pad 0.07 0.25 0.05 M S C A-B 0.05 S MAX0.02 S Solder Plating + 0.09 0.25 – 0.03 + 0.09 0.14 – 0.03 S TERMINAL SECTION PACKAGE STRUCTURE Note:Cutting burr of lead are 0.05mm MAX. PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.01g SONY CODE UQFN-12P-01 LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL -4- SPEC. COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm Sony Corporation