CXL1504M CMOS-CCD 1H Delay Line for NTSC Description The CXL1504M is a delay line used in conjunction with an external low-pass filter. Through negative phase input and positive phase output 1H delay time is obtained for NTSC signals. 20 pin SOP (Plastic) Features • Single 5V power supply • 14.3MHz driver • Low power consumption at 160mW (Typ.) • Built-in peripheral circuits • Completely adjustment free Functions • 905.5-bit CCD register • Clock driver • Autobias circuit • Input clamp circuit • Sample and hold circuit Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Voltage Range (Ta = 25°C) Supply voltage VDD 6 –10 to +60 –55 to +150 500 5 ± 5% Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 • Clock frequency fCLK 14.318182 • Input clock waveform sine wave V °C °C mW V Vp-p (0.5Vp-p typ.) MHz Input Signal Amplitude VSIG 560 mVp-p (Max.) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E71217A78-PS CXL1504M SUB NC NC VDD CLK VSS NC VDD NC VSS Block Diagram and Pin Configuration (Top View) 20 19 18 17 16 15 14 13 12 11 Pulse generation circuit Autobias circuit Clock driver φ1 Bias circuit (B) φS/H φ2 Output circuit, S/H circuit CCD (905.5bit) 8 9 10 VGGB 7 VSS 6 OUT 5 VGGA 4 VSS 3 VDD IS AB 2 IN 1 NC Bias circuit (A) Pin Description Pin No. Symbol I/O Description Impedance [Ω] 1 IS O CCD bias DC output 600 to 2k 2 AB O Autobias DC output 2k to 20k 3 NC — 4 IN I Signal input (Negative phase signal) > 100k (at no clamp) 5 VDD — 5V power supply (For clock driver) 6 VSS — GND 7 VGGA O Gate bias (A) DC output 2k to 10k 8 OUT O Signal output (Positive phase signal) 40 to 500 9 VSS — GND 10 VGGB O Gate bias (B) DC output 11 VSS — GND 12 NC — 13 VDD — 14 NC — 15 VSS — 16 CLK I 17 VDD — 18 NC — 19 NC — 20 SUB — 2k to 10k 5V power supply (For analog system) GND Clock input 4k to 50k 5V power supply (For digital system) GND –2– CXL1504M Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 14.318182MHz, VCLK = 500mVp-p, sine wave) See the Electrical Characteristics Test Circuits. Item Symbol Test conditions (Note 1) Bias conditions Min. 4 VBIAS1 [V] SW conditions 1 2 3 Typ. Max. Unit Note Supply current IDD — a a a — — 20 32 42 mA 2 Low frequency gain GL 200kHz, 500mVp-p, sine wave a a a b — –5.0 –3.0 –1.0 dB 3 Frequency response fr 200kHz ← → 3.58MHz, b 150mVp-p, c sine wave ← → a b b VIN – 0.2 –2.5 –1.3 0 dB 4 Differential gain DG 5-staircase wave (See Note 5) d a a c — 0 3 7 % 5 Differential phase DP 5-staircase wave (See Note 5) d a a c — 0 3 7 degree 5 S/H pulse coupling CP No signal input — b b a VIN — 200 350 mVp-p 6 S/N ratio S/N 50% white video signal (See Note 7) e a a d — 54 56 — dB 7 Notes 1) VIN is defined as follows. VIN is the input signal clamp level, it clamps the video signal sync tip level. CXL1504 4 Input (IN) Clamp level VIN Negative phase signal input VIN is the pin voltage for Pin 4 at no-input signal. Testing is executed with a voltmeter under the follwing SW conditions. Item VIN SW conditions Test point 1 2 3 4 — b a — V1 As VIN varies with each IC, they are all subject to testing. 2) IDD is the IC supply current value during clock and signal input. 3) GL is the OUT pin output gain when a 500mVp-p, 200kHz sine wave is input to IN pin. GL = 20 log OUT pin output voltage [mVp-p] 500 [mVp-p] [dB] –3– CXL1504M 4) Indicates the dissipation at 3.58MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 3.58MHz sine wave is fed to same, calculation is made according to the following formula. The input part bias is tested at VIN – 0.2V. fr = 20 log OUT pin output voltage (3.58MHz) [mVp-p] OUT pin output voltage (200kHz) [mVp-p] [dB] 5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure. below is input are tested at the vector scope. 143mV 357mV 500mV 143mV 1H 63.56µs IN pin input waveform is the inverted waveform in the figure above 6) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input part bias is tested at VINV. Test value (mVp-p) 7) S/N ratio during 50% white video signal input shown in figure. below is tested at a video noise meter, in BPF 100kHz to 4MHz, Sub Carrier Trap mode. 178mV 321mV 143mV 1H 63.56µs IN pin input waveform is the inverted waveform in the figure above Clock 4fsc (14.318182MHz) sine wave 0.3Vp-p to 1.0Vp-p (0.5Vp-p typ.) –4– –5– e d 5-staircase wave 50% white video signal SW1 c 3.58MHz 150mVp-p sine wave –1 b VBIAS1 b a SW3 1µ 51k SW2 V1 1M 1µ 1µ 2 3 4 3.3µ 1µ 1µ 20 SUB IS 1 19 NC AB 5 5V CXL1504M 18 NC NC VDD a 11 12 13 14 15 16 17 VDD IN 0.01µ 6 VSS b CLK 3.3µ VSS 10 14.3M –50 –50 6M Frequency [Hz] [dB] 0 –3 0 9 Note 1) LPF frequency response 8 1.2k 9V Note 2) × 3 BPF Note 1) × 3 LPF Noise meter Vector scope Spectrum analyzer OscilloOscilloscope scope 6M Frequency [Hz] 14.3M Note 2) BPF frequency response d c b a 0 200 SW4 [dB] 0 –3 7 VGGA 200kHz 150mVp-p sine wave 3.3µ 0.01µ NC 0.01µ VDD OUT a NC VSS 200kHz 500mVp-p sine wave 0.1µ CLK 4fsc (14.318182MHz) 0.5Vp-p sine wave VSS VGGB Electrical Characteristics Test Circuit CXL1504M Application Circuit Signal input (Negative phase signal) 1µ 1µ 1 20 –6– 3 18 1M 4 17 15 5 5V 0.01µ 6 CXL1504M 16 3.3µ 3.3µ 7 14 1µ 0.01µ 8 13 9 12 3.3µ 1µ 10 11 Transistor used PNP. 2SA1175 Signal output (Positive phase signal) 1.2k 9V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 1µ 2 19 0.01µ 0.1µ 14.318182MHz 0.5Vp-p sine wave CXL1504M CXL1504M Example of Representative Characteristics Frequency response vs. Supply voltage Low frequency gain vs. Supply voltage Frequency response [dB] Low frequency gain [dB] –1 –2 –3 –4 0 –1 –2 –3 –5 4.75 5.0 Supply voltage [V] 4.75 5.25 Differential gain vs. Supply voltage 5.0 Supply voltage [V] 5.25 Supply current vs. Supply voltage 40 10 Supply current [mA] Differential gain [%] 8 6 4 30 2 0 4.75 5.0 Supply voltage [V] 20 4.75 5.25 Low frequency gain vs. Ambient temperature 5.0 Supply voltage [V] Frequency response vs. Ambient temperature Frequency response [dB] Low frequency gain [dB] –1 –2 –3 –4 0 –1 –2 –3 –5 0 5.25 20 40 60 Ambient temperature [°C] 0 –7– 20 40 60 Ambient temperature [°C] CXL1504M Supply current vs. Ambient temperature Differentical gain vs. Ambient temperature 40 10 Supply current [mA] 6 4 30 3 0 0 20 20 40 60 Ambient temperature [°C] 0 20 40 60 Ambient temperature [°C] Frequency response 0 –2 Gain [dB] Differential gain [%] 8 –4 –6 –8 10k 100k Frequency [Hz] –8– 1M 10M CXL1504M Package Outline Unit: mm 20PIN SOP (PLASTIC) + 0.4 12.45 – 0.1 20 + 0.4 1.85 – 0.15 11 6.9 10 + 0.1 0.2 – 0.05 1.27 0.24 0.5 ± 0.2 1 0.45 ± 0.1 + 0.2 0.1 – 0.05 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-20P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP020-P-0300 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE –9–