CXL5506M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5506M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. CXL5506M 8 pin SOP (Plastic) CXL5506P 8 pin DIP (Plastic) Features • Single 5V power supply • Low power consumption 95mW (Typ.) • Built-in peripheral circuits Functions • 1130-bit CCD register • Clock driver • Auto-bias circuit • Input clamp circuit • Sample-and-hold circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5506M 350 mW CXL5506P 480 mW Structure CMOS-CCD Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) • Clock frequency fCLK 17.734475 MHz • Input clock waveform Sine wave Input Signal Amplitude VSIG 575mVp-p (Max.) (at internal clamp condition) AB VDD VG1 CLK Blook Diagram and Pin Configuration (Top View) 8 7 6 5 Auto-bias circuit Timing circuit Bias circuit Clock driver CCD (1130bit) Bias circuit (A) Output circuit Bias circuit (B) (S/H 1bit) VG2 3 4 VSS 2 OUT 1 IN Clamp circuit Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E90632B7X-PS CXL5506M/P Pin Description Pin No. Symbol Description I/O Impedance > 10kΩ at no clamp 1 IN I Signal input 2∗ VG2 I Gate bias 2 DC input 3 OUT O Signal output 4 VSS — GND 5 CLK I Clock input 6 VG1 O Gate bias 1 DC output 7 VDD — Power supply (5V) 8 AB O Auto-bias DC output 40 to 500Ω > 10kΩ 600 to 200kΩ ∗ Description of Pin 2 (VG2) Control of input signal clamp condition 0V ........ Sync tip clamp condition 5V ........ Center bias condition Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ). In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is 200mVp-p. Input waveform Clamp level –2– Output waveform CXL5506M/P Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 17.734475MHz, VCLK = 500mVp-p, sine wave) See "Electrical Characteristics Test Circuit" Item Symbol Test condition SW condition Max. Unit Note — 10 19 28 mA 1 a b –2 0 2 dB 2 b b –2 –1 0 dB 3 a a a Low frequency gain GL 200kHz, 500mVp-p, sine wave fR 200kHz ← → 4.43MHz, 150mVp-p, sine wave ←→ 3 IDD Frequency response Typ. 2 Supply current — Min. 1 b c Differential gain DG 5-staircase wave (See Note 4) d a c 0 3 5 % 4 Differential phase DP 5-staircase wave (See Note 4) d a c 0 3 5 degree 4 S/H pulse coupling CP No signal input f b a — — 350 mVp-p 5 SN 50% white video signal (See Note 6) e a d 52 56 S/N ratio — dB 6 Notes (1) This is the IC supply current value during clock and signal input. (2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. GL = 20 log OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] (3) Indicates the dissipation at 4.43MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 4.43MHz sine wave is fed to same, calculation is made according to the following formula. fR = 20 log OUT pin otuput voltage (4.43MHz) [mVp-p] [dB] OUT pin output voltage (200kHz) [mVp-p] –3– CXL5506M/P (4) In figure below, differential gain (DG) and differential phase (DP) are tested with a vector scope when the 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64µs Input waveform (5) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Test value (mVp-p) (6) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64µs Input waveform Clock 4fsc (17.734475MHz) sine wave 0.3 to 1.0Vp-p (0.5Vp-p typ.) –4– –5– 50% white video signal 5-staircase wave f e d c SW1 b 200kHz 150mVp-p sine wave 4.43MHz 150mVp-p sine wave a 200kHz 500mVp-p sine wave Electrical Characteristics Test Circuit 1µ 1000p 2 1 1M VG2 IN 7 VDD 8 AB 1µ 3.3µ 5V 6 1000p a 3 5 9V 2.1k –50 [dB] –50 17.7M d 0 –3 7M Frequency [Hz] b a SW3 c [dB] LPF frequency response Note 1) 4 VSS CLK 0.1µ 0 –3 b SW2 OUT VG1 1000p CLK 4fSC (17.734475MHz) 0.5Vp-p sine wave ×3 ×3 Noise meter Vector scope 200 7M 17.7M Frequency [Hz] BPF frequency response Note 2) BPF Note 2) LPF Note 1) Spectrum analyzer Oscilloscope CXL5506M/P –6– Input (Non-inverted signal) AA Application Circuit 1µ 5V 1M 1 8 1µ 3.3µ AA (Inverted signal) 3 6 10 560k 1µ 330k 1000p 1k 470 27p Delay time 190ns LPF 5V 2200 Transistor used NPN: 2SC2785 2200 2200 (ex. TH328LNLS-2620 Toukou made) Transistor used PNP: 2SA1175 4 5 0.1µ (Non-inverted signal) AA Output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 2 12 7 1000p 4fSC (17.734475MHz) 0.5Vp-p sine wave CXL5506M/P CXL5506M/P Example of Representative Characteristics Supply current vs. Ambient temperature Low frequency gain vs. Ambient temperature 2 Low frequency gain [dB] Supply current [mA] 30 20 10 –20 0 20 40 60 1 0 –1 –2 –20 80 0 Ambient temperature [°C] 20 40 60 80 Ambient temperature [°C] Frequency response vs. Ambient temperature Differential gain vs. Ambient temperature 10 0 Differential gain [%] Frequency response [dB] 8 –1 –2 6 4 2 –3 –20 0 20 40 60 0 –20 80 Ambient temperature [°C] Supply current vs. Supply voltage 40 60 80 Low frequency gain vs. Supply voltage 2 Low frequency gain [dB] Supply current [mA] 20 Ambient temperature [°C] 30 20 10 4.75 0 5 Supply voltage [V] 1 0 –1 –2 4.75 5.25 –7– 5 Supply voltage [V] 5.25 CXL5506M/P Frequency response vs.Supply voltage Differential gain vs. Supply voltage 10 0 Differential gain [%] Frequency response [dB] 8 –1 –2 6 4 2 –3 4.75 5 0 4.75 5.25 5 Supply voltage [V] 5.25 Supply voltage [V] Frequency response 2 Gain [dB] 0 –2 –4 –6 10k 100k 1M Frequency [Hz] –8– 10M CXL5506M/P Package Outline Unit: mm CXL5506M 8PIN SOP (PLASTIC) + 0.4 1.85 – 0.15 + 0.4 6.1 – 0.1 8 5 1 + 0.2 0.1 – 0.05 6.9 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 0.5 ± 0.2 4 + 0.1 0.2 – 0.05 0.45 ± 0.1 1.27 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-8P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP008-P-0300 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE CXL5506P + 0.3 6.4 – 0.1 + 0.4 9.4 – 0.1 5 7.62 8 + 0.1 0.05 0.25 – 8PIN DIP (PLASTIC) 0° to 15° 4 1 + 0.4 3.7 – 0.1 3.0 MIN 0.5 MIN 2.54 0.5 ± 0.1 1.2 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-8P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP008-P-0300 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.5g JEDEC CODE –9–